Features

* You can select 2, 3 or 4 phase operations, up to 1 mega -meter per phase

* Different sensing error exceeds the temperature exceeding the temperature ± 1%

* The logical grade PWM output of the external high -power driver interface

* The power current balance between all output phase [123 ]

* Built -in motivation Hao Dan Book

* Video code change

* 5 digits can be available. Programming 0.8 V to 1.55 V Output

* Able short -circuit protection

* Hold latency

*[ 123] Overvoltage Protective Clevey Logic Output Application

*

Power -type computer power supply

*

Next generation AMD processor

*

VRM module General description

ADP3166

is an efficient, multi -phase, synchronous anti -voltage switch stability The pressure controller is used to convert the 12V main power supply to the core power supply voltage required by high -performance AMD processors. It uses an internal 5 -bit DAC to read the voltage recognition (VID) code directly from the processor, which is used to set the output voltage between 0.8 V and 1.55 V. ADP3166 also uses a multi -mode PWM architecture to drive logic level output with a programmable switch frequency, which can optimize the size and efficiency of the VRM. The phase relationship of the output signal can be programmable to provide 2, 3 or 4 phase operations, allowing the constructing up to 4 complementary suppression and switches.

ADP 3166 includes a programmable air load offset and slope function, which adjusts the output voltage as a function of the load current, so that it is always in the best position of the system transient. The ADP3166 also provides precise and reliable short -circuit protection, adjustable current limit, and good output of delay power, which can adapt to the dynamic output voltage changes required by the CPU.

The commercial temperature range specified in ADP 3166 is 0 ° C to 85 ° C, which can be used in 28 lead TSSOP packaging.

Operation Theory

ADP3166 combined Multi-mode and fixed-frequency pulse width modulation multi-phase logic output control is used for 2, 3, and 4 Buck-CPU core power converters. Internal 5The PM vID DAC complies with AMD's Hammer series power specifications. Multi -phase operation is very important for the high current and low voltage required for the production of today's microprocessors. Handling high -current in a single -phase converter will generate high heat demand for the inductance and MOSFET in the system.

The multi -mode control of ADP3166 ensures

balanced current and calories between phases.

at a low -speed response at the lower switching frequency and output decoupling.

minimize the heat switch loss caused by low frequency operation.

Tighten the load line adjustment and accuracy.

high current output of 4 phase operations.

Use multiple aspects to cancel the reduction of the output ripple.

Due to independent component selection, it is easy to use and design.

flexible operation, can be designed according to low cost or high performance.

The number of phase

The number of working phase and its phase relationship is determined by the internal circuit output by the monitoring PWM. Generally, ADP 3166 works as a 4 -phase PWM controller. Ground pulse width modulation 4 pin program 3 phase operation, ground pulse width modulation 3 and pulse width modulation 4 pins program 2 phase operation.

When ADP 3166 is enabled, the controller outputs about 550 MV voltage on PWM3 and PWM4. The internal comparator checks the voltage of each pin based on a threshold of 400 millibolia. If the pin is ground, it will be lower than the threshold and the phase will be disabled. The output impedance of the pulse width modulation pin is about 5 kΩ. Any external drop -down resistance connected to the pulse width modulation pin should not be less than 25 kΩ to ensure normal work. Phase detection is performed during the first two clock cycles of the internal oscillator. After that, if the PWM output is not grounded, it will switch between 0V and 5V. If the PWM output is grounded, it will be disconnected.

PWM output is a logical -level device for driving an external gate drive, such as ADP3418. Because each stage is monitored independently, it is possible to run close to 100%. In addition, for the overlapping phase, multiple outputs can be opened at a time.

The clock frequency of the main hour clock

The clock frequency of ADP3166 is set by an external resistance from an RT pin. Frequency follows charts in TPC 1. To determine the frequency of each phase, the number of clocks is removed. If PWM4 is grounded, the main clock is removed by 3 as the remaining phase. If PWM3 and PWM4 are grounded, except 2. If all aspects are in use, divide by 4.

The output voltage differential dynamic response

ADP 3166 combines the difference sensor with high -precision VID DAC and benchmark and low offset error placing large. Keep the worst case specification of the ± 1%differential sensing error within the voltage and temperature range. The output voltage is induced between FB and FBRTN tube feet. FB should be connected to the adjustment node through a resistor, usually a remote sensor pin of the microprocessor. FBRTN should be directly connected to the remote sensing location. The internal VID-DAC and accuracy reference are referred to FBRTN. The minimum current of the FBRTN is 100 micro-security in order to perform accurate remote sensing. The internal error amplifier compares the output of the DAC with the FB pin to adjust the output voltage.

Output current influenza

ADP 3166 provides a dedicated current detection amplifier (CSA) to monitor the total output current to determine the correct position between the voltage and the load current, and perform it. Current limit detection. At the output end sensing load current, the total average current passed to the load. This is a method where the inherent ratio of the peak current detection or the sampling current by the sensing element (such as low -side MOSFET) is more accurate.

According to the different system goals, the amplifier can be configured in various ways:

no thermistor -free resistance output inductor ESR sensing, the lowest cost;

output inductor ESR sensor with a thermistor resistance improves the accuracy by tracking the temperature of the inductor;

the maximum accuracy measurement of the sensor.

The positive input of CSA is connected to the CSREF pin, and the CSREF pin is connected to the output voltage. The input of the amplifier is added from the sensor element (such as the opening point of the output inductor) to the resistance of the inverse input CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and the filter capacitance is placed in parallel with the resistor. The gain of the amplifier is programmable, and the load line required by the microprocessor is set by adjusting the feedback resistor. Then give the current information as the difference between CSREF -CSCOMP. The differential signal is used internally for VID DAC for offset positioning for voltage positioning, and is used as a differential input of a current limitation comparator.

In order to provide the best accuracy for the current sensing, CSA was designed to have a low offset input voltage. In addition, the sensor gain is determined by the external resistance, so it can make it very accurate.

Active impedance control method

In order to control the dynamic output voltage drop as a function of the output current, the signal zoom of the total output current at the foot of the CSCOMP tube can be equal to the regulator. During the resistance to passenger to the output current. Then use the lower voltage to set the input control voltage of the system. Reference to losing directly from DACThe drooping voltage is reduced in the voltage to tell where the output voltage of the error amplifier should be. This is different from the previous implementation and allows enhanced feedback responses.

Voltage control method

The voltage mode control loop adopts a high -gain bandwidth voltage mode error amplifier. The control input voltage of the positive input is set according to the voltage listed in Table I through the VID 5 -bit logical code. The voltage is also offset by the active positioning of the active positioning of the output voltage of the current function (usually called an active voltage positioning). The output of the amplifier is the COMP tube foot, which sets the termination voltage of the internal PWM slope.

Negative input (FB) is connected to the output detection position through a resistor RB to detect and control the output voltage at this time. The current source from the FB foot flowing by RB is used to set the air load offset voltage from the VID voltage. The air load voltage is positive relative to VID DAC. The main circuit compensation is added to the feedback network between FB and COMP.

Soft starting

The power -powered slope time of the output voltage is set by a capacitor and a resistor parallel, from a delayed pins to grounding. The RC time constant also determines the current limitation of the lock -up closing time, as described in the following section. When UVLO or EN is low logic, delayed feet to keep on the ground. After reaching the UVLO threshold and EN as the logic, the delayed electric container is charged by the internal 20μA current source. The output voltage follows the slope voltage on the feet to limit the surge current. The soft start time depends on the values of VID-DAC and CDLY, and RDLY will have a secondary impact. For more information about setting CDLY, see the application part.

When the PWRGD threshold is reached, the soft start cycle stops, and the delayed feet are pulled up to 3V. This ensures that when PWRGD sends a signal with good output voltage to the system, the output voltage is in the VID voltage. If the EN value is too low or VCC drops below the UVLO, the delayed power container is reset to ground to prepare another soft startup loop.

Flowing short circuit protection

ADP3166 compares the programmable current limit settings with the voltage on the output of the current detection amplifier output at the CSCOMP pin. The level of the current limit is set by the resistance from Ilimit to the ground. During normal operation, the voltage on Ilimit is 3V. The current of the external resistor is zoomed in the interior to give the current limit threshold of 10.4mV/μA. If the voltage difference between CSREF and CSCOMP drops below the current limit threshold, the internal current limit amplifier will control the internal COMP voltage to maintain the average output current at the limit.

After reaching the limit, disconnect 3V on the feet, and external delay capacitors are powered by external resistance. The comparator monitor the delay voltage and turn off the controller when the voltage drops below 1.8V. Therefore, current limitation atresiaThe delay time is set from RC time constant setting from 3V to 1.8V. The application part discusses the choice based on the selected CDLY.

Since the controller continues to circulate phase within the time of the lock closing delay time, if the short circuit is eliminated before reaching the 1.8 V threshold, the controller will return to normal work. The recovery feature depends on the state of PWRGD. If the output voltage is in the PWRGD window, the controller will return to normal work. However, if the short circuit causes the output voltage to drop below the PWRGD threshold, the soft start cycle is started.

By unloading VCC and re -applied to ADP3166, or reserved the lock lock to close the locks through a short period of time. To disable the short -circuit atresia closing function, the external grounding resistance should be kept open, and a large (greater than 1 MΩ) resistor should be connected from VCC to delay. This can prevent delay capacitors from discharging, so it will never reach the 1.8V threshold. The resistor will affect the soft start time, because the current through its current will increase to the internal 20 Weian current source.

During the startup process, when the output voltage is lower than 200 millivolves, the secondary current limit activation. This is necessary because the voltage of CSCOMP cannot be lower than the ground. This secondary current limit controls the internal COMP voltage to the 2V of the PWM comparator. This will limit the voltage drop of the low -voltage side MOSFET through a current balanced circuit.

Dynamic voltage identification

ADP3166 has the function of dynamically changing the video input when the controller is running. This allows the output voltage when the power supply is running and providing a current to the load. This is usually called flying video (OTF). VID-OTF can occur under light or heavy load conditions. The processor changes the VID input from multiple steps from the beginning to the end code to send a signal to the controller. This change can be positive or negative.

When VID input changes, ADP3166 detected the change and made DAC blank at least 400 ns. This time is to prevent error code due to logic distortion when the six VID inputs change. In addition, the first VID changes to start the PWRGD to eliminate the anti -faint function at least 100 microseconds to prevent fake PWRGD incidents. Each time the video is replaced, the internal timer will be reset.

Good power monitoring

Good power comparator monitors the output voltage through the CSREF pin. The PWRGD tube foot is an open leakage output, which indicates that the output voltage is within the nominal limit specified in the previously set regulation according to the VID voltage. If the output voltage exceeds this specified range, PWRGD will become lower. During the VID-OTF incident, PWRGD was blocked 100 microseconds to prevent fake signals from appearing during the output change.

Output crowbar

For part of the load and output component protection of the power supply, when the output voltage exceeds the upper limit of the good threshold of the power, the PWM output is driven low (open the low side MOSFET), and the Crowbar logical output becomes high. If there are no other faults, once the output voltage falls to the scope of the technical specifications, the lever action will be released. The release threshold is about 400 mv.

Open the low -side MOSFET will reduce the output with the increase of the reverse current in the inductance. If the output over -voltage is caused by short circuit of the high -voltage side MOSFET, the action current limits the input power supply or the fuse of the fuse, thereby protecting the microprocessor from damage.

Pry rod output can be used to send signals to the outside input pry rod or other protective circuits.

Output enable and UVLO

Input VCC must be higher than the UVLO threshold, EN PIN must be higher than its logical threshold, so that ADP3166 starts switching. If the UVLO is less than the threshold or EN PIN is low, the ADP3166 is disabled. This will keep the PWM output on the ground, make the delayed capacitor short -circuit on the ground, and keep the Ilimit pin on the ground.

In the application circuit, the Ilimit pin should be connected to the OD pin of the ADP3418 drive. Because ILIMIT is grounded, this will disable the driver program so that DRVH and DRVL are grounded. This feature is very important for the output capacitor discharge when the controller is prevented. If the drive output is not disabled, the output capacitor may generate negative voltage on the output because the output capacitor is discharged through the high current.

Application information

The design parameters of typical AMD K8 compatible CPU applications are as follows:

input voltage (vin) 12 v

VID setting voltage (VVID) 1.500 V

occupy the duty ratio (d) 0.125

maximum static output voltage error (± vSERR) ± 50 mv

maximum dynamic output voltage error (± vrederr) ± 70 mv

controller and ripple allowed error voltage (± vrerr) ± 20 millivck

Maximum output current (IO) 56 A

maximum output current jump (IO) 24 A

[

[ 123] Static output reduction (RO) is based on:

a), set the air load output voltage limit at the upper output end.

vonl vvid+vSERR –Verr 1.5303

B), low output full -load output voltage limit.

vofl VVID – Verr+Verr 1.470 volts

RO (vonl --vofl)/(IO) (1.530 volts -1.470 volts)/ (56A) 1.1 mΩ

dynamic output resistance (stick) Based on:

a), the output current with the output voltage jumps to the empty load setting in the output dynamic voltage The upper limit.

VONLD VVID+VDERR –Verr 1.550 volts

B), the output voltage before load changes (at IOUT IO).

VOL vonl - (IO RO) 1.504 volts

pole (vonld --vol)/(IO) (1.550 v – 1.504 V)/(24A) 1.9 MΩ

phase (n) 3

123] Set the clock frequency

ADP3166 adopts a fixed frequency control architecture. The frequency is set by an external timer resistor (RT). The clock frequency and phase determine the switching frequency of each phase, which is directly related to the switch loss and inductance, and the input and output capacitance size. For the clock frequency of the three -phase n 3,990 kHz, set the switch frequency FSW of each phase to 330 kHz, which means the actual balance between the switch loss and the size of the output filter component. Figure 1 shows that the frequency of oscillator of 990 kHz is required, and the correct value of RT is 200 kΩ. Or, you can use:

Among them, 5.83 PF and 1.5 MΩ are internal IC components.

In order to obtain good initial accuracy and frequency stability, 1%resistance is recommended.

软启动和电流限制闭锁关闭延迟时间

由于软启动和电流限制闭锁-关断延迟功能共享延迟管脚，这两个The parameters must be considered together. The first step is to set CDLY for the soft start slope. The slope is generated by an internal current of 20 μA. The value of RDLY will have a second -order impact on the soft start time because it sinks part of the current source to the ground. However, as long as RDLY remains greater than 200kΩ, this impact is very small. The value of CDLY can be used:

Among them, TSS is the required soft start time. Suppose RDLIt is 390kΩ, the required soft start time is 3ms, and the CDLY is 36NF.

The closest standard value of CCS is 39NF. Once you select CDLY, you can use:

If the result of RDLY is less than 200 kΩ, you should consider the smaller soft start time by re -calculating the formula of the CDLY, or Use a longer lock time. In any case, it should not be less than 200 kΩ. In this example, the delay of 8 ms makes RDLY 402 kΩ. The closest standard 5%value is 390 kΩ.

Selection of sensors

The choice of inductance and inductance determines the ripple current in the inductance. The smaller the inductance, the larger the ripple current generated, which will increase the output ripple voltage and conduction loss of MOSFET, but allows the use of smaller dimensions of inductance, and for the specified peak-peak transient deviation, the total output capacitance is smaller Essence In contrast, higher inductance means lower ripple current and lower conduction loss, but for the same peak-peak transient deviation, a larger inductance size and larger output capacitance are required. Among any multi -phase variables, the practical value of the electromotive peak ripple current is less than 50%of the maximum DC current in the same inductor. Formula 4 shows the relationship between inductance, oscillator frequency, and inductance. Formula 5 can be used to determine the minimum inductance according to the given output ripple voltage:

Formula for solving 10 MV P-P output ripple voltage 5

If the ripple voltage is smaller than the designed ripple voltage, the inductance can be smaller until the ripple value meets the requirements. This will allow the best transient response and minimum output decoupling.

You should use as much inductors as possible to minimize the number of output capacitors. A 600 mAh inductor is a good starting point, which gives 6.6 A computing ripple current. The inductance should not be saturated at the peak current of 22 A, and it should be able to process the sum of power consumption caused by the average current and magnetic core loss of 18.7 A in the winding.

Another important factor in inductive design is to measure the DCR of phase current. Large DCR will cause excessive power loss, and too small DCR values will cause measuring error. A good rule is that DCR is about 1 to 1/2 times of static drooping resistor (RO).

In our example, we use DCR an inductors of 1.6 MΩ.

Design inductor

Once the inductance and DCR are known, the next step is either designing an inductance or finding a standard inductance to get as close as possible to achieve the overall design goal. In order to ensure the accuracy of the control system, specifying the inductance and DCR tolerance is also important. Use 20%inductance and 8%DCR (at room temperature) is a reasonable tolerance that most manufacturers can meet.

The primary decision of the inductor design is to choose the magnetic core material. There are many possibilities for providing low -iron heart loss at high frequency. Two examples are powdery magnetic cores (for example, Kool-Mμ or micro-metal) and gap soft iron oxygen core (eg, 3F3 or 3F4 from Philips). Low -frequency iron powder iron core loss, especially when the electrical sensing value is low, and the ripple current is large, it should be avoided as much as possible.

The best choice of core geometric body is a closed -loop type, such as POT core, PQ core, U core, and E core or ring. A good compromise between price and performance is a magnetic core with a ring shape.

Output reduction

Design requirements When the output current increases, the voltage voltage measurement voltage measured at the CPU pin decreases. The specified voltage drop corresponds to static output reduction (RO).

The output current is measured by adding the voltage on each inductor, and then measured by a low -pass filter. This summer filter is a CS amplifier with resistance RPH (X) (summer) and RCS, and CCS (filter). The output resistance of the regulator is set by the following square, where RL is the DCR of the output inductance:

One can flexibly select RCS or RPH (x). It is best to choose RCS equal to 100kΩ, and then solve the RPH (x) by re -arranging equation 6.

Next, use Formula 6 to solve CCS:

It is best to have a dual position of a CCS in the layout , So that the standard value can be used in parallel to get as close to the required values as possible. For this example, choosing CCS as 1.5NF and 2.2NF is a good choice. In order to obtain the best accuracy, CCS should be a 10%capacitor. The closest standard of RPH (X) is 147 kΩ.

DCR temperature correction of inductance

Taking the DC resistance of inductance as a sensitive element, the copper wire is the DC resistance source, and the temperature changes of the inductor winding need to be compensated. Fortunately, copper has a well -known temperature coefficient (TC) of 0.39%/℃.

If the resistance change of the RCS is the opposite and equal percentage of the resistance of the wire, it will offset the temperature changes of the inductor DCR. Due to the non -linear characteristics of NTC thermistor, resistance RCS1 and RCS2 (see Figure 2) need to be used to linearize NTC and generate the required temperature tracking.

The following procedures and expressions will produce RCS1, RCS2, and RTH (thermist resistance values at 25 ° C) for given RCS values (thermistor values at 25 ° C)value.

1. Select NTC according to the type and value. Because we don't have a value, we start with a thermistor near RCS. The initial tolerance of NTC should also be greater than 5%.

2. According to the type of NTC, find out its relative resistance values at two temperatures. The good work temperature is 50 ° C and 90 ° C. We call these resistance values a (a (A 50 ° C)/RTH (25 ° C)) and B (B are RTH (90 ° C)/Rth (25 ° C)). Note that at 25 ° C, the relative value of NTC is always 1.

3. Next, find the relative value of the RCS required for each temperature. This is based on the required percentage changes, and we initially set it to 0.39%/℃. We call these R1 (R1 as 1/(1+T1-25)), and R2 (R2 is 1/(1+TC (T2-25))), of which TC 0.0039, T1 50 ° C, T2, T2 90 ° C.

4. Use the relative value of calculation of RCS1, RCS2 and RTH:

5. Calculate Rth Rth RCS, then select available heat At the same time, calculate the zoom coefficient K:

6. Finally The values of RCS1 and RCS2:

In this example, RCS is selected as 100kΩ, so we start from a 100kΩ armistor. By viewing the existing 0603 0603 In the type of thermistor, we found that Visha NTHS0603N01N01N1003JR NTC thermistor A 0.3602 and B 0.09174. From this we calculate RCS1 0.3796, RCS2 0.7195, and RTH 1.0751. K 0.9302. Finally, we found that RCS1 and RCS2 are 35.3kΩ and 73.9kΩ, respectively. Select the closest 1%resistance value to get 35.7 kΩ and 73.2 kΩ. 123] AMD's specifications In the case of air load, the nominal output voltage of the regulator should be offset to the value that is higher than the nominal voltage corresponding to the VID code. The constant current source setting of the RB. The value of the RB can be found through Formula 11:

The recent standard 1%resistance value is 2.00 kΩ.

COUT selection

AMD is usually recommended for various placesThe output of the regulator of the mission and the platform. You can also use some simple design rules to determine what you need. The basis of these guidelines is to use large capacitors and ceramic capacitors at the same time in the system.

First, the total amount of ceramic capacitors should be selected according to the number and type of the capacitor used. The best position of ceramics is in the socket. Others can also be placed along the outer edge of the socket.

It is recommended to use a ceramic combination value of 30 to 100 micro F, which is usually composed of multiple ceramic capacitors. Select the number of ceramics and calculate the total ceramic capacitor (CZ).

Secondly, when the flight voltage of the output is considering the VID (the voltage in the time TV tv enters the VV, the error is VERR), there is an upper limit for the total volume electricity capacity (CX), and it is based on satisfaction. The lower limit of the load release of the maximum load step:

to meet the satisfaction of satisfying The conditions of these expressions and transient response, ESR of the large -capacity capacitor group (RX) should be less than or equal to dynamic dynamic sag resistor ROD. If CX (min) is greater than CX (MA), the system will not meet dynamic video specifications, and may need to use smaller inductors or more phase (and may need to increase the switching frequency to keep the output ripples the same).

In our example, the combination of MLCC capacitors (CZ 50 μF). Within 100 μs, the dynamic video jump change from 1.5 V to 0.8 V (to VV 700 MV), and the setting error is 3%.

Solution of body capacitance production:

type k 3.5.

820 μF oscillator with 8 typical ESRs is 12 MΩ, each oscillator produces CX 6.56 mf, and RX 1.5 MΩ.

The last inspection should ensure that the ESL of the large -capacity capacitor (LX) is low enough to limit the initial high -frequency transient peak. This is:

In this example, for 8 OSCON capacitors, LX is 375 pH, which basically meets this limit. If the LX of the large -capacity capacitor group is too large, the number of capacitors must be increased.

It should be noted that for this multimodal control technology, as long as the conditions of equation 12, 13, and 14 are met, you can use all ceramic design.

Power gold oxygen semi -electrode crystals

In this example, each phase selects a high -voltage side switch and two N -channel power MOSFETs with two low -voltage side switches. The main selection parameters of the power MOSFET are VGS (TH), QG, CISS, CRSS, and RDS (on). SmalleThe pole -drive voltage (ADP3418 power supply voltage) indicates that the standard threshold or logical level threshold MOSFET must be used. When VGATE ~ 10V, it is recommended to use a logical flat threshold MOSFET (VGS (TH) lt; 2.5V).

The maximum output current IO determines the RDS (on) requirements of the low -end (synchronous) MOSFET. In ADP3166, the current is balanced between the phase, so the current in each low side MOSFET is the total number of MOSFETs (NSF) of the output current. In the case of leading losses, the following expression shows the total power consumption of each synchronous MOSFET in each phase -patterned wave current (IR) and average output current (IO):

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