Features

* Maximum sampling rate: 65msps

* 12 -bit resolution without lack of code

]* Power Consumption: 996MW

* CMOS technology

* Simultaneous sampling and maintaining

* 10 MMC medium frequency 70.5 decibel signal -to -noise ratio

* Internal and external reference

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3.3V digital/simulation power supply [123 [123 ] *

Serialized LVDS output

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Integrated frame and synchronization mode

* MSB and LSB No. 1 No. 1 One mode

* Double LVDS clock output current option

* Cup and format series

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TQFP-80 power board #63722; component Application

* Portable ultrasonic system

* Tape of the tape The machine

* Test equipment

*

Light Network

ADS5272 [123

] It is a high -performance, 65MSPS, 8 -channel parallel modulus converter (ADC). Provided internal reference and simplified system design requirements. Low power consumption allows the highest system integration density. The output of the serial LVDS (low -voltage differential signal) reduces the number and packaging size of the interface line.

The integrated lock ring will take the input ADC sampling clock to 12 times. This 12x clock is used to output the data of each channel in serialized. The 12X clock is also used to generate 1X and 6X clocks. These two clocks are sent as the LVDS clock output. The 6X clock is expressed by differentials to LCLKP and LCLKN, and the 1x clock is expressed by Adclkp and Adclkn. The word output of each ADC channel can be sent as MSB or LSB first. The position that coincides with the 1x clock output rising along is the first place of the word. The data will be locked by the receiver on the edge of the 6X clock.

ADS5272 provides internal reference, or you can choose to use external reference drivers. The best performance can be obtained through internal reference mode.

This device can be used in the TQFP-80 power board component and in -40 ° C to +85Specify within the scope of the ° C.

The serial interface time

The data is first shifted in MSB.

LVDS timing diagram (each ADC channel)

Reset timing

[123 ]

Power off timing

Operation theory

Overview

ADS5272 is an 8 -channel high -speed CMOS ADC. It consists of a high -performance sampling maintenance circuit and a 12 -bit ADC. The 12 bits given by each channel are serialized and sent in a pair of tube feet in the LVDS format. All eight channels of ADS5272 run from a clock called ADCLK. Each of the sample clock in the eight channels is generated using a carefully matched clock buffer tree from the input clock. The 12X clock required by the serializer is generated from the inside of the ADCLK. A 6X and a 1x clock also output in LVDS format, together with data to facilitate data capture. ADS5272 The reference voltage produced by the internal is used to fine -tune them to ensure that it is matched between multiple devices on a board. This characteristic eliminates the needs of the external wiring of the reference line, and also improves the matching of the gain between the device. The nominal values of REF and Ref are 2V and 1V, respectively. These values mean that the -1V differential input corresponds to the zero code of ADC, while the+1V differential input corresponds to the full standard code (4095 LSB). V (REF and Ref's co -mode voltage) can also be obtained from the outside through pins, nominal 1.5V.

ADC adopts a pipeline converter structure composed of multiple and internal units. Each level feeds its data to the digital error correction logic to ensure that it has excellent differential lineivity and no leakage code at the 12 -bit level. The assembly line structure causes the data delay of the 6.5 clock cycle.

The output of ADC enters a serial, which starts working from the 12X clock generated by PLL. Twelve data bits from each channel are serialized and first send LSB. In addition to serialized data, the serialization program also generates 1X clock and 6X clock. The generation of these clocks is the same as the generation method of serialized data, so these clocks maintain a perfect synchronization with the data. The data and clock output of the serialization program use the LVDS buffer for external buffer. The use of LVDS buffer to transmit external data has many advantages, such as reducing the number of output pipes (saving the wiring space on the board), reducing power consumption, and reducing the impact of digital noise coupling to ADS5272 internal analog circuits.

ADS5272 is powered by two sets of power and grounding devices. Analog electricityThe source/ground device is represented by AVDD/AVSS, and the digital device is represented by LVDD/LVSS.

Drive analog input

The simulation input bias is shown in Figure 1. The recommended driver input method is to be coupled by AC. AC coupling eliminates the concerns of setting the co -mode of the driving circuit because the input input uses two 600Ω resistor bias.

The sampling capacitor used for sampling input is 4PF. The choice of external AC coupling containers depends on the attenuation at the minimum expected input operating frequency. The attenuation of 10NF AC coupling capacitors was 0.04%.

If the input is DC coupling, the output co -mode voltage response of the circuit of the ADS5272 circuit is matched with V (as an output pins), which is within the range of ± 50mv. It is recommended that the output of the driving circuit derives the V provided by the device.

The sampling circuit is composed of a low -pass RC filter at the input terminal to filter the noise component of the differential coupling at the input terminal. Enter the samples on two 4PF capacitors, as shown in Figure 2. The sampling on the capacitor is performed according to the internal co -mode voltage (INCM). Connect the sampling capacitor to the switch of INCM first (before connecting it to the switch of analog input). This ensures that the charge injection caused by the switching degree has nothing to do with the input signal amplitude similar to the first order. SP refers to the sampling clock that is reached before the sampling clock. The decline of SP determines the sampling moment.

Enter overvoltage recovery

ADS5272 supported by the differential full -standard full -standard input peak voltage is 2V. For the nominal value V (1.5V), the voltage of the input and input terminal can be swinged from 1V to 2V. ADS5272 is specifically designed to process the overvoltage differential peak voltage for 4V (the voltage of the input and input terminals is 2.5V and 0.5V, respectively). If the input co -mode is not obviously disconnected from V during the overload (less than 300mV), the recovery of overvoltage input conditions is expected to be within 4 clock cycles. All amplifiers in SHA and ADC are designed specifically for good recovery from overload signals. Nmpm n -centimeter n cm

Reference circuit design

Digital beam formation algorithm to a large extent depends on the gain matching of all receiving channels. There are about 12 octagonal ADCs on a typical system board. In this case, it is important to ensure that gain matching, which basically requires the same reference voltage that all ADCs see. The matching reference in the eight channels of the chip is completed by using an internal reference voltage buffer. Adjust the reference voltage on each chip during the production process to ensure that the reference voltage on different chips is well matched.

All bias currents required for the internal operation of the device are set through the external resistor and areET is grounded. Use 56kΩ resistor on Iset to generate an internal reference current of 20 Weire. This current is in the internal mirror to generate the bias current of the internal block. Using larger external resistance at ISET can reduce the reference bias current, thereby reducing the working power of the device. However, it is recommended that the external resistance is within 10%of the specified value of 56K to make the internal bias hameness of each piece appropriate.

The buffer internal bandwap voltage also generates a voltage called V. The voltage is set to the intermediate level of Ref and Ref and can be accessed on PIN. The internal buffer driver V has a driver of ± 2mA. It refers to exporting the reference voltage of the input co -mode when the input is directly coupled.

When using the internal reference mode, the resistance should be added between the reference pins (REFT and Refb) and the decoupled capacitor, as shown in Figure 3.

This device also supports the use of external reference voltage. This model involves compulsory external REF and Ref. In this mode, the internal reference buffer is three -state. Because the switching current of the eight ADC comes from the external compulsory benchmark, its performance may be slightly lower than the performance when using the internal benchmark. It should be noted that in this mode, V and ISET continue to be generated by the internal gap voltage, just like in the internal reference mode. Therefore, it is important to ensure that the co -mode voltage of the external compulsory reference voltage matches the V in 50mv.

Time

Eight channels on the chip input through an ADCLK. In order to ensure that the aperture and jitter of all channels are the same, the clock tree network is used to generate a separate sample clock for each channel. The clock path of all channels has been matched from the source to sampling and maintenance. This ensures that the performance of all channels is the same as timing. The clock tree is used to match the pore diameter delay, that is, the delay between the rising edge of ADCLK and the actual sampling moment. The pore delay of all channels is matched, and the change range between the devices is 2.5ns to 4.5ns. Another key feature is the aperture jitter, which is defined as the uncertainty of the instantaneous sample. The design of the door in the clock path makes the RMS jitter about 1PS.

Ideally, the input ADCLK should have a 50%duty ratio. However, when the ADCLK routing to different components on the ship, the duty cycle to the ADCLK of ADS5272 may be deviated from 50%. The smaller (or larger) duty cycle consumes the available time of the samples or maintenance of each circuit, so it is not the best. Therefore, the internal PLL is used to generate an internal clock with a duty cycle of 50%.

PLL uses a lower operating frequency of automatic indication is about 20MHz.

LVDS buffer

The LVDS buffer has two current sources, as shown in Figure 4. OUTP and OUTNThe resistance of about 100Ω is loaded outside. According to data from 0 or 1, the current is guided to another direction of the resistor. There are four current settings of the LVDS buffer. The default current is set to 3.5mA, and a differential voltage drop of about ± 350mV is generated on the 100Ω resistor.

The LVDS buffer obtains data from serialized program. This serialization program obtains output data from each channel and sequences sequences into a single data stream. For the clock frequency of 40MHz, the data rate output by serials is 480Mbps. Data first output LSB, and the register is programmed as MSB first. The serialization program also provides a 1x clock and a 6X clock. The 6X clock (indicated as LCLK/LCLK) is used for synchronous LVDS data capture. You can also use the register to set the deskew mode. This mode gives a data stream alternately 0 and 1, which can be used to determine the relative delays between the 6X clock and the output data to achieve the best capture. The serials also generate a 1x clock and transmitted by the LVDS buffer. The 1x clock (referred to as adclk/adclk) is used to determine the beginning of the 12 -bit data frame. The data given by the synchronization mode (enabled by the register) is 6 0S 6 1s. Using this mode, the 1x clock can be used to determine the beginning of the data frame. In addition to the Deskew mode and the sync mode, users can also define custom mode and output from the LVDS buffer.

Noise coupling problem

High -speed hybrid signal is very sensitive to various noise coupling. One of the main sources of noise is the switch noise from serializer and output buffer. Pay special attention to isolation of these noise sources from sensitive simulation elements. As a starting point, the simulation domain and digital domain of the chip are clearly divided. AVDD and AVSS are used to represent the power supply of the analog part, while LVDD and LVSS are used to represent digital power. Pay attention to ensure the least interaction between the power group in the equipment. The degree of noise from the digital part to the simulation part depends on the following items:

1. The effective inductance of each power/ground device.

2. The isolation between numbers and simulation power/grounding device.

The smaller the effective inductance of the power/ground pins, the better the noise suppression effect. Therefore, multiple pins are used to drive each power/ground. It is also necessary to ensure that the impedance of the power supply and ground wire on board remains at the possible minimum value. In the circuit board, the use of ground planes and large -scale counter -coupled power containers between the power cord and the ground wire is necessary to obtain as well as as much as possible from the device.

It is recommended to use separate power to drive AVDD and LVDD, as well as LVDD and AVSS and LVSS separate ground planes to keep the ship isolation.

Compared with the CMOS buffer, the use of LVDS buffer greatly reduces injection noise. LVDSThe current in the buffer has nothing to do with the direction of the switch. In addition, low output swing and the differential characteristics of the LVDS buffer cause low noise coupling.

Power failure mode

ADS5272 has a power -off led foot, PD. Raising PD will cause the device to enter the power -off mode. In this mode, the benchmark and clock circuit and all channels are powered off. In this mode, the power consumption of the equipment has dropped below 100 MW. A single channel can also be selected by programming registers.

ADS5272 also has an internal circuit to monitor the state of the clock. If ADCLK stops (or runs below 3MHz), this monitoring circuit will generate a logical signal to make the device in a state of power off. Therefore, when ADCLK stops, the power consumption of the device will be less than 100MW. This circuit can also be used to use register options.

Supply order

It is recommended to supply power in the equipment in the following power supply:

1. AVDD has been powered on.

2. LVDD has been power -on.

After the power supply is stable, the device needs to be given an effective reset pulse. This will cause all internal registers to be reset to its silent value 0 (non -activity). If not reset, some registers may be in a non -default state when power -on. This may cause equipment failure.

PCB layout with PowerPad thermal packaging

ADS5272 packaged in a 80 -drawing PowerPad thermal enhancement package. In order to maximize the use of the thermal efficiency design in PowerPad packaging, the design of PCB must take into account this technology. See SLMA004 PowerPad Brief PowerPad Make Easy (see our website website), which solves the specific precautions required to collect PowerPad into PCB design.

Packaging information