General description

lmc662 CMOS dual operation amplifier is a single power operation. The working voltage from+5V to+ 15V is also available with rail -to -orbit output width and inputs that include grounding. The limitations of performance that troubles the CMOS amplifier in the past is not the problem of this design. Enter VOS, drift and broadband noise and actual load voltage gain (2 kΩ and 600 ω) are equal to or better than the bipolar equivalent that is widely accepted. This chip is a national advanced bisodiacum CMOS process. Four CMOS operations are seen in the LMC660 data table with the same function amplifier.

Features

Rail output amplitude

Specifying for 2 kΩ and 600Ω load

High -voltage gain: 126 decibel

Low input offset voltage: 3 MV

Low offset voltage drift: 1.3 Micro volt/degrees Celsius

Ultra -low input bias current: 2Fa

Input common modular range includes included in the total modular range includes V # 8722 from+5V to+15V power supply; n working range

ISS 400 μA/amplifier; independent V+

Low low Distortion: 0.01%at 10 kHz

conversion rate: 1.1V/microsecond

It can be used within the extension temperature range (-40 ° C to+125 ° C; it is very suitable for car applications [ 123]

It can be used for standard military drawing specifications

Application

High impedance buffer or front placement large

Precision current voltage converter

Long -term for a long time Pointer

Sampling maintenance circuit

Peak detector

Medical Device

Industrial control

Automotive sensor

Absolute maximum rated value (Note 3)

Differential input voltage ± power voltage

Power supply voltage (V+-V-)) 16 volts [ 123]

Output to V+short circuit (Note 12)

output to V-short circuit (Note 1)

Lead temperature

(welding, 10 seconds) [123) [123) [123) [123) ] 260

Celsius

Storage temperature. Temperature range -65 ° C to+150 ° C Input/output pin voltage (V+)+0.3 volts, (伏-)-0.3 volts

output pin current ± 18 milliligoAnn

Input pin current ± 5 mAh

Power pins 35 mAh current

Power consumption (Note 2)

Nack temperature 150

303C

ESD tolerance (Note 8) 1000V

Working value (Note 3)

Temperature range

lmc662amj/883 ,

LMC662AMD 55 ° C ≤TJ≤+125 ° C

lmc662ai 40 degrees C ≤TJ ≤+85 degrees C

lmc662c 0 00 ○ C≤TJ≤+70 ○ ○ ○ C

lmc662e 40 ° C ≤TJ≤+125 ° C

Power voltage range 4.75V to 15.5V

Power Consumption (Note 10)

Thermal resistance (θja) (Note 11)

8 -needle ceramic leaching 100 ° C/W

8 -pin mold pressure DIP 101 ° C /W

8 -needle SO 165 ° C/W

8 -needle side surface 钎 welding ceramic leaching 100 ° C/w

DCTability

Unless Another regulation, otherwise all the limits of TJ 25 degrees Celsius. Black body limit is suitable for extreme temperature. V+ 5 volts, V- 0V, VCM 1.5V, VO 2.5V, RL GT; 1M, unless there are other regulations.

DC Power Texability (continued)

Unless there are other regulations, all the limits of TJ 25 degrees Celsius are guaranteed. Black body limit is suitable for extreme temperature. V+ 5 volts, V- 0V, VCM 1.5V, VO 2.5V, RL GT; 1M, unless there are other regulations.

AC electrical characteristics (continued)

Note 1: Applicable to single power and division of power operations. The continuous short -circuit operation of the increase in ambient temperature and/or multiple computing amplifiers may cause a maximum allowable permission temperature to be 150 ° C. Long -term output current exceeding ± 30 mA can adversely affect reliability.

Note 2: The maximum power consumption is the functions of TJ (MAX), θJa, and TA. The maximum allowable power consumption at any ambient temperature is pd (TJ (MAX) – TA)/θJa.

Note 3: Absolutely maximum rated value indicates the limit where the device may be damaged. When the working rated value indicates that the device is in a state, the device tends to work normally, but it does not guarantee specific performance restrictions. For the specifications and test conditions of the guarantee, please refer to the electricityQi special. This guarantee specification is only applicable to the test conditions listed.

Note 4: Typical values represent the most likely parameter model. The limit is guaranteed by testing or association.

Note 5: V+ 15V, VCM 7.5V, RL connected to 7.5V, source pole test 7.5V ≤VO ≤ 11.5V, sinking test 2.5V ≤VO ≤ 7.5V.

Note 6: V+ 15V. As a voltage follower connection, there is a 10V step input. The specified number is the slower in the positive and negative conversion rate.

Note 7: Reference input. V+ 15V and RL 10kΩ are connected to V+/2. Each amplifier is motivated in sequence at a frequency of 1kHz to generate VO 13VPP.

Note 8: Human model, 1.5 kΩ connects 100 PF.

Note 9: Military RETS electrical test specifications can be provided according to the requirements. When printing, the LMC662AMJ/883 RETS specification fully meets the limits in this column of the black body. LMC662AMJ/883 can also be purchased in accordance with standard military drawing specifications.

Note 10: For equipment running at high temperatures, the heat resistance θja must be reduced according to the thermal resistance θja of PD (TJ -TA)/θJa.

Note 11: All numbers are suitable for packaging directly welded to the PC board.

Note 12: When V+greater than 13V or reliability may be adversely affected, do not connect the output to V+.

Unless there are other regulations, typical performance characteristics vs ± 7.5V, TA 25 ℃

Unless otherwise regulations, typical performance characteristics vs vs ± 7.5V, TA 25 ° C (continued)

Program prompt

The topology of the amplifier is LMC662 (Compared with the universal computing amplifier) Do not use the traditional unit gain buffer output stage; on the contrary, the output is obtained directly from the output of the input integror to allow rail -to -rail output swing. Because of the tradition of the buffer, in maintaining the gain and stability of the high -transportation amplifier, it is necessary to bear whether the railway must be able to withstand the railway. These tasks are now responsible for the integrator. Due to these requirements, the integrator is an event in the phase of a complex and an embedded gain. This stage is a dual -feed (CF and CFF) compensate the driver through a dedicated unit gain. In addition, the output part of the integral device is push -pull configuration for transporting heavy objects. When the entire amplifier path of the absorption current is the stage of obtaining first -level feedback, the source path contains four gain stages and two FED forward places. The large signal voltage gain at the source is comparable to traditional bipolar computing amplifiers, even if there are 600Ω load. The gain at the time of sink is higher than that of most CMOS operations amplifiers to additionalThe gain stage; however, the gain (600Ω) gain will be reduced, as shown in electrical diagrams.

Application prompt (continued)

compensation input capacitance LMC662 operational amplifier's high input resistance allows large feedback and source resistance values, not will not, not will not be The gain accuracy is reduced due to load. However, the circuit will be particularly sensitive to its layout when these large value resistors are used. Each amplifier has some capacitors between each input end and the difference capacitors between the grounding and the input end. When the amplifier is resistant, the input capacitor (and the additional capacitor sockets generated by the circuit board traces, etc.) and the feedback resistor are on the feedback path. In the general operation amplifier circuit below, Figure 2, the frequency of this pole is

Including the amplifier input capacitance and any bandate capacitors from IC sockets (if used) RP is a parallel combination of RF and RIN. This formula, as well as all the formulas below, is suitable for vertical and non -inverse operational amplifiers configuration. The frequency of feedback poles when the feedback resistance is less than a few KΩ, because CS is generally less than 10 PF. If the frequency of the feedback is much higher than the ideal " closed -loop bandwidth (the nominal closed -loop bandwidth of the CS)