Features

* members of the PIN compatible TXDAC product series

125 MSPS update rate

* 10 -bit resolution

* Excellent and non -messy dynamic range performance

* SFDR to nyquist@40 mHz output: 52 DBC

* Differential current output: 2 mia to 20 mAh

* Power consumption: 175 MW@5 volts to to 45 MW@3 volts

* Power off mode: 25 mw@5 v

*

The reference voltage on the film [ [ 123]

*

单电源+5V或+3V供电操作

*

封装：28铅SOIC和TSSOP边缘触发闩锁应用[ 123]

Communication transmission channel: base station; set -top box; digital radio link; direct digital synthesis (DDS); instrument.

Product description

AD9760

and AD9760-50 are 10-bit resolution members of the TXDAC series of high-performance, low power CMOS digital modular converter (DAC). AD9760-50 is a low-performance option that guarantees and specifies for 50 MSPS operations. The TXDAC series consists of 8, 10 -bit, 12 -bit, and 14 -bit DAC, which is optimized specifically for the transmission signal path of the communication system. All device shares the same interface options, small shape packaging and pins, thereby providing a path -based upward or down component to select the path of performance, resolution, and cost. Both AD9760 and AD9760-50 provide excellent communication and DC performance, while supporting the update rate of up to 125 and 60 MSPs, respectively.

AD9760's flexible single power supply range is 2.7V to 5.5V, and low power consumption is very suitable for portable and low power consumption applications. Its power consumption can be further reduced to only 45MW, and the performance decreases significantly because it reduces the full -size current output. In addition, the power loss mode reduces the standby power consumption to about 25 mW.

AD9760 is made of advanced CMOS technology. The structure of the segmented current source is combined with the proprietary switching technology to reduce the bruises and improve the dynamic performance. Edge trigger input locks and 1.2V temperature compensation band gap benchmark integration, providing a complete single -chip DAC solution. Flexible power options support+3V and+5V CMOS logic series.

AD9760 is a current output DAC, the nominal full standard output current is 20 mAh, and the output impedance is greater than 100 kΩ. Provide different dynamic current outputs to support single -ended or differential applications. The matching between the two current outputs ensures that the dynamic performance is enhanced in the differential output configuration. The current output can be directly connected to the output resistor to provide two complementary single -end voltage outputs or directly fed into the transformer. The output voltage conforms to 1.25V.

Reference and control amplifier configuration on the film to the maximum accuracy and flexibility. The AD9760 can be driven by the reference voltage or various external reference voltage. The internal control amplifier provides a wide ( gt; 10: 1) adjustment range that allows the AD9760 full -standard current to adjust the range of more than 2 mAh to 20 mia, while maintaining good dynamic performance. Therefore, the AD9760 can work at a reduced power level, or can be adjusted within the 20DB range to provide additional gain ranging capabilities.

AD9760 offers 28 lead SOIC and tssop encapsulation. It is stipulated in the industrial temperature range.

Product Highlights

1.AD9760 is a member of the TXDAC product series. It provides a path -based resolution (8 to 14 digits), performance and cost up or down components.

2.AD9760 is made of CMOS process, and the proprietary switching technology is used to improve dynamic performance, exceeding the performance that previous high power/cost bipolar or BICMOS devices can be achieved.

3. On the chip, the edge triggers the input CMOS lock interface is prepared to be+3V and+5V CMOS logic families. AD9760 can support a update rate of up to 125 MSPS.

4. The flexible single power supply range is 2.7 volt to 5.5 volts, and the wide -scale standard current adjustment range of 2 mAh to 20 mAh allows AD9760 to work at a reduced power level.

The current output of 5.AD9760 can be easily configured to various single -end or differential circuit topology.

规范的定义

线性误差（也称为积分非线性或INL）

线性误差定义为实际模拟输出与The maximum deviation of the ideal output is determined from a straight line from zero to full scale.

Differential non -linearity (or DNL)

DNL is the measurement of the simulation change, standardization into a full standard, which is related to the 1LSB change of the digital input code.

monotonicity

If the output increases or remains unchanged with the increase in digital input, the modulus converter is monotonous.

The offset error

The deviation of the output current and the ideal zero point is called partialMovement error. For iOuta, when all inputs are 0, the expected output is 0 mA; for iOUTB, when all inputs are set to 1, the expected output is 0 mAh.

gain error

The difference between the actual output range and the ideal output range. The output value of the actual range from the output value when all input set to 1s minus all input settings when the output value is set to 0s.

The output conforms to the range

The voltage range allowed by the output end of the current output digital modulus. Operations exceeding the maximum soft limit may cause the output level saturation or failure, resulting in non -linear performance.

Temperature drifting

The temperature drift is specified as the maximum change from the environment (+25 ° C) to the TMIN or TMAX value. For offsetting and gain drift, the drift is reported by PPM with a PPM of the full -scale bidding range (FSR) per degree Celsius. For reference drift, the drift is reported by the unit PPM.

Power suppression

When the power supply changes from the rated voltage to the minimum and the maximum regulatory voltage, the maximum change output is output.

Settlement time

Starting from the output conversion, the output reaches and maintains the time required for the specified error zone of its final value.

Failure pulse

Asymmetric switching time in DAC will generate output transients that are not expected, these transients can be quantized by fault pulses. It is specified as the net area of the fault in PV-S.

There is no mixed dynamic range

The difference between the output signal between the output signal and the peak mixed signal on the specified bandwidth, the unit is decibel.

Total harmonic distortion

THD is the ratio of the average root value of the average root roots of the first six harmonic components and the measured output signal. It is represented by percentage or decibel (DB).

+5V's typical AC characteristic curve

(avdd +5 v, dvdd +5 v, IOUTFS 20 mAh, 50 50, 50, 50, 50 Double -end load, differential output, TA +25 c, until Nyquist's sfdr, unless there is another instructions).

Function description Figure 39 shows the AD9760 of AD9760 showing the AD9760 Simplify the box diagram. The AD9760 consists of a large PMOS current source array, which can provide a total current of up to 20 mAh. The array was divided into 31 equal currents, forming 5 maximum valid positions (MSB). The next 4 or middle position consists of 15 equal current sources, and its value is 1/16 of the MSB current source. The remaining LSB is medianThe binary score of the current source. The use of a current source instead of the R-2R trapezoid diagram to achieve a low level, which improves the dynamic performance of multi-sound or low amplitude signals, which helps maintain high output impedance of DAC (that is, gt; 100kΩ).

All these current sources are switched to one or other in two output nodes (ie, iOUTA or IOUTB) through PMOS differential current opening. These switches are based on a new architecture, which greatly improves distortion performance. This new switching structure reduces various timing errors, and provides a matching complementary driving signal for the input of the differential current switch.

The analog and digital part of AD9760 have independent power input (ie AVDD and DVD), which can work independently within 2.7 volts to 5.5 volts. The number part is composed of the edge trigger the lock memory and segmented decoding logic circuit, which can work at a clock rate of 125 MSPS. The simulation part includes PMOS current sources, related differences with switches, 1.20V band gap benchmark voltage sources and benchmark control amplifiers.

Full marking output current is adjusted by the reference control amplifier, and can be set to 20 mA from 2 mAh from 2 mia through the external resistance RSET. The external resistance, combined with the reference control amplifier and voltage reference VREFIO, sets the reference current Iref, the Iref is mirrored to the segmented current source with an appropriate proportional factor.

Full marking current iOutfs is 32 times the Iref value.

DAC transmission function

AD9760 provides complementary current output, iOuta and IOUTB. IOUTA will provide a current output close to the full -scale, iOUTFS, when all bits are high (ie DAC code 1023), and iOUTB, complementary output, does not provide current. The current output that appears at iOuta and IOUTB is a function of input code and iOutfs, which can be expressed as:

where DAC code 0 to 1023 (that is, decimal representation).

As mentioned earlier, iOUTFS is a function of reference current IREF, which is nominally set by reference voltage, VREFIO and external resistance RSET. It can be expressed as:

The two current outputs are usually directly or pass through the transformer to drive the resistor load. If you need DC coupling, iOuta and iOUTB should directly connect to the matching resistance RLOAD connected to the simulated public line ACOM. Note that RLOAD can indicate iOUTA or iOUTB in the two -terminal 50Ω or 75Ω cables. Single -end voltage output that appeared in iOuta and iOUTB nodes is simple:

Note: The full standard value of VOUTA and VOUTB should not exceed the prescribed regulationsThe output is conforming to the scope to maintain the specified distortion and linear performance.

The differential voltage VDIFF appearing on iOuta and IOUTB is:

Replace the values of iOuta, iOutb, and Iref; VDiff can be expressed as:

The last two equations highlight some advantages of the AD9760 differential operation. First, the differential operation will help eliminate the co -mode error source associated with iOuta and iOUTB, such as noise, distortion, and DC offset. Secondly, the differential current and subsequent voltage VDiff are twice the single -end voltage output value (ie, VOUTA or Voutb), thereby providing twice the signal power for the load.

Note that single -ended gain drift temperature performance

AD9760 (vouta and voutb) or differential output (VDiff) can be enhanced by selecting temperature tracking resistors for RLOAD and RSET, because their The ratio relationship is as shown in equivalent 8.

Reference operation

AD9760 contains an internal 1.20 V gap benchmark, which can be easily disabled and covered by external benchmarks. Refio is used as input or output, which depends on whether internal reference or external reference. If Reflo is connected to ACOM, as shown in Figure 40, the internal reference is activated, Refio provides 1.20 V output. In this case, the internal benchmark must be compensated from Refio from REFIO to REFLO with 0.1 μF or larger ceramic capacitors. In addition, if any additional load is required, Refio should use an external amplifier with a bias current of less than 100NA for buffer.

By connecting Reflo to AVDD. In this case, external reference can be applied to Refio, as shown in Figure 41. External benchmarks can provide fixed reference voltage to improve accuracy and drift performance, or provide variable benchmark voltage for gain control. Note that because the internal benchmark is disabled, 0.1 μF compensation capacitors are required, and the high input impedance (ie 1 MΩ) of Refio minimize any load of the external benchmark.

Reference control amplifier

AD9760 also contains an internal control amplifier to regulate the DAC's full standard output current iOUTF. As shown in Figure 41, the control amplifier is configured as a V-I converter, so its current output Iref is determined by the ratio of VREFIO and external resistance RSET, as described as equal 4. Iref is copied to the segmented current source and uses appropriate proportional factors to set iOUTF, as described as equal 3.

The control amplifier allows width (10: 1) to adjust the Iref between 62.5 micro -security between 62.5 micro -peace, and iOutf is within the range of 2 mAh to 20 mia. The wide adjustment range of iOutf provides several application advantages. The first benefit is directly related to the power consumption of AD9760, which is proportional to iOutf (see the power consumption part). The second advantage is the adjustment of 20 decibels, which is the purpose of the beneficial system gain control.

The small signal bandwidth of the control amplifier is about 1.4MHz, and it can be reduced by connecting external capacitors between COMP1 and AVDD. The output of the control amplifier COMP1 is for internal compensation through 50PF capacitors. The capacitor restricts controls the small signal bandwidth of the amplifier and reduces its output impedance. Any additional external capacitance further limits the bandwidth and acts as a filter to reduce the noise contribution from the reference amplifier. FIG. 42 shows the relationship between external capacitors and reference amplifiers-3DB bandwidth. Since the -3DB bandwidth corresponds to the main point of the main point, time constant, the stable time of controlling the amplifier to reference input response can be approximate.

By installing 0.1 μF external capacitors, you can get the best distortion performance of any reconstruction waveform. Therefore, if Iref is fixed for a certain application, it is recommended to use 0.1 μF ceramic chip capacitors. In addition, because the control amplifier is optimized for low -power operations, the multiplication application of large signal swinging should consider using external control amplifiers to enhance the overall signal multiplication bandwidth and/or distortion performance of the application.

There are two ways to change the IREF of the fixed resource set. The first method is suitable for the single power system for internal benchmarks, and the co -mode voltage of the REFIO is changed within the soft range of 1.25 V to 0.10 V. Refio can be driven by a single power amplifier or DAC, allowing the fixed RSET to change Iref. Because the input impedance of Refio is about 1 MΩ, the simple, low-cost R-2R trapezoid DAC configured in the voltage mode topology can control the gain. The circuit is shown in Figure 43, using AD7524 and external 1.2V reference voltage AD1580.

The second method can be used for dual power systems, where the co -mode voltage of the REFIO is fixed, and IREF is changed from an external voltage VGC that is applied to the RSET by the amplifier. The example of this method is shown in Figure 44, where the co -mode voltage of the control amplifier is set to 1.20 V. External voltage VGC reference ACOM, and should not exceed 1.2 V. The value of RSET makes Irefmax and Irefmin not more than 62.5 μA and 625μA, respectively. The relevant equations in FIG. 44 can be used to determine the value of RSET.

In some applications, users can choose to use an external control amplifier to enhance the double bandwidth, distortion performance and/or stable time. External amplifiers (such as AD817) that can drive 50 PF loads are suitable for this purpose. Its configuration method enables it to connect with the weaker internal reference amplifier shown in Figure 45. In this case, the external amplifier will only over -drive the weak reference control amplifier. In addition, due to the limited current output of internal control amplifiers, it will not be damaged if it is excessively driven.

Simulation output

AD9760 generates two complementary current outputs, iOuta and IOUTB can be configured as single -ended or differential operations. IOUTA and IOUTB can be converted into complementary single -end voltage output Vouta and VOUTB through the load resistance RLOAD, as described by the equal 5 to 8 in the DAC transmission function part. The differential voltage VDiff between VOUTA and VOUTB can also be converted to a single -end voltage through a transformer or differential amplifier configuration. The AD9760 AC performance is the best, and it is specified using a differential transformer coupling. The voltage swing at the iOUTA and IOUTB is limited to ± 0.5 V. If you need a single -ended and single output, you should choose iOUTA.

When the AD9760 is configured for differential operations, it can enhance the distortion and noise performance of the AD9760. Through the coexistence suppression of a transformer or differential amplifier, the co -mode error source of iOuta and iOUTB can be significantly reduced. These co -mode error sources include the product and noise of the occasional steps.

With the increase of the reconstruction waveform frequency content, the improvement of distortion performance becomes more significant. This is due to various dynamic common modulus distortion mechanisms, digital feedback and noise.

The ability to execute differences to single -end conversion through the transformer also provides the ability to transmit double reconstruction signal power to the load (that is, assuming that there is no source end connection). Because the output current of iOuta and IOUTB is complementary, they will become adding methods during differential processing. The correct selected transformer will allow the AD9760 to provide the required power and voltage level for different loads. For examples of various output configurations, see the application AD9760.

The output impedance of iOuta and iOUTB is determined by equivalent parallel combination of PMOS switches associated with the current source. It is usually 100kΩ and parallel 5PF. Due to the nature of PMOS devices, it also depends on the output voltage (ie, Vouta and Voutb).

Therefore, keeping iOuta and/or iOUTB on the virtual ground through the I-V op amp will cause the best VC. Note: The INL/DNL specifications of AD9760 are measured by operating an amplifier on the virtual ground.

IOUTA and IOUTB also has a negative voltage and positive voltage conforms, which must be observed to achieve the best performance. Negative output compliance range-1.0V is set by the breakdown limit of the CMOS process. The operation that exceeds this maximum limit may cause output -level failure and affect the reliability of the AD9760.

Positive output conformity range slightly depends on the full standard output current iOUTFS. When IOUTFS 20 mAh, its nominal voltage decreased slightly from 1.25 volts to 1.00 volts (when IOUTFS 2mAh). When the maximum full label signal at the iOuta and iOUTB does not exceed 0.5V, the best distortion performance of the single -end or differential output can be achieved. The output (that is, VOUTA and/or Voutb) of AD9760 expand its output application that meets the range of RLOAD accordingly. The operation that exceeds this range will adversely affect the linear performance of the AD9760 and then reduce its distortion performance.

Digital input

The digital input of AD9760 is input pins and clock input pins by 10 data input pins and clock input pins. 10 -bit parallel data input follows the standard positive dual -in -system encoding, of which DB9 is the highest effective position (MSB), and DB0 is the lowest effective position (LSB). When all the data bit is logical 1, iOONTA generates a full marked output current. IOUTB generates a complementary output, and the full standard current between the two output divides the function of the input code.

The digital interface uses the main and slave memory triggered by the edge. The DAC output is updated as the clock rising edge, as shown in Figure 1, its design supports the clock rate of up to 125 MSPS. The clock can work at any occupy ratio of the specified lock pulse width. Settings and maintenance time can also change during the clock cycle, as long as the minimum specified hour is met, although the positions of these transition edges may affect digital feedback and distortion performance. The best performance is usually obtained when the input data is converted on the upside of the 50%duty cycle to the clock.

Digital input is a CMOS compatible with logic thresholds. Vthreshold is set to about half of the digital positive power supply (DVD) or VTHRESHOLD DVD/2 (± 20%).

The internal digital circuit of AD9760 can work within the range of the digital power supply range of 2.7 V to 5.5 V. Therefore, when DVD is set to adapt to the maximum high -level voltage, the digital input can also adapt to the TTL level VOH (maximum value). DVDD, which is 3.3 volts, usually ensure the appropriate compatibility with most TTL logic series. Figure 46 shows the equivalent digital input circuit of data and clock input. Sleep mode input is similar to this, but it contains an activity drop -down circuit to ensure that the AD9760 is kept in a state of enabling when maintaining this input.

due to AD9760 can be updated to 125 MSPS. The quality of clocks and data input signals is very important for gaining the best performance. The driver of the digital data interface circuit should be specified to meet the minimum settings and maintenance time of the AD9760 and the minimum/maximum input logic flat threshold it needs. Generally, choosing the slowest logic family that meets the above conditions will lead to the lowest data feeding and noise.

The digital signal path should be kept short and running in length to avoid delayed dissection. Inserting a low -value resistance network (that is, 20Ω to 100Ω) between AD9760 digital input and drive output may help reduce any overwhelming and bell at the digital input at the digital input at the data feedback. For longer running length and higher data update rate, we should consider adopting a band line technology with an appropriate terminal resistance to maintain a clean " digital input. In addition