Features

SO-8 package (LTC1595)

DNL and Inl: 1LSB maximum value

Low fault pulse: 1NV-S type

Quickly sink to 1LSB: 2μs (LT1468)

The pin of the industry standard

12 -bit DAC: DAC8043 and DAC8143/AD7543

Four Elephant Limits multiplication

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123] Low power current: maximum 10 μA

Powering and reset

LTC1595/LTC1596: reset to zero scale

LTC1596-1: reset to medium scale

3 -line SPI and Microwiretm compatibility

serial interface

Chrysanthemum chain serial output (LTC1596)

Clear asynchronous input

ltc1596: Clear removal For zero scale

LTC1596-1: Clear to medium scale

Application

Process control and industrial automation

Software control gain adjustment [ 123]

Digital control filter and power supply

Automatic testing equipment

Instructions

LTC #174; 1595/LTC1596/LTC1596-1 is serial Input, 16 -bit digital modulus output current. LTC1595 is a 12 -bit DAC8043 and a software package such as 8 -needle PDIP. LTC1596 is a pins and a hardware compatible with the 12 -bit DAC8143/AD7543 compatible with 16 -shot PDIP and so widely encapsulated. Both are specified within the industrial temperature range. The sensitivity of INL on the computing amplifier VOS is 5 times that of the 12 -bit DAC of the industry standards. Compared with the industry standard, the system can easily upgrade to the real 16 -bit resolution linearity without more accurate operational amplifiers. These DACs include a internal gas-dejected circuit reduced the typical value of the fault pulse by more than 10 times. DAC has clear input and power -on reset. This LTC1595 and LTC1596 are reset to zero scale. LTC1596-1 is a version of LTC1596, which can be replaced as medium.

Absolutely maximum rated value

VDD to agng 0.5 volts to 7 volts

VDD is dgnd 0.5 volts to 7 volts

AGND to DGND VDD+0.5 0.5 3

dgND to agng VDD+0.5 volts

-25 volts

RFB to agng, dgnd -25 volts

Digital input to dgnd -0.5V to (VDD+0.5V)

VOUT1, Vout2 to agng -0.5V to (VDD+0.5V)

The highest knot temperature 150 degrees Celsius

Work temperature range

LTC1595C/LTC1596C /LTC1596-1C 0 ° C to 70 ° C

LTC1595i/LTC1596i/LTC1596-1i –40 ° C to 85 ° C

Storage temperature range –65 ° C to 150 ° C [ 123]

Lead temperature (welding, 10 seconds) 300 degrees Celsius

Electric characteristics VDD u003d 5V*10%, vREF u003d 10V, VOUT1 u003d VOUT2 u003d agnd u003d 0V, ta u003d tmin to Tmax, unless otherwise There are explanations.

indicates the specification for the entire operation

The temperature range.

Note 1: Absolute maximum rated value means that the value of the value of the life expectancy may be damaged.

Note 2: ± 1LSB u003d ± 0.0015%full range u003d ± 15.3ppm full range.

Note 3: Use internal feedback resistors.

Note 4: Design guarantee, without trial.

Note 5: Iout1, DAC register loads all 0.

Note 6: The typical temperature coefficient is 100 ppm/c.

Note 7: 100 parallel with 13pf.

Note 8: Full range changes to 0.0015%, which measures the edges of LD1, LD2 or LD from the decline.

Note VREF u003d 6VRMS at 9: 1kHz. Load all 1 DAC registers; 1007 liters u003d working current.

Note 10: Calculated according to EN u003d √4ktrb, where: k u003d Bolzmann constant (J/° K); R u003d resistance ( ); t u003d temperature (° K); B u003d bandwidth (Hz).

Note 11: The shortest peak time of STB1, STB2, STB4. The lowest low tide time is for STB3.

Note 12: The shortest time of STB1, STB2, STB4. The shortest orgasm time is for STB3.

CodeType performance feature

pin function

LTC1595

vREF (pin 1): Reference input.

RFB (pin 2): feedback resistor. Usually the output -related current voltage converter operational amplifier.

Output 1 (pin 3): current output pins. Connect to the inverse input current voltage converter operational amplifier.

GND (pin 4): ground pins.

LD (pin 5): serial interface load control input. LD is pulled down, the data is loaded from the displacement register to the DAC register, and the DAC output is updated.

SRI (pin 6): serial data input. The data on the SRI pin is the clock in the shift register that is locked to the sequence rising edge. Data first load MSB.

CLK (pin 7): serial interface clock input.

VDD (pin 8): Positive power input. 4.5V ≤VDD ≤ 5.5V. Need to be bypass capacitors to ground.

LTC1596/LTC1596-1

Output 1 (pin 1): real current output pin. Connect to the input of an enlarged amplifier in the elevator current voltage converter.

Output 2 (pin 2): supplement the current output pins. Contact the simulation ground.

agng (pin 3): Simten to ground pins.

STB1, STB2, STB3, STB4 (pin 4, 8, 10, 11): serial interface clock input. STB1, STB2 and STB4 are triging inputs on the edge. STB3 is a drop -by -edge trigger input (see the true value table).

Serial input (LD5, LD9): Control pin. When the LD1 and LD2 are pulled down, the data will be shifted from the register to the DAC register to update the DAC output (see the true value table). SRO (pin 6): output of the displacement register. The edge of the activity of the serial clock is valid.

SRI (pin 7): serial data input. The data on the SRI pin is locked to the serial clock. Data first load MSB.

DGND (pin 12): Digital ground pins. Clear pin 13: Clear DAC pin. Clear DAC to zero when pulling down from LTC1596 low. Clear DAC to the medium scale when pulling down the LTC1596-1 low. This pin should be tied to the normal VDD.

VDD (pin 14): Positive power input. 4.5V ≤VDD ≤ 5.5V. Need to be bypass capacitors to ground.

VREF (pin 1 15): Reference input.

RFB (pin 16): feedback resistor. The output of the amplifier of the current voltage converter.

Table

Table 1. LTC1596/LTC1596-1 Input register table 2. LTC1596/LTC1596-1 DAC register

Explanation

LTC1595/LTC1596 is a 16 -bit multiplication DAC with serial input and current output. They use precise R/2R technology to provide excellent linearity and stability. These devices provide ± 10V reference input and voltage output range with an external computing amplifier through a 5V power supply work. These devices have a patented fiber, which can reduce the fault pulse 1NV-S and the output range is 0V to 10V.

Serial I/O

LTC1595/LTC1596 has a SPI/Microwire compatible serial port that accepts 16 -bit serial characters. The data is to accept MSB first and load them with storage. 8 -pin LTC1595 has a 3 -line interface. The data is transferred to the SRI data of the CLK pins rising along the edge. At the end of the data transmission, the data was loaded to DAC to pull the LD pin (see the LTC1595 timing chart).

Application information

16 -pin LTC1596 can provide additional pins with LTC1595 to improve flexibility. Four hours are STB1, STB2, STB3 and STB4. The working methods of STB1, STB2, and STB4 have been captured data on its rising edge. STB3 captures its data (see Table 1). LTC1596 has two loads, LD1 and LD2. Data, both pins must be low. If one of them is grounded, the other pins work is the same as the LTC1595 LD pin. Asynchronous clearance input (CLR) reset the LTC1596 to zero scale (LTC1596-1 to medium scale) as low (see truth table 2). LTC1596 also has a data output pin SRO, which can be connected to another DAC to SRI from the chrysanthemum chain to enter a multiple DAC on a 3 -line interface (see LTC1596 sequential map).

Single pole (2 quadrant limit) mode

(voltage u003d 0V to -vref) LTC1595/LTC1596 can be used with a single computing amplifier to provide a 2-quadrant multiplication operation, as shown in Figure 1. When the reference voltage is 10 volts, the circuit provides accurate orders as shown in the figurePolarity 0V to 10V output swing.

Application information

Dual (4 image limit) mode

(vout u003d --vref to VREF) LTC1595/LTC1596 can be available. Use it with dual transportation amplifiers and three external resistors to provide a 4 -limit multi -function operation, as shown in Figure 2 (last page). With a fixed 10V reference voltage, the displayed circuit provides a precision bipolar -10V to 10V output swing. The use of LTC1596-1 will cause power-on reset and clear pins to reset DAC to the middle scale (double pole zero). The computing amplifier selection is capable because the 16 -bit extremely high -precision LTC1595/LTC1596 should be considered that the computing amplifier to achieve excellent performance is capable. Fortunately, the offsets of INL and DNL to the computing amplifier have been greatly reduced compared with the previous generations of DAC. The offset of the operation amplifier will mainly affect the output offset and the minimum impact on INL and DNL. For example, the offset of 500 μV computing amplifier will cause about 0.55LSB

Application information

Inl degradation and 0.15LSB DNL degradation, 10V full marking range. The main impact of the operation amplifier's offset is the zero -scale error degeneration bias of the computing amplifier equal to the operation of the computing amplifier. For example, the same 500 μV operational amplifier offset will cause 3.3LSB zero -scale error and 6.5LSB full marking error, and the full marking range is 10V. The computing amplifier input bias current (IBIAS) generates only a zero -scale error, which is equal to Ibias (RFB) u003d IBIAS (RREF) u003d IBIAS (7K). Table 2 shows that the choice of LTC computing amplifier is suitable for LTC1595/LTC1596. In -depth discussions and options of the stable time and computing amplifier of the 16 -digit modulus converter, refer to the application annotation 74, ""the progress of components and measurement ensures the stable time of 16 -bit DAC.""

ground ground

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Like any high -resolution converter, clean ground is important. Low impedance simulation ground plane and star type should be used ground. IOUT2 u200bu200b(LTC1596) and GND (LTC1595) must be connected to the star -shaped ground as much as possible with low A.

Table 2. The 16 -bit stable time of various amplifiers driven by LT1595 DAC. LT1468 (shadow) provides the fastest settlement time to maintain super temperature accuracy