AD7940 is 3 MW, ...

  • 2022-09-21 17:24:28

AD7940 is 3 MW, 100 KSPS, and 14-bit ADC in 6-guide SOT-23

Features

- Quick throughput: 100 KSPS

- It is stipulated that VDD is 2.5 V to 5.5 v

- Low power

- 4 MW, 100 KSPS, 3 volts of power

- 17 MW, 100 KSPS, 5 volt power

- Wide input bandwidth:

-

10 kHz input frequency 81 db sinad

-

Flexible power/serial clock speed management

-

No pipeline delay

High -speed serial interface [ 123]

- SPI/QSPI Standard #8482;/Micro Sils #8482;/Compatible digital signal processor

- Standby Mode: Maximum 0.5 Wei'an

- 6-guide SOT-23 and 8-guide MSOP packaging

- Battery power supply system [ 123]

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Personal digital assistant

-

Medical Device

Mobile communication

[123 ]

- Instrument and control system

- Remote data acquisition system

General description

AD7940 1 is a 14 -bit, fast, and low -power consumption one by one. This component is powered by a single 2.50 V to 5.5 V power, and the throughput is as high as 100 KSPS. This part contains a low -noise, broadband trace and keeping amplifier, which can process more than 7 trillion input frequency.

The conversion process and data collection are controlled by CS and serial clocks, allowing the device to be a microprocessor or DSP interface. The input signal is sampled on the edge of the CS, and it also begins to be converted at this time. There is no component -related assembly line delay. AD7940 uses advanced design technology to achieve very low power consumption with rapid throughput. The reference of the part is obtained from the VDD, and VDD allows the maximum dynamic input range of ADC. Therefore, the analog input range of this part is 0 V to VDD. The conversion rate is determined by the SCLK frequency.

This section uses standards to approach AD one by oneC, accurately control the sampling time through CS input and one -off transition control.

Product Highlights 1. The first 14-bit ADC in SOT-23 package.

2. High throughput, low power consumption.

3. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the conversion time by increased the speed of serial clock. This allows the average power consumption when using the power loss mode without conversion. This part also has a shutdown mode to maximize energy efficiency at the maximum at a lower throughput. The maximum value when the power consumption is 0.5 points is micro -security.

4. Reference from power supply.

5. No pipeline delay.

Pin configuration and function description

The term

Points of points non -linearity

[ 123] This is the maximum deviation of the straight line of the end point of the function through the ADC. The endpoint of the transfer function is zero scale, the first code conversion of 1/2 LSB point below, and the last code conversion of 1/2 LSB point.

Fortune non -linearity

This is the difference between the measurement value between the two adjacent code and the ideal 1 LSB change of the two adjacent code in ADC.

The offset error

This is the first code conversion deviation (00.000) to (00.001) from the ideal, that is, agng+1 LSB.

gain error

This is the last bias of code conversion (111.110) to (111 ... 111) from the ideal (that is, V 1 lsb) offset offset After the error is adjusted.

Tracking and maintaining the collection time

At the end of the conversion, the tracking holder returns to the tracking mode. The tracking and keeping capture time is the time required to track and keep the output of the amplifier (within the range of ± 1LSB) after the conversion is over. For details, see the serial interface part.

The signal -to -noise ratio

This is the ratio of the signal to (noise+distortion) measured at the ADC output terminal. The signal is the average root amplitude of Kobo. Noise is the sum of all non -basic signals, and at most is half of the sampling frequency (f/2, excluding DC). This ratio depends on the number of quantitative levels in the digitalization process; the more levels, the smaller the quantified noise. The theoretical signal-to-noise ratio of an ideal N-bit sine wave input converter is given by the following:

signal to- (noise+distortion) (6.02 n+1.76) decibel

So therefore For 14 -bit converters, this is 86.04 decibels.

Total harmonic distortion (THD)

THD is the ratio of harmonic equity and the ratio of the base wave. For AD7940, defined as:

Among them, V1 is the average root amplitude of the Kyo, V2, V3, V4, V5, and V6 are the second harmonic to the first harmonic to No. 1 Six homogeneous square root amplitude.

Peak harmonic or bandate noise

Peak harmonic or bandard noise is defined as the average root value and base wave in the next maximum component (excluding DC) in the ADC output spectrum The ratio of the equity root value. Generally, the value of this specification is determined by the largest harmonic in the spectrum, but for the Harmony ADC buried in the noise layer, it will be the peak of noise.

Mutual distortion

When the input consists of a sine wave of two frequencies (FA and FB), any non -linear active device will be in the harmony and difference of the MFA ± NFB Frequently produce distortion products, where M, n 0, 1, 2, 3. Mutual disturbances refer to the items that M and N are not equal to zero. For example, second-order terms include (FA+FB) and (FA-FB), and third-order terms include (2FA+FB), (2FA-FB), (FA+2FB), and (FA-2FB).

AD7940 uses the CCIF standard for testing, which uses two input frequencies near the top of the input bandwidth. In this case, the second -order item is usually between the frequency and the original string wave, and the third -order item is usually close to the frequency of the input frequency. Therefore, the second and third -order terms are specified separately. Mutual disturbances are based on the THD specifications. Among them, the ratio of RMS of a single distortion product and the ratio of RMS amplitude with the basic principles represented by DBS.

Typical performance features

FIG. 5 shows the typical FFT diagram of AD7940 at 100 KSPS sampling rate and 10 kHz input frequency. Figure 6 shows that when the SCLK of 2.5MHz is sampled by 100KSPS, the signal -to -noise ratio performance of different power supply voltage and input frequency.

FIG. 7 shows the relationship diagram of the total harmonic distortion of various power supply voltage and the simulation input frequency, and Figure 8 shows the relationship diagram of the total harmonic distortion of various power impedance and the simulation input frequency (see The simulation input section). Figure 9 and 10 show the typical INL and DNL diagrams of AD7940.

Circuit information

AD7940 is a kind of fast, low power consumption, 14 -bit, single power ADC. This part can be supplied from 2.50 points V to 5.5 V. When running under 5V or 3V power, the AD7940 is equipped with a 2.5 -warn clock.

AD7940 provides users with a film tracking and maintaining ADC and a serial interface, which is encapsulated in a tiny6-guide SOT-23 package or 8-guide MSOP package, compared with other solutions, provides users with considerable space saving advantages. The serial clock inputs the data from the component and provides the clock source to the ADC one by one. The analog input range of AD7940 is 0 V to V. ADC does not require external reference or reference on the chip. The benchmark of AD7940 comes from the power supply, so it provides the widest dynamic input range. The AD7940 also has a power -off option to save the power supply between conversion. The power -off function is implemented through the standard serial interface, as described in the operation mode.

Inverter operation

AD7940 is a 14 -bit of a capacitive DAC approaching ADC one by one. AD7940 can convert the simulation input signal 0 V to V range. Figure 11 and 12 show the simplified schematic diagram of ADC. ADC includes control logic, SAR and capacitive DAC. Figure 11 shows the ADC in the collection phase. SW2 is closed, SW1 is in position A. The comparator is kept in a balanced state, and the sampling capacitor obtains the signal on the selected V channel.

When the ADC starts to change, the SW2 will be opened, and the SW1 will move to position B, causing the comparator to become unbalanced (Figure 12). Control logic and capacitive DACs are used to add and minus a fixed amount of charge from sampling capacitors to return the comparator back to the balance. When the comparator is re -balance, the conversion is completed. Control logic generate ADC output code (see the ADC transmission function part).

Simulation input

FIG. 13 shows the equivalent circuit of the AD7940 analog input structure. Two diode D1 and D2 provide ESD protection for simulation input. It must be noted that the analog input signal will not exceed more than 300 MV. This will cause these diode to be pressed forward and start to conduct current to the substrate. The maximum current that these diode can be transmitted is 10 mAh, not irreversible damage to the parts. The capacitor C1 in FIG. 13 is usually about 5 PF, which can be attributed to pin capacitors. The resistor R1 is a set of collective components composed of switches (tracks and switches). The resistance is usually about 25Ω. Capacitor C2 is an ADC sampling capacitor, and its capacitance is usually 25 PF. For communication applications, it is recommended to use the RC low -pass filter on the related simulation input pin to remove the high frequency component from the analog input signal. In applications where harmonic distortion and signal -to -noise ratio are very important, the simulation input should be driven by low impedance sources. Large source impedance will significantly affect the ADC's communication performance. This may need to use input buffer amplifiers. The choice of computing amplifier will be a function of a specific application. When no amplifier driver inputs, the source impedance should be limited to low value. The maximum source of impedance will depend on the total harmonic distortion (THD) of the tolerance. THD will increase with the increase of source impedanceAdd, performance will be reduced (see Figure 8).

ADC transmission function

The output encoding of AD7940 is direct binary. The design code conversion occurs on the continuous integer LSB value, that is, 1 LSB and 2 LSB. The size of LSB is VDD/16384. The ideal transmission characteristics of AD7940 are shown in Figure 14.

Typical wiring chart

Figure 15 shows the typical connection diagram of AD7940. V is obtained from V, so it should be separated well. This provides an analog input range from 0V to V. The conversion result is output in 16 -bit words. These 16 -bit data streams are composed of two front -lead, and the 14 -bit of the transition data is preferred. For applications involving power consumption, the power loss mode should be used between converting or multiple conversion pulses to improve power performance (see the operating mode part).

In fact, because the power supply current required by AD7940 is very low, the accuracy benchmark can be used as the power supply of the AD7940. For example, you can use the REF19X voltage benchmark (Ref195 represents 5V or Ref193 represents 3V) or AD780 provides the required voltage to ADC (see Figure 15). If the available power supply is noisy, or the system power supply voltage is not the working voltage required by the AD7940, this configuration is particularly useful, for example, 15 V. Ref19X or AD780 will be AD7940. The recommended beo-coupled container is 100 NF low ESR ceramics (Farnell 335-1816) and 10 μF low ESR 钽 (Farnell 197-130).

Digital input

Digital input used to AD7940 is not limited by the maximum rated value of simulation input. On the contrary, the number of digital inputs can reach 7V and is not limited by VDD+0.3V, which is the same as analog input. For example, if the VDD of AD7940 is 3V, you can use 5V logic levels on the digital input end. However, another advantage of SCLK and CS is not limited by VDD+0.3V is that the problem of power sorting is avoided. If one of the numbers is applied before VDD, the risk of locking will not appear, because if the signal is greater than 0.3 V before the VDD, locks will appear on the analog input.

Operation mode

During the conversion period, the operation mode of the AD7940 by controlling the (logic) state of the CS signal is controlled. There are two possible operation modes, normal and power off. After the conversion is started, the CS is pulled up and it will determine whether the AD7940 enters the power loss mode. Similarly, if the power is off, CS can control whether the device will resume normal work or continue to power off. These operation modes are designed to provideFlexible power management options. These options can optimize power/throughput ratio for different application requirements.

Normal mode

This mode provides the fastest throughput performance, because users do not have to worry about the power of power when AD7940 always maintains full power. FIG. 16 shows the working scheme of the AD7940 in this mode.

As mentioned in the serial interface part, the conversion is started on the decrease of CS. In order to ensure that the components are always fully powered, the CS must be kept low, and at least 10 SCLK decreases along the CS decrease. If CS becomes higher at any time after the 10th SCLK decreases, but before the 16th SCLK declines, the parts will be kept power -on, but the conversion will be terminated and SDATA will return to three states. At least 16 serial clock cycles are required to complete the conversion and access the complete conversion results. CS may be high until the next conversion or idle until CS returns high before the next conversion, the effective idling CS is low. Once the data transmission is complete (SDATA has returned to three states), another conversion can be started after a quiet time. TQUIET can be reduced again.

Power off mode

This mode is suitable for applications that require slower throughput. Between each conversion, the ADC power off, or a series of conversion can be performed at a high throughput, and then between these multiple conversion emergencies, ADC has a relatively long duration. When the AD7940 is disconnected, all analog circuits are powered off.

To enter the power -off state, the conversion process must be interrupted anywhere before SCLK's second decline edge of SCLK, as shown in Figure 17. Once CS is raised in this window of SCLKS, the parts will enter the power -off state, and the conversion of the decrease of CS will be terminated, and SDATA will return to three states. If the CS increases before the second SCLK decreases, the parts will keep the normal mode without power out of power. This will avoids accidental power off due to the CS line failure.

In order to exit this operation mode and power the AD7940 again to perform virtual conversion. At the decline of the CS, the device will start power and as long as the CS remains at a low level and continues to power until the decline edge of the 10th SCLK. Once at least 16 SCLK (or about 6 microseconds), the device will be fully powered, and the next conversion will generate valid data, as shown in Figure 18. If CS rises before the 10th decrease of SCLK, regardless of the frequency of SCLK, the AD7940 will be disconnected again. This can avoid accidental power due to the accidental emergencies of the 8 SCLK cycle when the CS line failure or the CS low. Therefore, although the device may start to power on the CS decrease, as long as the 10th SCLK declines edge, the CS rising along the electricity will be again.decline.

Power and throughput

By using the power consumption mode on the AD7940 when not converted, the average power consumption of ADC is at a lower throughput reduce. Figure 19 shows that as the throughput rate decreases, the parts keep a longer shutdown state, and over time, the average power consumption also decreases accordingly.

For example, if the AD7940 works in a continuous sampling mode, the throughput is 10 KSPS, the SCLK is 2.5 stems (v 3.6 five), and the device is in the switch mode between the conversion. The calculation of the power consumption is as follows as follows. Essence The maximum power consumption at normal operation is 6.84 Miwa (V 3.6 5), so. If the power -on time after power is disconnected is 1 microsecond, the remaining conversion time is 6.4 microseconds (transmitted by 16 SCLK), and it can be said that the AD7940 dissipates 6.84 MPA 7.4 models in each conversion cycle. When the throughput is 10 KSPS, the cycle is 100 microseconds. For the rest of the conversion cycle, 92.6 microseconds, components maintain a power outage mode. The AD7940 can be said to have dissipated 1.08 points for microseconds 92.6 conversion cycle. Therefore, when the throughput is 10 KSPS, the average power consumption of each cycle is:

FIG. 19 shows the use of 3.6 V supplies and A2.5 items with articles and A2.5. Mills SCLK.

Serial interface

Figure 20 shows the detailed sequential map with the AD7940 serial interface. The serial clock provides a conversion clock and controls information transmission from AD7940 during the conversion period.

CS signal starts the data transmission and conversion process. The decrease of CS puts Track and Hold in the HOLD mode, removes the bus from three states, and sampling the analog input. The conversion is also started at this time, and at least 16 SCLK cycles will be required to complete. Once the edge of 15 SCLK decreases, the tracking and keeping will return to the tracking mode to rising the edge of the next SCLK, as shown in point B in Figure 20. On the 16th SCLK decline, the SDATA cable will return to three states. If the rising edge of the CS appears before the 16 SCLK passes, the conversion will be terminated, and the SDATA cable will return to three states; otherwise, the SDATA will return to the three states above 16 SCLK, as shown in Figure 20.

The 16 -serial clock cycle is required to perform the conversion process and access data from the AD7940. CS is low, provides the first front guide, read by microcontroller or DSP. The remaining data is then output from the subsequent SCLK from the second front guide, so the first decline on the serial clock has the first front guide provided by the first front, and the second front guide zero zero zero zero zeroClock output. Data transmission will consist of two front and 14 -bit data. The last one in the data transmission is valid on the 16th decrease along the edge of the first (15th) decline.

Because the SCLK cycle is long enough, it can ensure that the data is prepared on the rising along the SCLK, so it can also obtain effective data on the rising edge of each SCLK instead of the decrease along the edge of the decrease. However, the first front guide is still driven by the CS decrease, so it can only be performed on the first SCLK decrease. It can be ignored. The first rising edge of the SCLK after the CS decreases will provide the second front guide, and the 15th rising SCLK edge will provide DB0. This method may not be suitable for most micro -controllers/DSPs, but may be used for FPGAS and ASIC.

microprocessor interface

The serial interface allowed parts on the AD7940 to allow components to directly connect to many different microprocessors. This section introduces how to interface AD7940 with some more common microcontrollers and DSP serial interface protocols.

AD7940 to TMS320C541

The serial interface on TMS320C541 uses continuous serial clocks and frame synchronization signals to synchronize data transmission operations with peripheral devices such as AD7940. CS input allows easy connection between TMS320C541 and AD7940 without glue logic. The serial port of the TMS320C541 is set to work in an emergency mode, with CLKX (TX serial clock) and FSX (TX frame synchronization) inside. The serial port control register (SPC) must have the following settings:

f 0

fsm 1

mcm 1

txm 1 [ 123]

Format FO must be set to 1 to set the length to 8 digits in order to implement the power -off mode on the AD7940. The connection diagram is shown in Figure 21. It should be noted that for signal processing applications, frame synchronization signals from TMS320C541 must provide equal sampling.

AD7940 to ADSP-218X

DSP of the ADSP-218X series can be directly connected to AD7940 without glue logic. The setting of the motion control register is as follows:

tfsw rfsw 1, alternate frame

invrfs 1VTFS 1, effective low frame signal

dtype 00, right -to -alignment data data data

SLEN 1111, 16 -bit dataword

ISCLK 1, internal serial clock

tfsr rFSR 0, Frame First Word

IRFS 0

ITFS 1

To achieve the power loss mode, SLEN should be set to 0111 to send an 8 -bit SCLK emergency.

The connection diagram is shown in Figure 22. ADSP-218X binds the TFS and RFS of the motion, and the TFS is set to output, and the RFS is set to input. DSP works in a alternate frame mode, and the motion control register is as described as described. The frame synchronization signal generated on the TFS is bound to CS, and, like all signal processing applications, the separation sampling is necessary. In this example, the timer interrupt is used to control ADC.

The timer register loads a value, which provides interruption in the required sampling interval. When it is received, the value in the transmission automatic buffer starts to transmit and generates TFS. TFS is used to control therefore, as well as data reading. Data is stored in the receiving automatic buffer memory for processing or movement later. The frequency of the serial clock is set in the SCLKDIV register. When using the TFS send instruction, that is, TX0 AX0, check the status of SCLK. Before starting transmission, DSP waits for SCLK to become higher, lower, and high. If the selected timer and SCLK value make the instructions to be sent, the data can be sent, or it can be sent to the edge of the next clock.

For example, if ADSP-2189 has 20MHz crystals and the main clock frequency is 40MHz, the main cycle time will be 25ns. If the SCLKDIV register loads 7, 2.5 will get MHz, and each SCLK cycle will pass through 16 main clock cycles. According to the selected throughput, if the timer register loads the value of 803 (803+1 804), 50.25 points SCLK will occur between the interruption and subsequent transmission instructions. Because the transmission instruction occurs on the edge of SCLK, this situation will cause non -equal sampling. If the number of SCLK between interruption is an integer, the DSP is implemented by the equal sampling.

AD7940 to DSP563XX

The connection diagram in FIG. 23 shows how AD7940 is connected to the ESIS (synchronous serial interface) of the DSP-563XX series of Motorola. Each ESIS (two on the board) runs in synchronization mode (SYN bit 1 in CRB), and the 1 -bit clock cycle frame synchronization of TX and RX generates (FSL1 digits in CRB 0 and FSL0 bits 0) Essence Select the normal operation of ESIS by setting MOD 0 in CRB. By setting the position wl1 1 and wl0 0 in the CRA, the word length is set to 16. The FSP bits in CRB should be set to 1 for the frame synchronization. It should be noted that for signal processing applicationsThe synchronous signal from DSP-563XX provides equal sampling.

In the example shown in FIG. 23, the serial clock is taken from ESIS, so the SCK0 pin must be set to output, SCKD 1.

Application prompt

grounding and layout

The design of the printing circuit board of the AD7940 should be separated from the simulation and the number parts and limits the number part In some areas of the board. This helps to use the horizon that is easy to separate. The minimum etching technology is usually the best on the ground plane because it provides the best shielding. Digital and simulation ground can only be connected in one place. If the AD7940 is in a system where multiple devices need AGND to DGND connection, it should still be connected at only one point. This point should be as close to AD7940 as possible to establish a star -shaped place.

Avoid running digital lines under the device, because this will coupling noise on the mold. The simulation ground plane should be allowed to run under AD7940 to avoid noise coupling. The power cord of AD7940 should be as large as possible to provide low impedance paths and reduce the impact of faults on the power cord. Quick switching signals, such as clocks, should be shielded by digital grounding to avoid radiation noise to the circuit board. The clock signal must not run near the analog input terminal. Avoid digital and analog signal crossing. The lines on the edge of the circuit board should become a right angle, which will reduce the impact of the feed wires through the line board. So far, micro -band technology is the best, but it is not always feasible on the double panel. In this technology, the component side of the circuit board is dedicated to the ground plane, and the signal is placed on the welded side.

Good decoupling is also very important. All analog power supplies should be separated from 10 μF 钽, and connected to AGND with 0.1 μF capacitors, as described in the typical connection diagram. In order to achieve the optimal performance of these decoupled components, users should try to keep the distance between the exfoliating container and the V and GND tube foot to the minimum value, and make the connection track length between the feet shorter.

Evaluate AD7940 Performance

AD7940's recommended layout is summarized in the evaluation board of AD7940. The assessment board includes the evaluation board, documentation and software that is completely assembled and tested, which is used to control the evaluation board from the PC controller through the evaluation board controller. The assessment board controller can be used with the AD7940 evaluation board and many other simulated device assessment boards ending at the end of the CB indicator to demonstrate/evaluate the AD7940 communication and DC performance.

The software allows users to perform AC (fast Fourier transformation) and DC (code histogram) test on AD7940. The software and documents are located on the CD attached to the assessment board.

Dimensions

1, z parts that conform to ROHS.

2. The linear error here refers to the code that is not lost.

3. This can be used as an independent evaluation committee, and it can also be used to evaluate/demonstrate the purpose of the evaluation control committee.

4. This circuit board is a complete unit that allows PC to control and evaluate the circuit board communication with all analog equipment at the end of the CB indicator.To order a complete assessment kit, you need to order a specific ADC assessment board, such as Eval-AD7940CB, Eval-Control BRD2, and 12 V AC transformers.For more information, please refer to the application of the evaluation committee.