Features

10 Might clock rate; second -order modulator; 16 -bit without leakage code; 16 -bit ± 2 LSB input; 3.5 microbl/degree Celsius maximum offset drift; vehicle digital isolation device ; Car reference; low power operation: 5.25 V is the maximum 18 mAh; -40 ° C to+125 ° C working range; 16 lead SoIC, 8 lead gull wing face installation DIP packaging; AD7401A ,,,,,,,,,, The external clock version is safe and regulatory approval; UL recognizes; 3750 V RMS, 1577 1 minute per UL; CSA component acceptance notification#5A; VDE qualification certificate; German industrial standard EN 60747-5-2 (VDE 0884 Part 2): 2003: 2003 -01; German Industrial Standard EN 60950 (VDE 0805): 2001-12; European Industrial Standard EN 60950: 2000; VIORM 891V Peak.

Application

*AC motor control

*Data acquisition system

*A/D+light isolation device replacement.

General instructions

AD7400A 1 is a second-order ∑-Δ modulator, which converts the analog input signal to high-speed, 1 digit data stream, and is based on Analog Devices , Inc.icoupler Technology isolate on the film. AD7400A works through a 5 V power supply and accepts the difference in input signal of ± 200 mV (± 320 mv full scale). The analog input is continuously sampled by the simulation modulation, without the need for external sampling and keeping the circuit. The input information is included in the output stream with a data rate of 10MHz. Using appropriate digital filter can rebuild the original information. Serial I/O can use 5 V or 3 V power supply (VDD2).

The serial interface is isolated by numbers. The combination of high -speed CMOS and single -chip empty transformer technology means that the segregation on the tablet provides excellent performance of superficial alternative devices such as optocoupled device. This part contains a reference on a piece. The AD7400A uses 16-directed SOIC and 8-guide gull-wing-faced packets, with a working temperature range of -40 ° C to+125 ° C.

Function box diagram

Typical performance features

t 25 ° C, use 20 kHz brick wall filters, unless otherwise explained otherwise Essence

The term

Fortu The difference between the measurement value of the two adjacent codes and the ideal 1 LSB change.

Integral non -linear

Integral non -linearity is the maximum deviation of the straight line of the end point through the ADC. The endpoint of the transmission function is specified to be negative, -200 MV (vin+-vin-), 16-bit level code 12288, and specified positive standard,+200 mv (vin+-vin-), 16-bit level level Code 53248.

The offset error

The offset is the medium-scale code (16-digit code 32768) and the ideal vehicle recognition number+vehicle identification number- (that is, 0 volts) Essence

gain error

This includes the gain error and negative scale gain error error. The gain error error of the full margin refers to the deviation of the defined bidding code (16-bit level 53248) and the ideal vehicle recognition number+-(+200 millivolta) after adjusting the offset error. Essence The negative label gain error is the deviation between the specified negative label code (16-bit level 12288) and the ideal vehicle identification number-(-200 millivolta). The gain error includes reference errors.

Sinad ratio

This ratio is the ratio of signal to (noise+distortion) measured at the ADC output end. The signal is the average root amplitude of Kobo. Noise is the sum of all non -basic signals. At most, it is half of the sampling frequency (FS/2), excluding DC electricity. This ratio depends on the number of quantitative levels in the digitalization process; the more levels, the smaller the quantitative noise. The theoretical signal-to-noise ratio of an ideal N-bit sine wave input converter is given by the following:

signal to- (noise+distortion) (6.02n+1.76) db

So therefore For the 12 -bit converter, this is 74 decibels.

Effective bit (ENOB)

The definition of ENOB is:

ENOB (sinad-1.76)/6.02

Total harmonic distortion ( THD)

THD is the ratio of the equity of the harmonic and the ratio of the base wave. For the AD7400A, it is defined as:

Among them: V1 is the average root amplitude of Kobo.

V2, V3, V4, V5, and V6 are the average root amplitude of the second harmonic to the sixth harmonic.

Peak harmonic or bandate noise

Peak harmonic or bandard noise is defined as the average root value and base wave in the next maximum component (excluding DC) in the ADC output spectrum The ratio of the equity root value. Generally, the values of this specification are determined by the maximum harmonic in the spectrum, but for the Harmony ADC buried in the noise layer, it is the peak of noise.

Common model suppression ratio

Common model suppression ratio isAt the frequency F of ± 200 mv, the ADC output power is the ratio of the co-mode voltage V+and V-on the frequency F of the frequency F. /Pfs)

In the formula: PF is the power at the ADC output mid -frequency F.

PFS is the power at the ADC output mid -frequency FS.

Power suppression ratio

The change of the power supply affects the full marking conversion, but does not affect the linearity of the converter. PSRR is the maximum change of the transition point specified at a full label (± 200 MV), which is caused by changes in the power supply voltage and nominal values (see Figure 7).

isolation transient resistance

isolation transient antipity. It specifies the increase/decrease rate of the transient pulse applied to the isolation boundary. Essence (Use the transient pulse frequency to 100 kHz.)

Operation theory

Circuit information

AD7400A isolation ∑-Δ modulator converts analog input signal to high-speed (10 MHz (10 MHz Data stream of unit data; the average time of the unit data of the modulator is proportional to the input signal. Figure 23 shows a typical application circuit, where the AD7400A is used to provide isolation between analog input, current influenza resistor and digital output, and then processing N position by digital filter processing.

Simulation input

Differential analog input of AD7400A is implemented by the switch capacitor circuit. The circuit realizes the second -order modulator of the input signal to a 1 -bit output stream. McLkout provides clock signals for the conversion process and output data frame clock. The clock source is within AD7400A. The modulator continuously samples the analog input signal and is compared with the internal voltage benchmark. A digital flow appears at the output end of the converter, which accurately indicates the simulation input of the time shift (see Figure 21).

0V Differential signal (ideal) generates a 1 and 0 stream at the MDAT output pin. This output is high within 50%, and it is low within 50%. A 200 millivolt -differential input generates a 1 and 0 stream, as high as 81.25%. -200 MV Differential input generated 1 and 0 streams, as high as 18.75%in time.

320 millivolt differential input generates all the ideal input flow. This is the absolute scale range of AD7400A, while 200 MV is the specified full marking range, as shown in the table 9.

To rebuild the original information, digital filtering and extraction need to be used for output. It is recommended to use SINC filter, because it is one level higher than the AD7400A modulator. If the 256 extraction rate is used, the 16 -bit word rate obtained is 39 kHz, and the internal clock frequency is 10 MHz. Figure 22 shows the transmission function of AD7400A relative to 16 -bit output.

Differential input

The simulation input of the modulator is a switch capacitor design. The analog signal is converted into charge through high linear sampling capacitors. The simplified equivalent circuit diagram of the simulation input is shown in Figure 24. The signal source of the driver's input must be able to provide charge to the sample capacitor every half of the MCLKOUT cycle and reach the required accuracy in the second half.

Since the AD7400A samples the differential voltage of its analog input terminal, it obtains low noise performance by providing low -mode noise input circuits at each input end. The amplifier used to drive analog input plays a key role in obtaining the high performance of AD7400A.

When the capacitance load is switched to the output end of the op amp, the amplitude decreases instantly. The op amp tried to correct this situation, and in this process, its conversion rate limit was reached. This non -linear response can cause excessive bells and lead to distortion. To solve this problem, a low -pass RC filter can be connected between the amplifier and the input end of the AD7400A. The external capacitors of each input terminal can help provide the current peak generated during the sampling process, and the resistor isolates the through the transient characteristics of the op amp with the transient characteristics of the load.

FIG. 25 shows the recommended circuit configuration of the driver differential input to obtain the best performance. One capacitor between the two input feet, which can effectively provide one of the charge required for one input by another input. The series resistance is isolated from the current peak of any op amp to the current during the sampling process. The recommended values of resistors and capacitors are 22Ω and 47 PF, respectively.

Digital filter

It is recommended to use Sinc filter with AD7400A. The filter can be implemented on FPGA or DSP. The Verilog code below provides an example of implementing Sinc filter on Xilinx Spartan II 2.5V FPGA. This code can be compiled into another FPGA, such as Altera device. Note that in this case, the data is read on the edge of the clock; however, if you want, you can read on the edge of the clock. Figure 29 shows the effect of using different extraction rates in different filter types.

Application information

grounding and layout

[12]3] It is strongly recommended to use the power of 100 nf on V and V. The decoupling on one or two V tubes does not significantly affect performance. In the application involving high -common model transients, we should pay attention to ensuring that the plate coupling on the seismic barrier is minimized. In addition, the design of the circuit board layout should ensure that any coupling occurs on the same pipe foot on the side of the given component. Failure to ensure that this may cause the voltage difference between the pins exceeding the absolute maximum rated value of the device, resulting in atresia or permanent damage. Any decoupling device used should be as close to the power as possible.

The series resistance in the simulation input should be minimized to avoid any distortion effect, especially at high temperature. If possible, the source impedance on each analog input is to minimize the offset. Pay attention to the simulation of the input PCB trajectory's non -matching and thermocouple effect to reduce the offset drift.

Evaluate AD7400A Performance

A simple and independent AD7400A assessment board can ensure isolation from the split ground and the split plate under the AD7400A package. This board allows each foot of the access device to evaluate. External power and all other circuits (such as digital filters) must be provided by users.

Insulation life

All the insulation structures, with sufficient time and/or voltage, are easy to break through. In addition to testing by regulatory agencies, the simulation equipment has also conducted a series of extensive assessments to determine the life of the insulation structure of the AD7400A.

These tests enable the equipment group to withstand continuous cross -seal voltage. In order to accelerate the occurrence of faults, the selected test voltage value exceeds the voltage value of normal use. Record the failure time value of these devices and use it to calculate the acceleration coefficient. Then use these factors to calculate the fault time under normal operation conditions. The value shown in Table 7 is the minimum value of the following two values:

ensure the value of the continuous service life for at least 50 years.

maximum working voltage approved by CSA/VDE.

It should also be noted that the life of AD7400A changes according to the waveform type applied to the isolation grid. Depending on whether the waveform is bilateral communication, single pole communication, or DC, the insulation structure of the I coupling device will be under different pressures. Figure 30, Figure 31 and Figure 32 show different isolation voltage waveforms.

The size of the shape