Features

0.7a DC output current

2. V to 18 V input voltage

output voltage can be adjusted from 0.6 V

250 kHz switch frequency, programming up to 1 MHz

Internal soft start and inhibition

Low voltage difference operation: 100%duty cycle

Voltage feedback

] Air load current operation

overcurrent and heat protection

VFQFPN8 3 mm packaging

Consumer: set -top box, DVD, DVD burning Machine, car audio, LCD TV and display

Industry: Charger, PLD, PLA, FPGA

Network: XDSL, modem, DC-DC module

Computer: CD Storage, hard disk, printer, sound card/graphics card

LED driver

Instructions

L5980 is the minimum embedded power AMOSFET, which is the lowest voltage switch regulator, so it can provide more than 0.7A The DC current of the current load depends on the application conditions. The input voltage range from 2.9 to 18 volts, and the output voltage can be from 0.6 V to Vin. The minimum input voltage is 2.9V, and the device is also applicable to the 3.3V bus. The minimum external component is required. The device includes an internal 250 kHz switch to the external frequency oscillator to 1 MM. The FVQFPN package with an outer outer pad allows it to be reduced to about 60 ° C/W.

Electric characteristics

1. In the temperature range of -40 to+125 ° C, refer specification. The specifications with a temperature range of -40 to+125 ° C are guaranteed by design, representation and statistical correlation.

2. Design guarantee.

Function description

L5980 is based on the ""constant frequency control mode"". The output voltage VOUT is controlled by the feedback pink (FB) to provide an error signal. Compared with the sawtooth wave with a fixed frequency, it controls the power switch. The main internal module is shown in the box diagram in Figure 3. They are: a full -integrated oscillator, providing jagged waves to adjust the duty cycle and synchronization signals. Its switching frequency can be adjusted by external and external. Realize the feedback of voltage and frequency. Z soft start circuit to limit the influx of the starting phase. The pulse width of the voltage mode error amplifier amplifier width modulation and the relevant logical circuit power switch required for internal circuits. High -voltage side driver of the embedded Poro -Porter power MOSFET switch. zThe peak current limits the induction block, which is used to handle overload and short circuit. Z A pressure regulator and internal benchmark. It provides internal circuits and provides fixed internal reference. A voltage monitoring circuit (UVLO), which is used to check input and internal voltage. Hot blocks to prevent heat out of control.

oscillator and synchronization

FIG. 4 shows the frame diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock. The frequency depends on the resistor unnecessary connected to the FSW. If the FSW pin is kept floating, the frequency is 250 kHz; it can be increased to as shown in Figure 6 and is grounded by the external resistor. In order to improve the template performance of the line and keep the PWM gain and input keep the constant voltage, the voltage feedback is to achieve changes based on the input voltage (see Figure 5.A) by changing the slope of the jaggedness. If the oscillator frequency increases the external resistor. In this way, the frequency feed (Figure 5.B) is achieved to keep the PWM gain and the switch frequency constant (see Section 5.4 expression). Synchronous signals are generated on the synchronous pipe foot. The phase shift of this signal is 180 ° with the clock. When the two devices are synchronized, this delay is very useful to connect the synchronous pins together. When connecting the synchronous pipe foot, the high oscillator frequency of the device is used as the main device, so the device is switched from the frequency but delayed for half a cycle. In this way, the average root value of the current can be reduced to the maximum extent.

This device can work simultaneously to feed the external clock signal at a higher frequency. Synchronous changes to the zigzal wave amplitude and change the pulse width adjustment gain (Figure 5.c). When studying the stability of the ring, this change must be considered. In order to minimize the change of the PWM gain, the free running frequency (the resistance on the FSW pin) should be set only slightly lower than the external clock frequency. This changes in the pre -adjustment frequency will change the tap tooth slope to obtain neglected truncated serrated, due to external synchronization.

Soft start

Soft start is the key to ensuring the correct and safe startup of the booster variable. It avoids the impact of excitation surge, making the output voltage rising single. Soft start is an amplifier executed by the staircase slope on the wrong non -turning input (VREF). Therefore, the output voltage conversion rate is:

Among them, SRVREF is a non -inverter input conversion rate, while R1 and R2 are the resistance division of the resistor to adjust the output voltage (see Figure 7) Essence Soft start stairs include 64 steps from 0 V to 0.6 V, each 9.5 MV. The time base of one step is 32 clock cycles. So the converting time and output voltage conversion rate depends on the switch frequency

For example, when the switching frequency is 250 kHz, the SSTIME is 8 ms 8 ms.Essence

error amplification and compensation

Error amplifier (E/A) provides error signal execution pulse width comparison with jagged waves. Its non -inverter input is connected to the 0.6V voltage benchmark internally, and its inverter input (FB) and output (comp) are external available for feedback and frequency compensation. In this device, the error amplifier is a voltage modulus calculation amplifier with high DC gain and low output impedance. The characteristics of non -checked errors are as follows:

In continuous conduction mode (CCM), the transmission function of the power segment has two poles and output capacitors generated by LC filters and output capacitors Zero points produced by ESR. According to the output ESR value, various compensation network capacitors can be used. If the zero point introduced by the output capacitor will help compensate the LC filter, the bipolar of the LC filter can use type II compensation network. Otherwise, the type must be used to use the compensation network (the relevant compensation network selection). In any case, the method of compensation cycle is to introduce zero to obtain a safe phase.

Over -current protection

L5980 implements over -current protection sensor flow and excessive power MOSFET. Due to the noise generated by the power MOSFET switch activity, the current response is disabled in the initial stage of the conduction time. This can avoid failure to detect the failure state. This interval is usually called ""cover time"" or ""blank time"". The cover time is about 200ns. When the current is detected, according to the operating conditions.

1. Output voltage adjustment. When the current is detected, the power MOSFET is closed and the internal reference (VREF), which will set the error amplifier to zero and maintain this state clock cycle within the soft start time (TSS, 2048)). After this period of time, a new soft start -up stage occurred, and internal references began to tilt (see Figure 8.A).

2. Soft start phase. If the current limit is reached, the power MOSFET is closed to achieve pulse over flow protection. In the soft start phase, in the case of overcurrent, the device can skip the pulse to maintain the output current constant equal to the current limit. If the current is higher than the current threshold at the end of the ""cover time"