Features

*256-bit end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ

*Compact MSOP-10 (3 mm × 4.9 mm) packaging [123 123 ]

*Choose SPI/I2C compatible interface

*Extra -package address decoding AD0

*complete read/write of the wiper register

*Open the pre -pre -pre -pre -pre -pre -pre -pre -pre -pre -pre -based Set the medium -scale power supply

*Single power supply 2.7 V to 5.5 V

*Low temperature coefficient 45 ppm/℃

*low power consumption, IDD 8 Wei'an [ 123]

*Wide working temperature — 40 ° C to+125 ° C

*SDO output allows multiple equipment chrysanthemum chains

123]

The replacement of the mechanical potentiometer in the new design

*pressure, temperature, location sensor adjustment,

*Chemical and optical sensor

*RF amplifier Partial pressure

*Auto electronic adjustment

*gain control and offset adjustment

Overview

AD5161

is 256 position adjustment adjustment adjustment The application provides a compact 3mm × 4.9 mm packaging solution. These devices execute the same electronic adjustment function as mechanical potentiometers or variable resistors, and have enhanced resolution, solid -state reliability and superior low -temperature coefficient performance.

The wiper settings can be controlled by a SPI that can be selected or compatible with I2C, and can also be used to read the wiper register content. When using the SPI mode, the device can be a chrysanthemum chain (SDO to SDI), allowing multiple components to share the same control line. In the I2C mode, the address pin AD0 can be used to place up to two devices on the same bus. In the same mode, the command position can be used to reinstate the position of the water scraper to the medium scale or the closing device to enter the zero power consumption state.

Working under 2.7 volt to 5.5 volt power, the power consumption is less than 5 Weire, which can be used for portable battery power supply applications.

Note: The terms of terms, virtual reality, and RDAC can be used for use.

Typical performance features

Test circuit Figure 27 to FIG. 35 illustrates the test conditions used in the defined product specification table.

SPIInterface

I2C interface

s Starter condition p Stop conditions

A Confirm

x Do not care w write

r Read

RS reset the wiper to the medium size 80 hours

SD shut down the wiper to the B terminal and disconnect A. It does not change the contents of the wiper register.

D7, D6, D5, D4, D3, D2, D1, D0 Data Bit

Operation

AD5161 is a 256 256 Ploth digital control variable resistor (VR) device.

The internal power supply opens the preset and places the wiper during the medium scale in the process of power, and simplifies the failure state recovery during power -power.

Variable resistance programming

The pumping resistor operation

The naming resistance between the terminal A and B is 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The last two or three digits of the part number determine the nominal resistance value, such as 10 kΩ 10; 50 kΩ 50. The nominal resistor (R) of the VR has 256 contact points, which is in contact with the B -terminal through the water scratch terminal. The 8 -bit data in the RDAC memory is decoded to select one of the 256 possible settings. Assuming that the 10 kΩ components are used, the first connection of the wiper starts with the B terminal of the data 0x00. Due to the existence of a 60Ω wiper contact resistance, the minimum 60Ω resistor is generated between terminal W and B. The second connection is the first tap point, corresponding to the data 0x01 99Ω (R/256+R 39Ω+60Ω). The third connection is the next tap point, indicating that the data 0x02 is 177Ω (2 × 39Ω+60Ω), and so on. Every time a LSB data value is added, the wiper will move up the resistance ladder until the last tap point reaches 9961Ω (R -1 LSB+R). FIG. 41 shows the simplified diagram of the equivalent RDAC circuit, where the last resistance string will not be accessed; therefore, in addition to the wiper resistance, the LSB of the nominal resistor at the full label is small.

The general formula of determining the digital programming output resistance between W and B is:

Among them, D is loading The decimal equivalent of the binary code in the 8 -bit RDAC register, R is the end -to -end resistance, and R is a wiper resistor generated by the internal switching resistance.

In short, if R 10 kΩ and the A terminal opens the way, the RDAC lock in the shownCode setting the following output resistance R.

Note that under the condition of zero scale, a limited wiper resistance of 60Ω exists. In this state, you should pay attention to limit the current between W and B to the maximum pulse current not exceeding 20 mAh. Otherwise, the internal switching contact is degenerate or damaged.

Similar to the mechanical potentiometer, the RDAC resistance between the water scraper W and the terminal A also generate digital control complementary resistance R. When using these terminals, the B terminal can be opened. Set the resistance value of R starts with the maximum value of the resistance, and decreases as the data value loaded in the lock memory. The general equation of this operation is:

If the R 10 kΩ opens the road and the B terminal will be opened, the output resistance R will be set to the RDAC lock code.

The typical equipment matching the equipment depends on the process batch, and its change may be as high as ± 30%. Because the resistance element is processed by thin -film technology, R changes with a very low temperature coefficient of 45 PPM/℃ with temperature changes.

Programming the potential scorer

Voltage output operation

Digital potentiometer is easy The voltage is a proportional pressure division. Unlike V to GND (must be positive), the voltage between A-B, W-A and W-B can be arbitrary polarity.

If the impact of the wiper resistance on the approximate value, connect the A terminal to 5 V and the B terminal to the ground, the output voltage will be generated when the wiper is connected to B, from 0 V to less than 5 V 1 LSB. The voltage of each LSB is equal to the 256 positions of the voltage applied on the AB terminal to remove the potentiometer. The general equations that define any valid input voltage on the terminal A and B relative to the V output voltage of the ground is:

For more accurate calculations, including the wiper resistance V v The influence can be found:

The operation of the digital potentiometer in the signs mode will lead to more accurate ultra -temperature operations. Unlike the resistor mode, the output voltage mainly depends on the ratio of internal resistance R and R, not an absolute value. Therefore, temperature drift is reduced to 15ppm/℃.

Pack selected digital interface

AD5161 provides the flexibility of optional interface. When the digital interface selection (DIS) pin is connected low, the SPI mode is connected. When the DIS pin is connected, the IC mode is connected.

SPI compatible 3 -line serial bus (DIS 0)

AD5161 contains a 3 -line SPI compatible digital interface (SDI, C C, C C, C. CS and CLK). 8 -bit serial characters must be loaded first. The format of the word is shown in Table 5.

A sensitive CLK input of the positive edge needs to be converted cleanly to avoid timely timing of incorrect data into serial input registers. Standard logic family works well. If a mechanical switch is used for product assessment, it should be triggers or other appropriate methods. When the CS is low, the clock loads the data to the serial register on the edge of each positive clock (see Figure 36).

The data settings and data maintenance time in the specification table have determined effective timing requirements. AD5161 uses an 8 -bit serial input data register. When the CS line returns the logic high -electricity, the word is transmitted to the internal RDAC register. Ignore the extra MSB bit.

Chrysanthemum chain operation

Serial data output (SDO) pin contains a leakage N -channel FET. This output requires a pull -up resistor to transmit the data to the SDI pin of the next software package. This allows several RDACs of the chrysanthemum chain of the serial data cable of a single processor. The voltage of the pull -up resistance end can be greater than the V power supply voltage. It is recommended to increase the clock cycle when using a pull-up resistor on the SDI pin of the following device, because the capacitor load at the chrysanthemum chain node SDO-SDI between the devices may cause the time delay of the subsequent device. Users should realize this potential problem in order to successfully realize data transmission (see Figure 42). If the two AD5161s are chrysanthemum chains, at least 16 -bit data is required. The first 8 bits are conforming to the format as shown in Table 5, turn to U2, and then turn to U1 in the same format. In all 16 bits entering their own serial registers. After that, the CS is pulled to complete the operation and loads the RDAC lock. If the datawords during the CS low period are greater than 16 bits, any additional MSB will be discarded.

I2C compatible 2 -line serial bus (DIS 1)

AD5161 can also be controlled by a serial bus compatible with IC. RDAC is connected from the device to this bus.

The first byte of AD5161 is from address bytes (see Table 6 and Table 7). It has a 7 -bit address and a R/W bit. The six MSBs of the machine address are 010110, and the following bit is determined by the state of the device's AD0 PIN. AD0 allows users to place up to two devices compatible with IC on a bus.

2 line IC serial bus protocol operation is as follows:

1. The host starts the data transmission by establishing a startup condition, that is, when the SCL is high, the SDA line occurs from high to low on the SDA line. Conversion (see Figure 39). The following bytes are from the address byte, which includes 7 digits from the machine address, and then a R/W bit (the digit decides to read or write data from the machine device).

The address corresponds to the passage of the sending address through the ninth pmDuring the bell pulse, the SDA cable is pulled down to respond (this is called the confirmation position). At this stage, all other devices on the bus remain free, and the selected device waits for the data to write or read its serial register. If R/W is high, the host will read the device. On the other hand, if the R/W bit is low, the main device will be written into the device.

2. The additional instruction bytes that contain the read operation without reading operations. The instruction bytes of this mode of writing mode follow the address byte byte. The first (MSB) of the instruction byte is a byte that does not need to be concerned.

The second MSB, RS, is a medium -scale reset. The logic high on this bit moves the wiper to the center tap, R r. This function effectively covers the contents of the register, so when the resetting mode is exited, RDAC will remain at medium scale.

The third MSB, SD, is a closed position. When the wiper is short -circuited to the terminal B, the logic is high and the terminal A is disconnected. This operation generates almost 0Ω in the transformer mode, and 0 V is generated in the potential mode. It should be noted that the shutdown operation does not interfere with the contents of the register. After closing, the previous settings will be applied to RDAC. In addition, new settings can be programmed during shutdown. When the part is returned from the closure state, the corresponding virtual reality settings will be applied to RDAC. The rest in the instruction bytes are not important (see Table 6).

3. After confirming the instruction by byte, the last byte in the writing mode is data byte. The data is transmitted through serial bus with the order of 9 clock pulse (after 8 data bit). The transition on the SDA line must occur at the low period of SCL and maintain stability at the high period of SCL (see Table 6).

4. In the reading mode, the data byte follows the confirmation of the bytes of the machine. The data is transmitted in the order of 9 clock pulses (slightly different from the writing mode, and there are 8 data bits and one confirmation position). Similarly, the transition on the SDA line must occur at the low period of SCL and maintain stability at the high period of SCL (see Figure 40).

5. When all the data bit has been read or writes, the host will establish a stop condition. The stop condition is defined as a conversion from low to high on the SDA line when SCL is high. In the writing mode, the host will pull the SDA cable to high during the tenth clock pulse to establish a stop condition (see Figure 39). In the reading mode, the host will no " confirmation of the ninth clock pulse (that is