Features

*5V high-speed rapid settlement

*110 MMC, -3 decibel bandwidth (g +1) ( AD8051 / AD8052 [123 ])

*150 MMH, -3 decibel bandwidth (g +1) ( AD8054 )

*145V/μs conversion rate

* 50 ns settlement time to 0.1%

*Single power operation

*Output within the 25 MV range of any orbit

*Input voltage range: 0.2 V to +4 V ; Vs 5 v

*Video specification (G +2)

*0.1db gain flatness: 20MHz; RL 150Ω

*Differential gain/phase: 0.03%/0.03 °

*Low distortion-80 DBC total harmonic@1 MHz, RL 100Ω

*Excellent load driving capacity

*Drive 45 mAh 45 mAh , 0.5 volt power rail (AD8051/AD8052)

*Drive 50 PF capacitor load (G +1) (AD8051/AD8052)

AD8054)

*Low power consumption: 4.4 mAh/amplifier (AD8051/AD8052)

Digital drive

*clock buffer

*Consumer video

*Professional camera

*CCD imaging system

*CD/ DVD CD

Generally explained

AD8051 (single), AD8052 (dual) and AD8054 (4) are low -cost, high -speed, voltage feedback amplifiers. The amplifier works at a low power current on +3 V,+5 V or ± 5 V power supply. They have real single power capabilities, and the input voltage range is 200 millivoltors below the negative, within 1 volt of the orbit.

Despite the low cost, AD8051/AD8052/AD8054 has excellent overall performance and multifunctional. The output voltage fluctuates within the 25 millivoltage range of each orbit, providing the maximum output dynamic range and excellent speeding recovery.

AD8051/AD8052/AD8054 is very suitable for video electronic devices, cameras, video switches or any high -speed portable equipment. Low distortion and rapid settlement make them active filterThe ideal choice of 波 application.

8-AD8051/AD8052 in SOIC SOIC SOIC, AD8052, 14-Direction SOIC in MSOP AD8054 and 14-Viter TSSOP packaging can use.

Thermal resistance

This specification is suitable for devices in free air.

Maximum power consumption

AD8051/AD8052/AD8054 The maximum power that can be securely dissipated is limited by the increase in knot temperature. The maximum safe connection temperature of the plastic packaging device is determined by the glass of the plastic (about 150 ° C). Temporarily surpassing this limit may cause the parameter performance to change due to changes in the stress applied to the mold. The knot temperature that exceeds 175 ° C for a long time will cause equipment failure.

Although AD8051/AD8052/AD8054 has internal short circuit protection, this is not enough to ensure that it will not exceed the highest cordon (150 ° C) under all conditions. To ensure normal operation, the maximum power reduction curve must be observed.

Typical performance features

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Operation theory

Circuit Description

AD8051/AD8052/AD8054 is a Devices, Inc. Private ultra -fast complementary complement made on the simulator machine. The double pole (XFCB) process can build PNP and NPN transistors similar to FTS in the 2GHz to 4GHz area. This process is insulating to eliminate parasites and locks caused by isolation. These characteristics are allowed to build high -frequency, low -deformed large -scale and low power currents. This design uses differential output input levels to maximize bandwidth and clean air (see Figure 40). The smaller signal parts required for the first -level output (node SIP, SIN) reduces the impact of non -linear current caused by knotting capacitors, and improves distortion performance. This design realizes the harmonic distortion of -80 DBC@1 MHz to 100Ω on a single 5V power supply, V 2V P-P (gain +1).

The input of the device can process the voltage within the range of the rail 1 V below the track 1 V. More than these values will not cause phase reversal; however, if the input voltage exceeds 0.5 V, the ESD device will start to start. Under such driving conditions, the output is kept on the track.

AD8051/AD8052/AD8054 rail -to -orbit output range is input by a complementary public transmitterProvide at the level. The high output driver capacity is achieved by directly injecting the front current of all output levels into the output device Q8 and Q36. The bias of Q8 and Q36 are completed by I8 and i5 and the feedback circuit (not displayed) of the common mode. This circuit topology structure allows AD8051/AD8052 to drive 45 mAh output current, and allows AD8054 to drive 30 mAh output current, and the output voltage is within the 0.5 volt range of the power rail.

Application information

Specific recovery

When exceeding the output and/or input range, the amplifier is driven. The amplifier must be recovered from this speeding state. As shown in Figure 41, AD8051/AD8052/AD8054 is restored within the negative speed 60 ns and recovered within 45 ns of the positive speed.

Drive capacitance load Assuming AD8051/AD8052 under the closed -loop gain of +1,+v 5V, the load is 2kΩ, and it is parallel with 50PF. Figures 42 and Figure 43 show their frequency and time domain responses to small signal incentives, respectively. AD8051/AD8052/AD8054 capacitance load driver can be achieved by adding a low -value resistance connected to the load. Figures 44 and Figure 45 show the effects of a series resistance on the capacitor drive of a variable voltage gain. With the increase of closed -loop gain, larger phase margin allows greater capacitor loads and less peak values. Adding a series of connected resistors with a lower closed -loop gain can also achieve the same effect. For large capacitor loads, the frequency response of the amplifier is mainly determined by the attenuation and load capacitance of the series resistance.

Precautions for layout

AD8051/AD8052/AD8054 specified high -speed performance requirements carefully pay attention to circuit board layout and component components carefully choose. The choice of appropriate radio frequency design technology and low parasites is necessary.

PCB should have a ground plane that covers all the unused parts on the side of the circuit board component to provide a low impedance path. The ground plane should stay away from the area near the input pin to reduce parasitic capacitors.

Power capacitors should be used for power bypass. One end should be connected to the ground plane, and the other end should be within the 3 mm range of each power. Another large (4.7 μF to 10 μF) 钽 钽 钽 钽 electrolytic container should be connected in parallel, but it does not have to be so close to provide current provides current for fast and large signal changes at the output end.

The feedback resistance should be close to the reverse input pin to minimize the parasitic capacitor of the node. The parasitic capacitor of the inverter input is less than 1PF, which will significantly affect high -speed performance.

For the long signal (greater than about 25 mm), a strap line should be adoptedDesign technology. These should be designed as a 50Ω or 75Ω characteristic impedance, and each end is correctly connected.

Active filter

A higher -frequency active filter requires wider bandwidth op amp to work effective. The excessive phase shift generated by low -frequency operation amplifiers will significantly affect the performance of the active filter.

FIG. 46 shows an example of the 2 MHz dual -bandwidth filter of the three MHz dual bandwidth filters using AD8054. This circuit is sometimes used in the medical ultrasound system, reducing the noise bandwidth of the analog signal before the modulus conversion.

Please note that the input terminal of the unused amplifier should be connected to the ground.

The frequency response of the circuit is shown in Figure 47.

Simulation-Digital and Digital-Simulation Application

Figure 50 is a schematic diagram, which show The drive of the converter. This converter is used to convert the i and Q signals in the communication system. In this application, only the i -channel is driven. Enable the I channel through the application logic high selection (pin 13).

AD8051 runs from the dual power supply and configures to gain +2. The input signal is terminated at 50Ω and the output is 2V P-P. This is the largest input range of AD9201. The 22Ω series resistance limits the maximum current and helps reduce the distortion of ADC.

AD9201 has different inputs for each channel. These are specified as A and B inputs. The B input of each channel is connected to VREF (pin 22), and VREF provides a positive reference voltage of 2.5V. Each B input has a small low -pass filter, which also helps reduce distortion.

The output of the op amp was coupled to INA-I (PIN 16) through two parallel container AC to provide good high-frequency and low-frequency coupling. The 1kΩ resistor references the signal to VREF applied to Inb-I. Therefore, compared to the bias voltage applied to INB-I, INA-I swing positively at the same time.

In the case of 20 milliseconds/second of the sample clock, the digital analyzer analyzed the output of simulation to numbers. Two input frequencies: 1 MM and 9.5 MM, these two frequencies are just lower than Nakist frequency. These signals are well filtered to minimize any harmonics. FIG. 48 shows the ADC FFT response in the case of 1 MHz analog input. SFDR is 71.66DB, and the simulation number generates 8.8NOB (valid bit number). When the analog frequency increases to 9.5MHz, the SFDR is reduced to -60.18dB, and ADC works at 8.46NOBS, as shown in Figure 49. The circuit contains AD8051 without deteriorating AD9201.

Synchronous stripper

Synchronous pulses are sometimes carried on the video signal, so that no separate channels are required to carry synchronous information. However, for some functions, such as simulation to digital conversion, it is not advisable to have synchronization pulses in video signals. These pulse reduces the dynamic range of video signals and does not provide any useful information for such functions.

Synchronous stripper removes synchronous pulses from the video signal while passing all useful video information. Figure 51 shows a practical single power circuit using a single AD8051. It can directly drive the reverse terminal video cable.

Video signal plus synchronous application to non -vertical input, and there are appropriate terminals. The amplifier gain is set to 2 by the two 1 kΩ resistors in the feedback circuit. The bias voltage must be applied to the R1 to make the synchronization pulse of the input signal be stripped at the appropriate level.

Inputting the videos of the video pulse is an ideal location for removing synchronous information. This level is multiplied by the amplifier 2. This level must be at the ground at the output end to perform synchronous peeling operations. Because the amplifier from the input of R1 to the output gain is -1, the voltage equivalent to 2 × V must be applied to make the cadre levels coming out of the ground. Blank

Single -power composite video line drive

Many composite video signals have a hidden level on the ground and have positive and negative video information. This signal requires a dual power amplifier to pass. However, through the shift of the AC level, you can use a single power amplifier to pass these signals. These technologies may cause the following complications.

The boundary-peak-peak signal of the duty cycle-occupying ratio of the duty cycle needs to be more dynamic with the mobility-peak-peak amplitude capacity than its (bounded) peak-peak. The worst case is that the dynamic signal swing will be nearly twice the peak value. Two conditions for defining the maximum dynamic swing are one signal. This signal is usually low, but the duty cycle is relatively high. The occupation ratio is only one percent of a small part, and the other is defined by the opposite condition.

The worst case of a composite video is not so high. A boundary condition is that for the entire frame, most of the signals are black, but at least once in the frame with the smallest width of the white (full amplitude).

Another extreme is all white video signals. This signal's faint interval and synchronization prompts have negative drifts that meet the composite video specifications. The combination of horizontal and vertical removal intervals limits this signal at the highest (white) level at about 75%.

Due to the duty ratio between the two extremes above, the 1V P-P composite video signal multiplied by gain 2 needs to swing about 3.2V P-P at the output end, so that the computing amplifier can pass arbitrarily without the inconsistency of the inconsistency. ChangeEmpty composite video signal.

Some circuits use the synchronous cutting tip to keep the cutting tip at a relatively constant level to reduce the required dynamic signal swing. However, these circuits may have pseudo -shadows, such as synchronous cutting -edge compression, unless they are driven by source with very low output impedance. AD8051/AD8052/AD8054 has sufficient signal swing when running on a single 5V power supply to process a composite video signal with AC coupling.

The input of the circuit in FIG. 52 is a standard composite (1V P-P) video signal, which has an anti-hidden level on the ground. Enter the network level through AC coupling mobile video signals. The non -vertical input bias of the operation amplifier is half of the power supply voltage.

The feedback circuit provides a unit gain for the input DC bias, and provides the gain of 2 in any signal in the video bandwidth. The output terminal is coupled and used to drive the line.

Select the capacitor value to provide the minimum tilt or field distortion of the video signal. These values are necessary for videos regarding the quality of the studio or broadcast. However, if you only expect a low -expected video (sometimes referred to as consumer video), the value and cost of the capacitor can be reduced by up to five times, and the visible degradation in the image is the least.

The size of the shape