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2022-09-21 17:24:28
A4490 is a three -output reduction switch stabilizer
Features and advantages
#9642; Three antihypertensive converters
#9642; 4.5 to 34 v input voltage range#9642; 550kHz fixed fixed Frequency
#9642; Multi -phase switch
#9642; Independent control of various variants
#9642; #9642; internal compensation
#9642; 4 × 4 mm qfn packaging, PCB occupies small space
Packaging: 20 contact QFN (suffix ES)
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Explanation
A4490
High -frequency switch allows choosing cheap inductance and small ceramic output capacitors. The turning cycle of the regulator is staggered to minimize the stress on the capacitor and reduce the electromagnetic interference. The charge pump is used to provide the power supply that drives the power switch to ensure that it works under a very wide job occupation ratio, and avoids the need for the power discharge clamp circuit. Internal diagnosis provides comprehensive overload, input arrears and overheating protection.
A4490 uses 20 contacts, 4 mm × 4 mm, 0.75 mm nominal total height QFN, with exposed pads to enhance heat dissipation. No lead, 100%matte tin plating lead frame.
Applications include:
#9642; Photo, inkjet and portable printers
#9642; Industry
#9642; handheld equipment
#9642; Portable application
Typical application
Figure Figure
Function description
Basic operation
A4490 contains three fixed frequency buck switch converters with peak current mode control (including slope compensation). Each converter can open and close independently by activating the high level enable input (EN1, EN2, and EN3). When enabled, the corresponding lossesStart under the control of the soft startup program, so as to avoid the output voltage super adjustment and minimize the input wave current. 
At the beginning of each switching cycle, the antihypertensive switch was turned on. When the level of the current signal of the switch reaches the level of the current requirements signal, the connection time of the switch is terminated. In the next switch cycle, turn on the switch again and repeat the cycle.
A shared clock is used to define the switch frequency of each regulator. Each cycle of the three switching cycles (REG1, REG2, and REG3 moves 120 ° each other to minimize the pulse current absorbed from the input filter capacitor as much as possible. Under certain conditions, for example, under low VBB conditions and relatively high users set output voltage, the switch overlap between channels is inevitable.
Under the condition that the duty occupation ratio (DC) is less than the minimum value, such as light load or high VBB voltage, the converter enters the pulse jump mode to ensure the adjustment.
Provide a charge pump regulator to ensure that all three power switches have sufficient gate drivers throughout the entire input voltage range. The regulator allows to run under a very wide working load cycle. At the initial power, the internal regulator is used to provide bias power for the control function on the chip.
In the case of short -circuit or overload, each regulator channel uses a pulse current limit. If the overload time is long enough, the temperature of the integrated circuit may rise to enough to make the heat clearance circuit work. Under the control of the soft startup circuit, this part will be restarted automatically after eliminating the conditions of the heat ban, and assuming that all other conditions are met and automatically restarted. For more information, see the shutdown part.
Power configuration
A4490 supports the alternative to providing logical power voltage on the VDD pin. In addition, you can use VBB or ENB tube feet to call for ICs.
For VDD power supply, to minimize power consumption, especially under high input voltage, it is recommended to use external power supply on the VDD input pin. Generally, the voltage comes from one of the three adjustment outputs set between 3.3 and 5 V (VregX).
Another advantage of power supply for VDD from the outside is that the VBB owed voltage lock level is reduced. In order to maximize the operation time of the switch under VBB power off, support two optional voltage shutdown conditions, depending on the realized VDD power supply configuration. If the external VDD is not applied, VBB, VBBUV (SD) is a typical 4.1V. When an external VDD is used, the minimum value of VBB and VBBCPUV (SD) is usually 3.5 V.
One point that needs to be noticed from Vreg output VDD: During the initial application of VBB, since Vreg has not reached the specified value, the internal bias power supply will automatically start from the internal regulator. This means that the starting threshold is determined by VBBUV (SU) (4.3V typical value) because there is no external VDD. When Vreg began to provide VDD to the outside, the closing threshold was reduced to VBBCPUV (SD) (typical value was 3.5 V). This assumes Vreg exists.
Use VBB to power on Figure 1. Each enable input (ENBX) is connected to the VBB orbit through the 100 kΩ resistor to maintain a high level. VDD is powered by a regulator. When the VBB voltage reaches the minimum threshold VBBUV (SU), the charge pump power supply (VCP) rises. When the VBB+VCP reaches the minimum threshold-the old VBBCPUV (SU), the soft startup program of all three regulator channels (VregX) has started (TSS). When the three regulators reach the 85%FBX threshold, start the power -on retirement timer. After the TPOR), PORZ becomes higher, indicating that all regulators and VBB meet the specifications.
When the VBB voltage starts to be lower than the level of the underwriting warning (VBBUV (POR)) 3.6 V (typical values), the PORZ logo reset. This will warn the system controller VBB voltage in advance. Please note that this function can be guaranteed only when VDD is provided outside. During this period, the three switches continued to work.
When the VBB decreased further, the VCP power supply also decreased, which reduced the driving voltage of the series switch. In addition, when these specific converters reach the corresponding maximum duty cycle (DMAX), high -voltage tracks begin to lose adjustment first.
The voltage with a lower output voltage reaches a certain degree of steady state before the power is disconnected by the A4490. At this time, all the corresponding VBB underwriting thresholds have been reached. For example, if the VDD power is exported from the outside, the 1V output may continue to work to a 3.4V VBB (typical value). The degree of influence depends on many factors, including input and output filter capacitors, output loads, gate driving amplitude, MOSFET RDS (on), and so on. 
VBB existence, UVLO starting threshold, VBBUV (SU) and VBBCPUV (SU) have been reached. Each regulator is enabled in turn. Initially, Vreg1 was activated and started under the control of the soft startup circuit (TSS). Before Vreg1 reached 85%FB1, Vreg2 was enabled and started with a separate soft start control.
When both regulator reaches the 85%FB threshold, start the power -on reset (POR) timer. Please pay attention, only in the placeThe enabled regulator reaches its corresponding 85%FB level before the POR timer can be enabled. After the TPOR passed by the power -to -power reset time, if the FB level of Vreg1 and Vreg2 is not lower than its 80%FB level, the PORZ signal will become higher.
Later, if Vreg3 is enabled, PORZ is reset, and Vreg3 is started under the control of the soft startup circuit. When the 85%FB3 threshold is reached, the Por timer is activated. After TPOR, if all FB levels are higher than their respective 80%FB levels, the PORZ signal will become higher.
Note that if any regulator channel is not enabled, the channel will not affect Pots. In order to avoid multiple signals of the PORZ signal, the system is recommended to be designed to be within the scope of the specifications before TPOR's past.
If any regulator channel drops below 80%FB, the PORZ signal will be reset. If the voltage is then restored to 85%FB, the Por timer is activated again. Note that when the feedback voltage drops below 80%FB level, the soft start will not start. This is to allow quickly to restart automatically when overloaded or similar failures. If you need to start softly, it is recommended to disable the system controller when receiving the PORZ reset signal, and then re -enable the relevant regulator channel again. Once the last regulator is disabled, the PORZ signal is reset.
Power -power reset and power -to -power reset duration (TPOR) is determined by selecting an appropriate capacitor connected to the CPOR pin. The value of the TPOR can be determined by the following formulas:
When both VBBs are higher than the level of the underwriting warning, the FB pins of the regulator enabled are greater than the V RRG voltage than the VREG voltage At 85%, the PORZ output will become higher.
Since the external capacitor is charged through a 5μA current source, you must be careful in the layout to avoid additional leakage paths. The capacitor should be close to the CPOR pin, and the grounding connection with the A4490 GND pin should be as short as possible.
It is recommended to set the TPOR cycle to the startup phase that exceeds all three regulators to avoid the possibility of Porz output multiple triggers. 
Among them The values between 4.7 and 12 kΩ should be between GND and FB1 pins. The R1 is connected between the output guide and the FB1 pin. Vreg1 is the set output regulator voltage. VFB is a reference voltage.
The tolerance of the feedback resistance affects the voltage setting value. Therefore, when determining the number of overall supervision, the tolerance choice must be considered.
Flow from FB1 nodeThe bias current of R2 IBIAS will introduce a small voltage offset to the output terminal.
Establishing each regulator channel can be enabled separately through the corresponding ENBX pin. If any channel is required automatically after the VBB voltage is applied, the specific channel should connect the ENB pin to the VBB guide through the pull -up resistor.
The resistor should be selected to limit the current to the range of less than 1 mAh than the maximum specified value. This prevents the internal protection clip from opening. It is recommended to use a 100 kΩ pull -up resistor. This will ensure that when VBB 36V, the current is kept below the maximum value.
Each regulator channel of the soft start contains a soft startup circuit. When the appropriate regulator enable input setting is high; VBB, charging pump and bias power supply voltage higher than the minimum value; and when there is no heat shutdown conditions, the soft start of the loop is started. Note that overload or short circuit will not cause a soft start cycle, unless the heat shutdown incident occurs.
During the soft start of the loop, the reference voltage from 0 to 0.8 V (typical values), in turn forced the current demand signal to increase linearly.
When the heat shutdown incident or VBB was under pressure, all converter channels were disabled (VBBUV (SD) or VBBCPUV (SD)).
Once the above failure conditions are eliminated, and assuming that ENB input is enabled, the appropriate channel will automatically restart under the control of soft start.
The typical peak current limit of each channel is limited to at least 2.5 A, and the duty cycle is 0.9. The minimum current limit appears when the maximum duty occupation ratio (0.9) is the greatest impact of slope compensation in this case. As the duty occupation ratio decreases, the current limit is increased. This means that for the narrow application of work cycle, it can work in the case of load current greater than 2.0A.
FIG. 3 shows the typical peak current limit and the duty cycle. For example, it can work in the case that the peak current limit is 3.75 A and the duty cycle is 0.3.
In addition to ensuring that no peak current limits are not exceeded, under the worst load and input voltage conditions, it is also important to check the impact on thermal performance.
Component selection
The induction of the induction of the electrical value L determines the ripple current. Make sure that in the worst case, no minimum current limit is: VBB (min), ILOAD (MAX), FSW (min), and L (min).
It is recommended to use the gap iron oxygen solution instead of the powder iron solution. The latter shows a relatively high magnetic core loss and has a great impact on long -term reliability.
The inductor is usually specified at the two current levels, and the square root current and saturated current are specified. Regarding the average root current, it is important to understand how the average root current level is based on the environmental temperature regulations. Some manufacturers only quote the environmental temperature, while other manufacturers quotate the self -feel temperature risetemperature. For example, if the rated temperature of the inductor is 85 ° C and the self -sensing temperature of 25 ° C under the maximum load, the inductor cannot work safely under the full load to work more than 60 ° C. The ambient temperature. The average root current can be simply assumed to be the maximum load current, and there may be a certain amount of margin to allow overloads.
The first phase of determining the value of the inductor is the peak ripple current of about 20%to 25%of the maximum load.
The maximum peak ripple current Iriple appeared under the maximum input voltage. Therefore, it should be found in these conditions (for Vreg1 channels):
Among them, VF is the positive pressure drop of the re -cycle diode. 
The maximum peak current can be found from it to ensure that it does not exceed the saturated current level of the selected electrical sensor:
The recommended inductor manufacturer and range are the scope of the recommended inductor manufacturer. :
Taiyo Yuden: 1.5 A output NR6045 series
Taiwano Yuden: NRG4026 series, for 1.0A output
#8226 ; Sumida: CDH74 series, used for 1.5 A output 
output capacitors, for consideration of size, cost and performance, it is strongly recommended to use ceramic X5R or X7R capacitor types. When using ceramic capacitors, another important consideration is the effect of electric field on the actual value of the capacitor. In order to reduce the effect of the capacitor with the reduction of the output voltage, the working voltage of the capacitor is recommended to be far greater than the set output voltage. The output voltage of 3.3V and below is recommended to use 6.3V rated capacitors.
For the output voltage of 5V, 10V rated capacitors should be used.
The output capacitor determines the output voltage ripple to close the control loop. In order to ensure stability, the capacitance must increase as the output voltage decreases. From the perspective of ripple voltage, this is actually reasonable, because the ripple voltage is usually specified as a percentage of the output voltage.
The minimum output capacitor under the given output voltage below:
The capacitor value greater than the above value can be used to reduce the effect of bandwidth. This may be necessary in a system with extremely low requirements for ripple/noise.
The output ripple depends to a large extent on the output capacitorIf you observe good layout practice, you can ignore the impact of ESR and ESL.
Output voltage ripples may be approximately:
Input capacitors are strongly recommended to use ceramics, X5R or X7R capacitors.
The value of the input capacitor determines the amount of current (EMI) on the power (VBB power supply) terminal. The current of inflow and outflow input capacitor depends on the relative impedance between the input capacitor impedance and source impedance. In order to obtain a low -impedance filter solution, it is recommended to connect at least two capacitors.
Similarly, the heating effect of the average root current that flows over ESR generally does not need to be considered. In addition, the shift of the input current of each regulator also helps reduce the total balance of the general equalization.
The diode of the anti -stress diode was turned on during the cut off. It is recommended to use the Schottky diode to minimize the forward voltage drop and switch loss.
When the minimum occupation ratio D, the worst case of dissipation occurs at the largest VBB. The average current of the diode is as follows:
Positive voltage drop VF can be found through the actual load current (rather than the average current).
Static power consumption is as follows:
You must also consider the heat rated value Rθ and the ambient temperature of the packaging to ensure sufficient heat dissipation to knot the diode tube tube tuber to knotting the diodes. The temperature is kept in the safety work area of the device. 
Support components POR capacitors (C11), charge pump capacitors (C1), energy storage capacitors (C2), and VDD filter capacitors (C12) should be ceramic X5R or X7R.
Thermal factors
In order to ensure that the A4490 operates in a safe operation area, this actually means that the joint temperature is limited below 150 ° C, and multiple inspections should be performed. The general method is to calculate the specific power dissipation. What kind of thermal impedance (R) is needed at a given temperature to maintain the knot temperature.
Another factor worth considering is that other power consumption components on the system PCB may affect the thermal performance of A4490. For example, the contribution of power loss contributions from re -cycle diode and sensor resistance may cause the knot temperature of the A4490 to be higher than expected.
The following steps can be used as a guide to determine the appropriate thermal solution. It should be noted that this process is usually an iterative process to obtain the optimal solution. These factors can be testedThe following is as follows:
The first step. The highest ambient temperature of the application is estimated to be ta (MAX).
Step 2. Define the maximum knot temperature TJ (MAX). Note that the absolute maximum temperature is 150 ° C.
Step 3. Determine the power consumption in the worst case, PD (MAX).
The assessment should consider these factors under the maximum load and minimum VBB. The influencing factors include switching static and dynamic loss and control loss. The following sections will explain the static loss of switching. The following steps can be used to determine the switch static loss:
Estimated maximum occupy ratio:
where VF is the vF is The forward voltage drop of the Schottky diode under a given load current.
Under the given connection temperature, it is estimated that the RDS of each regulator switch (open):
Note that if the VBB range is limited to 4.5 to from 4.5 to to to the way Between 5.5 V, RDS (open) will increase. For example, as mentioned in the electrical characteristic table, at 25 ° C, the RDS (open) greater than 6 V (open) is a typical 450 MΩ. Under the same temperature conditions, when VBB 4.5V, RDS (on) is usually 560MΩ. For VBB with a voltage between 4.5-6V, RDS (on) can be found through linear approximation. For more information about A4490 between VBB voltage with 4.5 and 5.5 V, see the power configuration part.
You can determine the static loss of each switch: 
Among them, ILOAD is a load of a specific regulator channel.
The following switch dynamic loss can be used to determine the switch dynamic loss: 
The FSW is the switch frequency.
Control losses The following steps can be used to determine the control loss:
Among them, IBBON is a static current when all three regulators are opened.
Total losses can now estimate total loss:
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You can find the RDS (on) of each switch:
The static loss of each switch is as follows:
(b) Switch dynamic loss
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(E) The thermal impedance required for the solution is as follows:
For this special solution, a high -heat efficiency board is required to ensure that the connection temperature is maintained below 115 ° C below 115 ° C Essence In order to get the maximum efficiency, the PCB board area under the A4490 hot board should be exposed copper. Several heating holes (such as between 4 and 8) should be used to connect hot pads to the internal ground plane. If possible, an additional hot copper plane should be applied to the bottom of the PCB and connected to the hot pads of A4490 through the hole.
This calculation assumes that it is not affected by the heat of other components. If possible, it is recommended to install the anti -diode on the back of the printing circuit board. Make sure that low impedance electrical connections are achieved between plates.
The ground surface of the printing circuit board layout guide depends to a large extent on the heat requirements described in the previous section. The ground reference power component should refer to the star -shaped ground far from the A4490 to minimize the problem of ground rebound. 
In order to avoid grounding and offset problems, it is strongly recommended that ground reference feedback resistors (R2, R4, and R6) should be close to the ground connection of A4490 as much as possible.
A local quiet connection ground plane can be achieved around these components, but the ground plane should have high impedance connections connected to the power -class star -shaped connection.
If the ground plane is used, it is recommended not overlapping the joint node (LX1, LX2, and LX3) to avoid the possibility of noise picking. In order to minimize the possibility of noise injection, it is recommended to isolate the ground plane around high impedance nodes (such as: FBX, ENBX, and CPOR).
In terms of power component ground, a star connection should be adopted to minimize the ground circuit impedance. Note that although a ground plane may be required to meet the thermal characteristics of the solution, it is still necessary to achieve grounding star connection for the power component. The grounding of the charging pump (PGND) shall be connected to the heat -through hole. 
FIG. 5 also illustrates the current passing of the current in the switching field effect pipe power. Pay attention to the following points: Capacer CIN should be as close to the VBB terminal as much as possible. The capacitance should be separated between Vreg1 and Vreg3's VBB terminals and Vreg2's VBB terminals.
Vreg1 and Vreg2's VBB terminals should be connected to the VREG3 VBB terminal through a short and wide trajectory.
Each induction device should be as close to the respective switches (LX1, LX2, and LX3) and output capacitors as possible.
FIG. 6 shows the conductive guide path of the switching field effect tube control cycle. Pay attention to the following points:
Diode D should be as close to the switch FET and inductance as much as possible.
support components: POR capacitor (C11), charge pump capacitors (C1), energy storage capacitors (C2) and VDD filter capacitors (C12) should be as close to their respective terminal connections as possible. The grounding reference capacitor should be as close to the ground terminal as possible.
The following three charts show the typical configuration of the power supply to the application. The middle chart corresponds to the typical application shown on the homepage.
Allegro Microsystems, LLC reserves the right to improve according to the requirements of detailed specifications to improve the performance, reliability or manufacturing of their products. Before the order is placed, remind users to confirm that the information it depends is the latest.