特点和优点

#9642; 典型应用，输出额定值高达±1 A，35 V

#9642; 低RDS（开）输出，0.67Ω源， Typical value of 0.54Ω exchange

#9642; automatic current attenuation mode detection/select

#9642; 3.0 V to 5.5 V logic power supply voltage range

#9642 ; Mixed, fast and slow current attenuation mode

#9642; Low power consumption synchronization rectification

#9642; internal OVLO, UVLO and heat shutdown circuit

#9642; Cross current protection

#9642; Diagnosis of power/ground short circuit and short -circuit/low load current

Packaging: 28 -pin TSSOP (suffix LP) with exposed heat pads [123 ]

Explanation

A3980

is a complete micro motor driver and built -in translation to facilitate operation. It is designed to operate a bipolar step motor in the whole level, half -order, eighth, and sixth -order mode, with a voltage of 35V and ± 1A. The A3980 includes a current -fixed -turn off current regulator that can operate in the mode of slow, fast or mixed attenuation. This will reduce the listening noise of the motor, improve the accuracy of steps, and reduce power consumption.

Translation is the key to A3980 easy to achieve. Just enter a pulse at the step input terminal to drive a micro -step. There is no phase sequence table, high -frequency control line or complex programming interface. The A3980 interface is very suitable for applications with complex μP unavailable or overloaded.

Provide internal simultaneous rectifier control circuits to improve power consumption during pulse width modulation operation.

Internal circuit protection includes: lag heat shutdown, overvoltage lock (OVLO), underwriting voltage lock (UVLO) and cross -current protection. No special power -powered order is required. In addition, the two diagnostic fault indications indicate short -circuit or opening of the motor winding.

A3980 uses a light and light (1.1 mm) 28L Tssop with exposed heat pads. This device does not contain lead, 100%matte tin -plated leading framework.

Typical application

Figure Figure Figure

[ 123] Function description Device operation. The A3980 is a complete micro -buffer motor drive with a built -in converter. It is simple and the control line is the least. It hasOperate the bipolar step motor. The current in the two output bridges and all N -channel DMOS field effects in the crystal of the crystal tube is controlled by the fixed turnover time PMW (pulse width modulation) control circuit. In each step, the current of each bridge is set by its external current detection resistor (RS1 or RS2), reference voltage (VREF), and its DAC output voltage (controlled by the output control of the converter).

When power is powered, the converter is reset to the initial state. In this state, the motor is driven to the initial micro -step position, and the two phase current currents are set to+70%. The converter then sets the voltage regulator to a two -phase hybrid attenuation mode. When the order signal appears on the step input, the converter will automatically sort the DAC to the next level and the current polarity. (See Table 3 in the current level sequence) Micro -step resolution is set by the combination effect of input MS1 and MS2, as shown in Table 1.

When stepped, if the new output level of DAC is lower than its previous output level, there is a source of attenuation mode (fast attenuation, slow attenuation or mixed attenuation) of the source bridge. If the new output level of the DAC is higher or equal to its previous level, the attenuation mode of the full bridge is set to slow attenuation. This automatic current attenuation is selected to improve the micro -step performance by reducing the current waveform distortion caused by the electrocomputers.

Original point micro -step position. When power is powered, or the UVLO (under voltage lock) condition caused by the low voltage on the VDD, the converter in the A3980 resets the motor to the initial micro -step position. This corresponds to 45 °, which is a step with+70%of both phase current. Reference Table 3, for the full step mode, this is step 1; for the half step, this is step 2; for the eighth step, this is step 5; for the sixteenth step, this is step 9. In Table 3 and 5 to Figure 8, the initial micro -step position is indicated.

Step input (step). A conversion from low to high on the step input makes the translator arrange in order and makes the motor an incremental increase. The converter controls the input of DAC and the current direction of each winding. The incremental size is determined by the combination of MS1 and MS2.

Micro -step selection (MS1 and MS2). Select the micro -step format, as shown in Table 1. Any changes to these inputs will not take effect before the next increase.

Input (DIR). This determines the rotation direction of the motor. At low, the direction is clockwise, when it is high, the direction is counterclockwise. The change of the input will not take effect before the next increase.

Internal pulse width control current control. Each full bridge is controlled by the PWM current control circuit with a fixed disconnection time, which limits the load current to ITRIP. Initially, a pair of DMOS FETs were enabled, and current flows through the motor winding and current detection resistor RS. When the voltage on the RS is equal to the DAC output voltage, the current detection comparator reset the pulse width modulation locklive. Then, the locks are turned off the source DMOS (in the slow attenuation mode) or the receiver and the source DMOS (in the fast attenuation mode or the mixed attenuation mode).

The cross -guidance function is similar to the maximum value of current limit iTrimax (a), which is:

where RS is the resistance of sensor resistors ( Ω), V REF is the input voltage on the REF pin (V).

DAC output reduces VREF output to the current influenza response in accurate steps, so that:

(see Table 3.)

It is important not to exceed the maximum rated value (0.5 V) on the sensor pin. For the full -level jump mode, VREF can be used to the maximum rated value of VDD, because the peak sensing value is 70%of the maximum value:

as shown in Table 3. In all other modes, VREF should not exceed 4V because the peak can reach VREF / 8 or 100%.

Fixed rest time. The internal pulse width modulation current control circuit uses a disposable circuit to control the duration of the DMOS FET. Through the combination of external resistors (RT) and capacitors (CT), the one -time closure time (TOFF) of each phase of the two phases is determined. One combination is connected from the timing terminal RC1 to ground, and the other is similar to RC2. TOFF (NS) is approximately:

In the range of CT 470 PF to 1500 PF and RT 12 kΩ to 100 kΩ.

Reinforced concrete feeding. In addition to the fixed PWM control circuit shutdown time, the CT component also sets up a comparator to eliminate the time. When the internal current control circuit switch output, this function will make the output of the current influenza comparator blank. The output of the comparator is shielded to prevent fake over -current detection caused by the switch -related switch -related switch -related switch -related switches of the diode. TBLANK (NS) can be approximately similar:

, CT is the value of the capacitor CT (NF).

The blank time should be as short as possible without causing error failure to ensure minimal power consumption under failure conditions. The blank time also defines the minimum duration of the full bridge DMO output that causes the load current to rise. In order to ensure the correct detection of motor failure, the minimum opening time is extended by increasing the fault sampling time TSCT. The shortest time is:

oil supply pump (CP1 and CP2). The oil supply pump is used to generate door power supply greater than VBB to drive the source endDMOS door. A 100 NF ceramic capacitor (CCP) that can withstand the battery voltage VBATT should be connected between CP1 and CP2. In addition, a 100NF ceramic capacitor (CCS) is required between VCP and VBB as an energy storage device for high -pressure DMOS devices. The voltage on the CCS is limited to the charge pump voltage, and the voltage is always less than 10V.

Vreg (vreg). The internal voltage is used to operate the DMOS FET side of the receiver. The Vreg terminal must be cut off with 220 NF (10 V) capacitors. Vreg is monitored by internal monitoring. In the case of failure, the DMOS output of the A3980 was disabled.

Enable the input (enable). This input is just turn off all DMOS output. When setting as high logic, the output is disabled. When the logic is set low, the internal control is enabled to use the output as needed. The converter input (STEP, DIR, MS1, and MS2) and internal sorting logic maintain the activity status, which has nothing to do with the enable input state.

Sleep mode (sleep). In order to minimize the power consumption when the motor is not used, the input will disable many internal circuits, including output DMOS FET, voltage regulator and charge pump. The logic on the terminal of sleep makes the A3980 enter the sleep mode. High logic allows normal operation and start (at this time the A3980 drives the motor to the initial micro -step position). When VBB is larger than VOVB-Vovbh less than VOVB, the A3980 will maintain a security mode until VBB is reduced to lower VOVB-VOVBH.

Quick attenuation input percentage (PFD). When the output current level of the step input signal input instruction is lower than the previous step, it switches the output current at an attenuation to slow, fast or mixed attenuation mode according to the voltage level input by PFD, as shown in the table below.

Mixed decay operation. Depending on the order order, if the voltage on the PFD pin is between 0.6 × VDD and 0.21 × VDD, the whole bridge can work in the mixed attenuation mode, as shown in Figure 5 to Figure 8. When the trigger point is reached, the A3980 enters the fast attenuation mode until the voltage on the RC tube's foot is attenuated to the same level as the voltage applied to the PFD tube foot. The duration of the bridge in the fast attenuation mode TFD (NS) is from:

from the range of the range from CT 470 PF to 1500 PF and RT 12 kΩ to 100 kΩ to 100 kΩ Inside.

After this rapid attenuation cycle, the remaining part of the A3980 in the fixed shutdown time cycle was switched to the slow attenuation mode.

Synchronous rectification. When the pulse width modulation is turned off, the cycle is triggered by the internal fixed shutdown time cycle, and the load current cycles according to the attenuation mode of the control logic. Synchronous rectification characteristics are opened during current attenuationOpen the appropriate FET and effectively make the low -DMOS RDSON body diode short circuit. This has significantly reduced power consumption and eliminates the needs of the external Schottky diode. There are two modes of synchronous rectification: activation mode and disable mode (as described below).

activation mode. When the input on the SR terminal is set to the logic low, the activation mode is enabled. This mode allows synchronous rectification, but when the zero current level is detected, it also turns off the synchronous rectifier to prevent the load current from reversing. This prevents motor winding reverse conductivity.

The disable mode. When the input on the SR terminal is set to the logic, the disable mode takes effect. This mode is disabled to synchronize rectification. When the external diode is required to transmit power consumption from A3980 to the external diode, this mode is usually used.

Close. When VREG has a super temperature or underwriting failure, the DMOS output of the A3980 will be disabled until the failure conditions are eliminated. In the case of over -pressure failure, the receiver DMOS FET is opened, and the source FET is closed. When the VDD is low, if the VDD is low, the UVLO circuit disables the DMOS output until the VDD reaches the lowest level. Once the VDD is higher than the minimum level, the converter will be reset to the initial state, and the DMOS output will be re -enabled.

Hot protection. When the joint temperature reaches the heat turnover value (usually 170 ° C), all the drivers will be closed. This is only used to protect the failure of the A3980 from the failure of the joint temperature. Thermal protection does not protect the A3980 from being unsustainable, so it integrates additional fault diagnosis. The hot stack is about 15 ° C lag.

Diagnostic function. The A3980 includes a TOR circuit that can detect Moni-short-circuit, short-circuit, short-circuit or opening load. When the motor is in the start micro -step position, the short circuit is detected by monitoring the voltage on the DMOS FET, and the opening load is detected by monitoring phase current. All fault detection is performed after a delay after blank time.

Short to VBB. By monitoring the voltage of the FET at the bottom of each full bridge, a short circuit connected from any motor to a battery or VBB connection can be detected. When the effect on the spot is powered on, the voltage should not be greater than the VDSLT value specified in the electrical table.

Short -circuit on the ground. By monitoring the voltage of the top FET in each bridge, any motor can be detected to connect to the ground short circuit. When FET is turned on, the voltage should not be greater than the VDSHT value defined in the electrical table.

Short -circuit load. By monitoring the voltage of the top and bottom FET in each bridge, the load can be detected.

Short fault operation. Because the motor capacitance may cause the measurement voltage to display the fault of the whole bridge switch, the voltage is sampled until the blank time and the delayed TSCT generated inside. Once the short circuit is detected, all the output of the fault phase will be disabled until the next order. Life in the next stepIn the order, the output is re -enabled, and the voltage of the field effect tube is sampled.

When the failure still exists, the A3980 continues this cycle in each step command: enable the output for a short time, and then disable the output. This allows the A3980 to deal with continuous short circuit without damage. If short circuit occurs during fast steps without any measures, the repeated short -circuit current pulse will eventually cause the temperature of the A3980 to rise and ultra -temperature failure.

Low load current fault operation. By monitoring the current phase current at each output, the motor is driven to the start micro -step position, and the low load current can be detected. At the start micro -step position, the current of each phase should reach 70%of ITRIMPMAX. If a phase current does not exceed half of the expected value (more than 35%of the ITRIMPAX) at the initial micro -step position, the lower load current situation of the next rising along the step input in the step input. If the measurement current of the two phases exceeds 35%of the ITRIMPAX, the next rising edge of the order input will not cause failure.

If the loading condition occurs during a single step execution, the loading condition is detected after the translator cycle enters the main state. Although the A3980 continues to drive the DMOS output under opening the load conditions, it will not clear the fault Flags before the next main state appears.

There are two cases that lead to low load current. The first is the opening of one or two motors. In this case, the current can never flow through the phase, so the low load current will always gather together. The second case is that the electromotive force of the motor limits the phase current in the range lower than the low -load current. This will occur when the operation of the step motor is close to its extreme speed. In order to confirm the opening load conditions when the low load current aggregates, the step rate should be reduced to the level of less than half of the step rate. If the low load current FL AG remains activated at a lower step rate, after completing the number of steps required to pass the initial conditions, the opening conditions are confirmed.

In order to be able to detect the open load state immediately after power -on or after the dormant mode came out, the A3980 converter was reset to the initial micro -step position, and a low load current fault FL AGS was set. If there is no open load condition, the fault FL AGS will be reset at the next rising along the step input.

Provide a monitor. Monitor external and internal power to ensure that they are within the correct scope of work. If the main power supply exceeds the overvoltage limit VOVB, the fault FL AGS is set, and the A3980 enters a security mode. In this mode, all low -end DMOS FETs are enabled and all high -end DMOS FETs are disabled. This enables the A3980 to survive under the load reserves of up to 50 V and a duration of 500 ms on VBATT. If the internal regulator VREG or logical power supply VDD is lower than the respective departure restrictions (VVVR or VVVD), then: Set fault FL AGS, disable DMOS output, and internal logic is reset to the boot state (the converter is set to the Home).

Diagnostic fault logo (FF1, FF2). Diagnostic failure control-Use two fault FL AG output (opening) report status. These are active low outputs, as shown in Table 2 to distinguish between faults. When both fault lights are high, there are no faults.

Application information

A3980 is a power supply circuit, so you must carefully consider the effects of power consumption and high current on interconnection and power wiring.

Power consumption. The first -level value of A3980 can be determined by checking the power consumption of the two full bridges in each operation mode. When using synchronous rectification, the current flows most of the time through the opening of the DMOS FET. When the synchronous rectification is used, the current flows through the DMOS FET body diodes during the attenuation phase. Use fast decay or slow decay can also affect dissipation. All the above combinations can be calculated based on the virtual basic DMOS output state, as shown in the figure below.

Drive current slope

The diagonal DMOS output transistor is opened. The current flows from the positive power to ground through the load. Used for all combinations.

Disposal refers to the I2R loss in the DMOS transistor:

Synchronous slow decay

Two low -end DMO output transistors are opened. The current passes through the transistor and load cycle.

Disposal refers to the I2R loss in the DMOS transistor:

Non -synchronous slow decay

A low -edge DMOS output transistor and a Body diode conduction. The current passes through the diode, transistor and load cycle.

The loss is the I2R loss in the DMOS transistor plus the IV losses in the diode:

The fast decay synchronous change change

The DMOS output transistor that is opposite to the diagonal is opened. The current goes to the positive power supply from the ground through the load.

Disposal refers to the I2R loss in the DMOS transistor:

Non -synchronized fast decay

A diagonal body diode conduction with diagonal opposite. The current goes to the positive power supply from the ground through the load.

Losses are IV loss in the diode:

The total loss of four attenuation modes is the average of the current slope The current attenuation of the current and PWM cycle.

For slow attenuation, the current rises by about 20%, and the decrease is about 80%. For fast attenuation, the ratio of each situation is about 50%. Please note that these are approximately pictures, which are slightly different according to the characteristics of motor and synchronous rectification.

PTOT in each attenuation mode can be calculated according to the following formulas.

Synchronous slow attenuation mode:

The allowable packaging power consumption

1. In JEDEC Standard High K " 4 layer of RθJA under 28 ° C.

2. At 38 ° C/W