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2022-09-21 17:24:28
A8450 is a multi -output voltage regulator
Features
*6 V to 45 V input range
*5.7V output DC-DC antihypertensive converter
*Folding and lack of pressure locking Over current protection (UVLO)
*Double 5 V output
- Digital 5 v ± 2%, 200 mia
-In simulate 5 V, 200 mia [123 ]
-The short-circuit protection on the simulation regulator-In simulation-digital regulator output tracking lt; 0.5%, throughout
Work temperature range
*3.3 V linear regulator, with folding current limit
*adjustable 1.2V to 3.3V linear regulator, adjustable folding current limit
*ignition switch enable; sleep mode
[123
]*100%duty -occupying ratio under low input voltage run
*Normal output of the power supply
* - 40 ° C to 135 ° C The temperature range of the environment
] A8450
is a multi -output power supply for car applications. The A8450 works in a wide range of input power sources, designed to meet the requirements of high environmental temperatures.
Four voltage voltage output provides a variety of options. 3.3 V registers and 1.2 to 3.3 V can be used to power the microcontroller or DSP core, or for I/O, sensing and A-D conversion. Two 5V outputs, one number, and another simulation, the output is tracked within 0.5%within the operating temperature range. In addition, analog regulator can prevent short circuits of batteries. All four regulators have folding current limit protection.
You can use two input pins to enable or disable the device. The high -voltage input on the enBat pin allows the use of engine ignition or battery switch signal enable/disable. The logic level on the ENB pin allows microcontroller or DSP signal enable/disable. When disabled, the current of the A8450 is less than 10 Weire. Por (power -on reset) module monitor the power supply voltage and provide a reset signal with adjustable delay to be used for microcontroller or DSP reset.
A separate fault tube foot signal TSD (heat shutdown), 5 V simulation power short circuit and 5 V analog or digital under pressure.
A8450 uses 24 -pin SOIC packaging (part number suffix LB), with a fuse power ground pins to improve thermal performance. This provides 35 ° C/W RθJa on the 4th layer (see chart on page 4).
Use the following complete part numbers when ordering:
function box diagram
Sequence diagram [ 123]
Lolar transformer picture
Vehicle identification number 12 volts; ILOAD 100 mAh; temperature A 25 ° C; communication coupling; C1, C2, C3, and C4 1 micro F.
For adjustable regulator, the transient load response increases with the decrease in voltage. This is because the regulator can provide more base -driven (VADJBD) because there are more available voltages. When the adjuster is close to 3.3V, its transient load response is equivalent to the response of the V33 regulator.
For all regulators, the load transient can be improved by increasing the output capacitor (C1, C2, C3, and C4). To reduce ESR, it is best to use ceramic capacitors. However, the large value in ceramic capacitors is either unavailable or very expensive. If you need a larger value, above 22 μF, the low ESR electrolytic capacitor can use the rated value. Performance can further improve T (50 microseconds/point) by adding 1 μF ceramics by parallel with electrolyte.
Function description
BUCK converter with a switching regulator. A8450 integrates current mode, frequency conversion DC-DC converter and switch regulator, as shown in Figure 2. This function allows the device to effectively process various input power levels. The DC-DC converter outputs a typical voltage of 5.7V, and the over-current limit is 1.2A typical voltage.
The converter adopts soft startup characteristics. By controlling power, the surge current required for external capacitors, COUT and any DC load charging, which will slow down the output voltage of the converter and limit the maximum demand for VREG.
The internal charge pump provides a gate driver for the N -channel MOSFET antihypertensive switch. When using a low VBB input voltage, a 100%duty occupation ratio is achieved.
When VBB is lower than 12V, the TOFF closure time decreases, as shown in Figure 3. This decrease keeps the switch frequency FPWM in a reasonable range and reduces the ripple current. Reducing the ripple current under low VBB levels to prevent the remaining volume of linear regulator caused by VREG ripple voltage.
5 V linear regulator. Provide two power linear regulators in two 5V. These low -voltage stabilizers have a foldable flow limit function for short circuit protection. When the short circuit acts on the voltage voltage output terminal (V5A or V5D), the current is folded back to 0 volts at 50 mA, as shown in Figure 4A. When the short circuit is eliminated, the voltage returns to its adjustment output.
During the power period, the V5A and V5D regulator followed each other. When the device enabled and accelerated from the disable mode, when Vreg reaches about 1.8V, the regulator will start tracking Essence These regulatorsMake sure that they are tracked within 0.5%under normal working conditions.
3.3V and adjustable linear regulator. Two additional linear regulators, one output 3.3V, and the other output is 1.2V to 3.3V. It can be achieved with an external NPN -mounted transistor. The output voltage of the regulator VOUTVAJ (V) is set by the value of the output resistance R1 and R2 (ω). It can be calculated as:
Among them, V FB (V) is the voltage on the feedback foot FB.
additional pins, CL33 and CLADJ provides setting current limit. They are used to protect the short -circuit of the external channel crystals from short circuits on the ground. The current limit setting value ICL (MA) uses the following formula calculations:
Among them 3.3 V regulator, R4 is used for adjustable regulators). When exceeding ICL, as shown in Figure 4b, the maximum load current of the regulator is folded back to 40%of the ICL ± 10%. If there is no need to limit the current, the CL33 and CLADJ pin should be received short to the VREG pin.
The disable mode. When the two input signal pins ENBAT and ENB are pulled down, the A8450 enters the disable mode. This is a sleep mode. In this mode, all internal circuits are disabled in order to draw the smallest current from VBB. When any of these pins is pulled up, the device will be enabled. When the disable mode appears, the buck converter switching regulator does not work before the charge pump stability (about 300 microseconds).
Enable mode. When one or two signal input pins ENBAT and ENB are in high state, the A8450 is enabled.
ENBAT is a edge trigger (Logic 1≥2.7 V), which is used to respond to high -voltage signals (such as from a car ignition switch or battery switch). A8450 is enabled. Under this capacity, ENBAT is only used as an instantaneous switch of the wake -up device. If you do not need a high -pressure signal, you can continue to lower ENBAT.
ENB is used to start the reset of the device. If ENBAT is pulled down, ENB acts as a single reset control.
Diagnosis. The leakage output through the NFAULT pin was pulled down, and the signal of any of the following fault conditions was sent to the DSP or microcontroller:
V5A, 5 V simulation regulator output, short circuit to the power supply to the power supply
V5A and V5D regulator output below the UVLO threshold vuvlov5
Device connection temperature TJ exceeds the thermal warning threshold tjtw
OilPump. The charge pump generates a voltage higher than the VBB in order to provide sufficient gate drivers for the N -channel BUCK switch. A 0.1 μF ceramic single -chip capacitor C7 should be connected between the VCP pin and the VBB pin as an energy reservoir running the switching regulator of the booster converter.
VCP is subject to internal monitoring to ensure that the oil supply pump is disabled when the failure occurs. In addition, a 0.1 μF ceramic single -chip capacitor C8 should be connected between CP1 and CP2.
Putting on reset delay. Por block monitor the power supply voltage and provide a signal that can be used to reset DSP or microcontroller. The POR event is triggered by any condition:
V33 or VADJ is pulled to its UVLO threshold, vuvlov33 or Vuvlovadj. If the current restrictions are limited to any regulator, VOC exceeds. This happens if the current exceeds the IDSLIM and the Vreg voltage drops below Vregmon.
Enb and ENBAT are lower. This will immediately pull the NPOR pin, indicating that the device is starting to break the electrical sequence. In addition, the buck converter switching regulator is disabled, and the Vreg power supply begins to decline. The rate of Vreg attenuation depends on the value of total current consumption, ILOAD and output capacitors (C1, C2, C3, and C4).
Vreg below its ultraviolet threshold.
During any normal power period, VOUTVADJ is lower than vuvlovadj to trigger POR.
Provide an open output through the NPOR pin and send a POR event signal to the DSP or micro -controller. The reset occurs after the adjustable delay TPOR set by the external capacitor C9 connected to the CPOR pin. The value of TPOR (MS) uses the following formula calculations:
In the formula, CCPOR (μF) is the value of the C9 capacitor.
By reducing the pulse of the ENB and ENBAT tube, the POR can be forced to implement the POR without significantly reduced the power supply voltage VREG. However, the pulse duration should be short enough so that Vreg will not decrease significantly.
The heat shutdown. When the device connection temperature TJ is detected, the NFAULT pin indicates the failure of the NFAULT pin. At the same time, the BUCK converter is disabled by the heat shutdown circuit to protect the A8450 from damage.
Component selection
Output sensor (L1). This inductor must be rated as a total load current, ILOAD. In addition, the selected value must keep the line wave current at a reasonable level. The typical option is the power sensor with a rated value of 100 μH and 1.3 A.
The worst case of ripple current Iriple (MAX) (MA) can be calculated as:
[μH), where LL1 (μH) is a selected component. For inductance, VL1OFF is through the voltage of the inductance (V), when the A8450 is in a static state:
Among them, VD1 (V) is the voltage drop on the diode D1, ILOAD (MA) It is the total load current, and the RL1 is the specified DC resistance (ω) of the selected electrical sensor at its rated temperature.
The frequency FPWM (Hz) of the switching regulator in the buck converter can pass:
In type, ton (μs) is calculated as:
and vl1on (v) as:
Example
given typical applications, vbb 14 v v v v v v v v v V v] , TOFF 4.75 microsecond, ILOAD 550 mAh. (Note that for VBB GT; 12V, the value of TOFF is constant, as shown in Figure 3.)also provides a 100μH power inductance, with a rated value of 400 mΩ and a temperature of 125 ° C (note, inductance, inductance sensation The temperature rated value may include the self -heating effect. If the rated value of 125 ° C includes the self -heating temperature at 20 ° C at the maximum current, the actual environmental temperature TA cannot exceed 105 ° C.
In the case of short -circuit output, the BUCK converter can reach its internal current limit IDSLIM, usually 1.2A. To ensure safe operation, the ISAT rated value of the selected electrical sensor should be greater than 1.4 A. However, if it is 3.3 V V V The rated values of the external current limit resistor R3 and R4 selected by the adjustable (1.2 V to 3.3 V) regulator regulator make the total electric sensor current ILOAD can never reach the internal current limit, then the electrical sensor can choose the ISAT rated value to the device close to the device Calculate the output current ILOAD, plus the maximum ripple current Iriple (MAX).
You can choose a higher inductance value to reduce the iris. If you want to increase the total currently maximum current from the switching regulator, you can choose this to choose this Method. The maximum total current ILOAD (MA) calculated as:
Capture the diode (D1). The rated value of Shawitki captured the diode should be the maximum load current ILOAD ILOAD ILOAD 1.2 times, because the duty cycle under the low input voltage VBB can be very close to 100%. The rated voltage should be higher than the maximum input voltage VBB (MAX) expected under any operating conditions.
VREG output capacitor (COUT ). Select VREGWhen the output capacitor is COUT, the voltage ripples in VREG output are mainly considered. The calculation of VRIPLE (P-P) (MV) calculation as follows:
ESR unit is Om. The maximum level of VRIPPLE (P-P) is less than 200 MV.
For electrolytic output capacitors, it is recommended to use a low ESR type with a minimum rated voltage of 10 V. However, due to the decrease in the voltage of ESR, the most economical and effective choice may be capacitors with higher rated voltage.
The regulator output capacitor (C3 and C4). The output capacitors used with 3.3 V registers (C3) and 1.2 V to 3.3 V can be used (C4) should be 1 μF or larger X7R (5%tolerance) Ceramic or equivalent capacitors, within the temperature range of -55 ° C to 125 ° C, the maximum capacitor changes is ± 15%.
The ESR of these capacitors does not affect the output of the corresponding regulator. If a larger capacitor is used, the regulator improves ripple suppression at the frequency greater than 100 kHz.
Through the transistor (Q1 and Q2). The power transistors used to realize 3.3 V registers and 1.2 V to 3.3 V can be adjusted. The transistor must ensure:
stable operation. The deadline of the regulator control circuit is 100 kHz. You must choose a crystal tube with a width bandwidth FT (KHz) and Beta, HFE (A) rated value:
enough base driver. For lower total load current, you can use lower current gain HFE, ILOAD. The lower limit of ILOAD is limited by the minimum base current, IBD (minimum) of the A8450, and the minimum HFE limit through the transistor, so that:
Note that HFE depends on the working temperature. The lower temperature will reduce the HFE and affect the current capacity of the transistor.
enough power consumption. In order to ensure proper thermal treatment, the design of the application must consider the power consumption characteristics of the PCB of the PCB of the A8450 and PASS transistors. Generally speaking, power loss PD (MW) Reverse:
For vreg 5.8 v, vout typical applications 2.5 volts, ILOAD 190 mAh
[
[ 123]Adjusting the power consumption of the transistor
There are various packaging types of the transistor, and the heat dissipation efficiency of the packaging is also very different. Generally speaking, increasing thermal efficiency will also greatly increase costs. Choosing a bag that is closely matched with the operating conditions is very good for optimizing application design and costimportant.
Even with the use of heat enhancement packaging, it is difficult to provide high current to the load at high environmental work temperature. According to the load requirements, as shown in FIG. 5, the resistance may be used to protect the pipeline that cannot be hot.
The output current limit resistance RCL (corresponding to R3 and R4) will decrease between 175 MV and 225 MV when the highest current outputs ILOAD. Assuming that there is no additional resistor, the voltage drops each time, VDROP (MV).
The crystal tube is:
This can be substituted into the power consumption formula:
[ 123]
A typical application is given, where Vreg 5.8V, VRCL 0.175 V, vout 3.3 V, ILOAD 350 mAh, then the PD is about 814 MW.
Local discharge can be used to estimate the minimum working temperature rated value required for transistors. The capacity of packaging heat dissipation is similar to the heat resistance Rθ (℃/w) from the mold (connection point) to the surrounding environment. This includes the significant effect of the loss of PCB through the packaging lead and the installation of the transistor, as well as the state of environmental air. The typical rated of DPAK package is 32 ℉ C/W. Given PD 0.814 W, the expected self -feeling temperature rise in the packaging ∏TJ (℃) is similar:
In the car application, if the ambient temperature under the engine cover It can exceed 125 ° C, and the passage must be raised to provide the required BETA value at a temperature greater than or equal to 151 ° C.
For the selected transistor, VCE can change according to the current, temperature and transistor β. Under normal circumstances, the rated value of the transistor is minimum β under the specified VCE. However, the calculation of VCE should leave a certain amount of rain, so there is always enough space to drive the device under the required load.
In order to provide work margin, or if a lower RCL value is required, the voltage -lowering resistor RDROP can be added to the circuit between the RCL and the transistor (Figure 5). It is also important to consider the tolerance in the resistance and Vreg. The Vreg (min) voltage is 5.6V, which reduces the local discharge level, and at the same time reduces the available voltage of VCE. Calculating the maximum and minimum voltage drop can help determine the value of the voltage drop resistance.
The required resistance value RRDROP can be determined according to the voltage of the components of the circuit, as shown in the following formula:
Where
Assuming Vreg (MAX) 5.8 V, VOUT (MAX) 3.3 V. Also assume that TA 125 ° C, VCE 1V (according to MPSW06 NPN transistor regulations, beta 300 at 125 ° C).
In order to determine the resistance value of the current limit resistance and resistance resistance, VRCL and VDROP can be represented by ion 350 mA. However, under normal working conditions, the current restrictions set by RCL will be higher than the normal current, so assuming ILOAD (LIM) 0.400 A and RCL 44Ω.代替测定VRCL:
我们现在可以解决RRDROP和VDROP
因此,
[ 123]
and
Use four 0.25 W resistance (value 14.7Ω) parallel will reduce 1.3 volts.
使用如上所计算的降阻,晶体管中的功耗PD(W)降低到:
和
[123 ]
The power consumption in the transistor was significantly reduced. The transistor in the power packaging is 32 degrees Celsius/watt at 400 mAh (50 mAh). When there is a resistance, the temperature rises by 13 degrees Celsius. When 350 mAh, similar transistors tube tube tube was Without resistance, the temperature rose 26 degrees Celsius. Under high output current, proper selection of resistors can prevent external channel transistors from overheating.
A8450 power consumption. A8450 design for the application of high environmental temperature. The total power consumed in the device must be considered with the heat dissipation capacity of the PCB installed A8450 and the ability of the equipment package itself.
The capacity of packaging heat dissipation is similar to the heat resistance Rθ (℃/w) from the mold (connection) to the surrounding environment. This includes the significant effect of the loss of PCB installed on it by packaging wires and packaging, as well as the temperature of the environmental air. When installed on the high -conducting printing circuit board (based on the Jedec standard printing circuit board and has four layers of buried copper areas), the test results of the 24 -drawing SOIC SOIC are about 35 ° C/W.The total power PD (LIM) (W) that can be applied to the device can be applied to the maximum allowed temperature TJ (MAX) (degree Celsius), Rθ, and environmental air temperature to Show:
PD (lim) can be estimated according to several parameters, using the following formulas:
Among them [ 123]
and ILOAD ILOAD (V33)+ILOAD (VADJ)+ILOAD (V5D)+ILOAD (V5A) RDSON is a function of TJ. In order to estimate local discharge (LIM), it is assumed that the relationship is linear within the actual TJ working range (see the RDSON test conditions in the electrical characteristic table).
DC (occupy ratio) is a function of VBB and Vreg. This can be accurately calculated as:
The rough estimate of the DC is:
IV33BD (MAX) is V33BD The maximum current on the pin. It depends on the IOUTV33 and HFE of the transistor.
IADJBD (MAX) is the maximum current on the Vadjbd pin. It depends on the IOUTVADJ and HFE of the transistor.Over -current protection
3.3 V and 1.2 to 3.3 V can be adjusted by the regulator. The current provided by the regulator is limited to ICL. As shown in Figure 4B, the current above ICL is linearly folded. In the case of short -circuit load, the setting electrode current is reduced to 40%of the ICL ± 10%to ensure the protection of the transistor. After the short circuit is eliminated, the voltage is restored to the prescribed level.
The maximum power consumed in the crystal tube under short -circuit load conditions is:
Among the vout 0 V.
Low input voltage operation
When the charge pump has been tilted to enough to enhance the buck switch, the buck converter switching regulator is enabled. This occurs during VBB≈5.7V. At this time, the A8450's duty ratio DC can be forced to 100%until the vehicle identification number is high enough to allow the switch to start working normally. The point that starts at the beginning of the normal switch depends on the ambient temperature TA. The increase in TA caused RDSON to increase. Other important factors are ILOAD, Vreg, ESR (L1) with output inductors, and the positive bias (D1) of the output of the Schottky diode.
regulator bypassSome applications may not need to use all four regulators provided in A8450. There is no corresponding external component for unused regulators.
If the application does not require one or two of the two 5V regulators, it will not connect its output terminal V5D or V5A, bypass the unused regulator. At the same time, the corresponding output capacitor C1 or C2 is not used.
For 3.3 V register and 1.2 V to 3.3 V, if you do not need a regulator, the corresponding external components are not used. In addition, if the 3.3V regulator is not used, the CL33 and V33 are not connected. If you do not use the adjustable regulator, Cladj and FB are not connected. However, in order to ensure the stability of the A8450, anyThe basic driver of the unused regulator V33BD or VADJBD must be short -circuited for Vreg.
Wire 6, 7, 18, and 19 are the internal fuse connecting the wire to enhance heat dissipation.The accurate appearance depends on the judgment of the supplier.
The products described here are made based on one or more US patents or are applying for US patents.
Allegro Microsystems, Inc. Reserve the right to formulate product performance, reliability or manufacturing to improve the terms required at any time according to the detailed specifications.Before the order is placed, remind users to confirm that the information it depends is the latest.