Features

High bandwidth: 500 mHz (g u003d+2 v/v)

High conversion rate: 2675 V/μs (4 V steps (4 V steps Entry)

Over 71 dbc

low input voltage noise: 6.1 nv/√Hz

#8226; Fast speeding recovery: 8 ns

Quick stability time (1%4-v stepping): 7.9 ns

low input offset voltage: ± 1 mv

Low input bias current: ± 10 pa

High input impedance: 1012 | | 2.5 PF

Internal gain setting resistance: g u003d+2 v/v or g u003d —1 v/v

High -output current: 70 mia

Application

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Test and measure the front end

High input impedance probe

Enter

ADC input amplifier product

Instructions

OPA653 combined with a very wide frequency band voltage feedback amplifier and JFET input level and internal gain setting resistance to achieve realization A high dynamic range amplifier is used for fixed gain applications of+2V/V or -1V/V.

The 500 MHz width increase of the+2-v/V bandwidth is supplemented by a very high 2675-V/μS conversion rate and a fast stability time, making it an ideal choice for time domain and pulse-oriented application.

Excellent –72 DBC THD distortion performance, at 10 MHz, make OPA653 the best choice for frequency domain and FFT analysis applications.

In addition, the low 6.1-nV/√Hz voltage noise, low bias current and high impedance JFET input support very low noise, broadband, and high input impedance applications. For example, high impedance probes, data collection cards and oscilloscope front end.

Typical features: vs u003d ± 6 v

g u003d+2 v/v, RL u003d 100 , TA u003d+25 ° C At time, unless there is another explanation.

Application information Broadband, non -conversion and inverter operation

OPA653 is a very broad -frequency band voltage feedback amplifier, its internal gain Set the fixed gain and high impedance JFET input level of+2V/V or -1V/V. Its high bandwidth of 500 MMS can be used to transmit high signal bandwidth with a gain of +2 V/V, or if it is driven from a low resistance source, the -1 V/V gain can be provided. The design of OPA653 provides very low noise and accurate pulse response, and low -adjustment. In order to achieve the comprehensive performance of OPA653, we need to pay close attention to the layout and component selection of the printing circuit board (PCB), as described in the rest of the data table.

FIG. 21 shows the non-ease gain of+2-V/V circuits as a typical characteristic foundation. Most curves are characterized by signal sources with 50Ω -driven impedance and measuring devices displaying 50Ω load impedance. In FIG. 21, the 49.9- #8486 of VIN+Input Office is used to match the source impedance of the test generator and cable, while the 49.9- series output resistor VOUT provides matching impedance to the measurement equipment load and cables to match the resistance impedance. Essence Unless there is another instructions, the voltage specification of the data table is at the non -switching input pin vin+or the output pin VOUT.

FIG. 22 The non-conversion gain of OPA653 in the 50Ω test environment is -1 V/V configuration for testing typical features. The circuit operation is basically the same as Figure 21, but the terminal connection resistor using a 72.3- between VIN input and grounding, so with the gain setting the resistor (RG u003d 160 ), the input impedance is about about about It is 50 . As a preventive measure, the VIN+input terminal is connected to the ground, and the resistor is used to avoid the input end of the single crystal pipe oscillation by 49.9- Read.

Please note, the 72.3- the input terminal connection resistor and 50- the source impedance modified the noise gain to +1.84 V/ V, the best performance compensation for the amplifier with the noise gain of +2 V/V. This compensation reduces phase margin and causes higher peak values u200bu200band more over -ring/bells in the pulse response. Through the inverter and non -inverted frequency and pulse response diagrams in comparative data, this impact can be seen. The amplifier phase margin can be recovered in applications using inverter configuration.

Operation suggestion

Set the resistance value to minimize noise

OPA653 provides low input noise voltage diagram 23 shows the noise analysis model containing all noise entries. In this model, all noise items are considered noise voltage or current density items represented by NV/√Hz or PA/√Hz.

The total output point noise voltage can be calculated as a square root contributed by the output noise voltage. This calculation stacks all the noise power of the output end, and then takes the square root to the point noise voltage. Formula 1 shows the general form of the output noise voltage, as shown in Figure 23.

Divide this expression with noise gain u003d 1+rf/rg, and get the equivalent input reference point noise voltage when obtaining the input without a deductive input, such as equivalent 2 (equivalent 2 houses 2 Show:

Adding a high resistance value to Formula 2 can quickly control the total effects input noise. Since the gain setting resistance RF and RG are inside the device, the user cannot change the noise contribution, and the noise gain is equal to+2V/V.

However, pay attention to the impact input of RT or other source impedance on irreversitivity. High-non-conversion input resistance resistance value will increase significant noise; for example, 2.4 k will add a Johnson voltage noise item (6.2 nv/√Hz) that is equal to the amplifier itself. Therefore, although the JFET input of OPA653 is very suitable for high -source impedance applications in Figure 21, the overall bandwidth and noise are limited by high -source impedance.

Driving capacitance load

For the operator, one of the most common and most common load conditions is that the capacitance is loading OPA653 is very strong, but you should be careful when you are light negative load. In this way, the output capacitance will not lead to a decrease in stability, the peak response peak, overwhelming, and ringtone. When to consider the output resistance of the amplifier, the capacitor load adds a pole to the signal pathway, reducing the phase margin. For standard operational amplifiers, there are several external solutions that can solve this problem. Because OPA653 has internal gain setting resistance, the only choice is to use series output resistance. This option is a good solution, because when the frequency response is flat, the pulse response and/or distortion are considered when considering the frequency response, the pulse response and/or distortion, the series output resistance is the simplest and most effective technology. The idea is to insert a series isolation resistance RISO between the amplifier output and the capacitance load, and isolate the capacitance load from the feedback circuit, as shown in Figure 24 below. In fact, this structure isolates the phase shift from the loop gain of the amplifier, thereby restoring phase margin and improving stability.

Typical features show the recommended RISO and capacitance load performance (see Figure 17) and the frequency generated under 1-k response. Please note that the lower capacitance load requires a larger RISO value. In this case, the design goals of the maximum flat frequency response are used. If you can tolerate some peaks, you can use a lower RISO value. Long PCB cables, non -matching cables, and connections to multiple devices can easily reduce the performance of OPA653. Always consider this impact carefully, and use the OPA653 output pins to add recommended series resistors (see the circuit board layout part). For a typical 10Ω load, under the low -resistance load (for example, the 10Ω load) can be represented by a low -resistance load.

distortion performance

OPA653 can transmit low distortion under high frequency. The distortion of the typical features shows typical distortion in various cases. Generally, the use of higher power voltage (recommended to use ± 6V), lower output voltage fluctuations, and lower loads can obtain the best distortion performance.

In the unwanted configuration, the total load includes the feedback network, which is the sum of the value of the feedback network, the sum of the value of RF+RG u003d 320 (See Figure 22).

Power decoupling is crucial to harmonic distortion. In particular, in order to obtain the best secondary harmonic performance, the high-frequency 0.1-μF power supply container should be as close to the positive and negative poles of the power supply as much as possible, and it should be placed on a single point away from the input pins on the ground. Essence

pulse and transient response

In order to obtain the best pulse and transient response, OPA653 should be used in the noise gain configuration of +2 V/V. -μF power supply container should be as close to the power of the power as possible.

Note: Noise gain +2 V/V is achieved by connected VIN-and 0- points. In the non -reversible gain application of +2 V/V, VIN -should be grounded; in the reverse gain application of -1 V/V, VIN -should come from nearly 0Ω power, such as the operation amplifier.

Circuit plate layout

To obtain the best performance and high -frequency amplifier, such as OPA653 needs to pay close attention to PCB layout parasites and external component types. Suggestions that can optimize equipment performance include the following.

A) Solle all the signal input/output (I/O) pins of the parasitic capacitor. Parasitic capacitors on the output and reverse input terminals will cause instability: at the non -switching input terminal, it will react with the source impedance, resulting in unintentional frequency band limits. In order to reduce unnecessary capacitors, a window should be opened on all the ground and power plane around the signal I/O pins. Otherwise, the ground and power aircraft should remain complete elsewhere.

B) Short the distance (less than 0.25 inches or 6.35 mm) from power pins to high frequency 0.1-μF decoupled capacitor. At the device pin, the ground layout of the grounding and power supply should not be close to the signal input/output pin. Use a single-point grounding away from the input pins and use it for a high-frequency and negative power supply high-frequency 0.1-μF decoupling capacitors. Avoid narrow power and ground traces to minimize the inductance between the pin and the decoupling capacitor. The power connection should always be disconnected with these capacitors. The large (2.2-μF to 10-μF) decoupling capacitors should also be used on the power pins, which are valid at a lower frequency. These larger capacitors can be placed in a slightly far away from the device and can be shared between multiple devices in the same area of u200bu200bPCB.

C) Carefully select and place external components to maintain the high -frequency performance of OPA653. The resistor should be a very low type of electric resistance. Surface stickers are the best work and allow more compact overall layout. Metal membrane and carbon composition, axial binding resistance can also provide good high -frequency performances. Once again, the length of the lead and PCB tracking length is as short as possible. Do not use a wire winding resistor in high -frequency applications. The inverter input foot is most sensitive to the parasitic capacitor; therefore, the feedback resistance is always placed at the position of the negative input as close to the negative input. The output is also very sensitive to the parasitic capacitor; therefore, the series output resistance (Riso in this example) should be as close to the output pin as much as possible.

Other network components, if the non -converting input terminal connection resistor, should also be placed near the package. Even if the parasitic capacitor is very low, the high resistance value will generate significant time constant, thereby reducing the performance of the device. A good axial metal membrane or surface -sticker is about 0.2 PF when connecting with the resistor in parallel. For the resistance value greater than 1.5 k , the parasitic capacitor will add one pole and/or zero to less than 500 MHz, which will affect the operation of the circuit. Keep the resistance value at the lowest possible. The value of less than 500 value will automatically maintain low -resistance sound items, and minimize the impact of parasitic capacitors.

D) The connection between other broadband devices on the board can be performed through a short direct record or through the plate transmission line. For short connections, the input of tracking and to the next device is considered as a concentrated capacitor load. Relatively wider traces should be used (50 dense ear to 100 dense ear, or 1.27 cm to 2.54 cm). It is estimated that the total capacitance load is estimated, and RISO is set according to the recommended RISO and the capacitance load (Figure 17). Low parasitic capacitance load (less than 5 PF) may not require RISO, because OPA653 is named for name, and can work under the 2-PF parasitic load.

As the signal gain increases (increasing empty -load phase margin), a higher parasitic capacitor load without RISO is allowed. If a long record is required, and the inherent 6-DB signal loss inherent in the dual-end transmission line is acceptable, the micro-band line or strip line technology is used to achieve the matching impedance transmission line (see the relevant micro-band and the strap-shaped wire line ECL design manual of layout technologyTo. A 50Ω environment usually does not need to be on the ship. In fact, the higher impedance environment improves distortion, such as distortion and load curve shown. According to the characteristic circuit board tracking impedance defined by the circuit board material and trace line size, the matching string resistor from OPA653 to the tracking of the tracking and the end -connected resistor equipment of the destination input end. Remember the parallel combination of the terminal impedance is the parallel resistor and the destination equipment input impedance: the total effective impedance should be set to match the tracking impedance. If the attenuation of the transmission line is unacceptable, the transmission line can only be terminated at the 6th end of the long record. In this case, the tracking is considered as a capacitance load and a series resistance value is set, as shown in the relationship diagram of the Riso and the capacitance load (Figure 17). This configuration cannot maintain signal integrity and dual -end lines. If the input impedance of the destination device is low, due to the pressure of the sterilizer formed by the series output to enter the terminal impedance, there will be some signal attenuation.

E) It is not recommended to sockets such as OPA653. The additional lead length and capacitance between the sockets will produce a very troublesome parasitic network, which is almost impossible to achieve smooth and stable frequency response. Welded OPA653 directly to the circuit board to get the best results.

Input and ESD protection

OPA653 is built on a very high -speed complementary bipolar process. For these very small geometric devices, the internal cutting voltage is relatively low. These segments are reflected in the absolute maximum rating table. As shown in Figure 25, all device pins are protected by the internal ESD to protect the power supply.

These diode provides moderate protection to enter an over -drive voltage higher than the power supply. Protecting diode can usually support 30 mAh continuous current. If there may be a higher current (for example, drive to OPA653 with a system with ± 12-V power components), you should add a string-limited connected resistor to two input terminals. Keep these resistance as low as possible because high value will reduce noise performance and frequency response.

Evaluation module

Principle diagram and PCB layout

Figure 26 is OPA653EVM schematic diagram. The first to the fourth layer of the PCB is shown in Figure 27. It is recommended to follow the layout, ground layer structure and power wiring of external components near the amplifier.