Description

WM8782 is a high -performance, low -cost stereo sound for ADC designed by recording media applications.

The device provides a stereo -sound line level input and two control input pipes (format, IWL), allowing audio interfaces of three industry standard modes. An internal operational amplifier integrates an analog input signal greater than 1VRMS at the front end of the chip.

This device also has a high -pass filter to remove DC offset from the residual objects.

WM8782 provides the main mode or the model clock solution.

Control the input pin m/s used to allow operations from mode or main mode. According to the sampling rate, the three-dimensional Sigma-Delta ADC is used for 128X, 64X or 32X over-sampling. Digital audio output 16-24-bit word length and sampling rate support 8kHz to 192kHz.

The device is a hardware control device in a 20-SSOP package.

Features

signal-to-noise ratio 102db ( #39; a #39; weighted@48kHz)

THD-90 decibel (AT AT -1 DBS)

Sample frequency: 8–192kHz

Main and Through Clock mode

MCLK: 128FS, 192FS, 256FS, 384FS, 512FS, 768 feet

audio data interface mode

-16-24-bit left-to-24 bits, 16-24-bit Alignment of right

Power supply voltage

-In simulation 2.7 to 5.5V

-D number core: 2.7V to 3.6V

#8226 20 needle ssop packaging

Application

can record DVD player

Personal video recorder

set -top box

recording room audio processing equipment

block diagram

Device description

Introduction

WM8782 is a 24 -bit stereo ADC, designed for recording applications such as DVD and other high -required recording applications, designing recorders, recording studios, PVR and AV amplifiers. WM8782 consists of a stereo line level input, and then Sigma-DelTA modulator and digital filter.

The device provides stereo lines input and two control input pins (format, IWL) to allow the audio interface S of.

The front end of the chip integrates an internal operational amplifier to adapt to the simulation input signal greater than 1VRMS. The device also has a high -pass filter to remove the residual DC offset.

WM8782 provides the main mode or the model clock solution. Control the input pin M/S to allow operations from mode or main mode. WM8782 supports long audio output words from 128FS to 768FS and 16-24 digital audio. The sampling rate from 8KHz to 192kHz is supported, according to the sampling rate.

The line input is biased into VMID by the internal bias of the amplifier.

Model converter WM8782 uses multiple bits to sample SIGMA-DELTA ADC. The single channel of ADC is shown in the figure. Many excessive sampling SIGMA-DELTA ADC schematic diagram

A number of over-sampling SIGMA-DELTA ADC principles graphsbibi feedback and higher than higher than higher than higher than higher than higher The use of sampling rates reduces jitter and high frequency noise.

When AVDD 5.0 volts, the ADC full label input was 1.0V RMS. Any voltage greater than the full margin may cause ADC to load and cause distortion. Pay attention to the full margin input with a linear relationship and AVDD. Internal op amp and appropriate resistance can be used to reduce signals more than 1VRMS before reaching ADC.

The ADC filter performs a real 24 -bit signal processing to convert the correct sampling frequency output from ADC to digital audio interfaces from ADC to digital audio interface.

Modern Digital Filter ADC Digital Filter contains digital high -pass filters. The high -pass filter responds to the characteristics of the digital filter. The work of the Qualcomm filter has eliminated the audio signal.

Audio data format

In the left alignment mode, the first rising along the BCLK after LRCLK can use MSB transition. Then send other places before LSB in order. According to the word length, BCLK frequency and sampling rate, there may be an unused BCLK cycle before each LRCLK conversion.

Figure left alignment audio interface (assuming N -bit character length) In the right alignment mode, LSB transitions can be used on the last rising edge of the BCLK before LRCLK. All other positions are transmitted before (MSB first). According to the word length, BCLK frequency and sampling rate, there may be an unused BCLK cycle after each LRCLK conversion.

Fign -bit characters)

S mode, MSB's second rising edge of the BCLK after LRCLK conversion is available. Then send other places before LSB in order. According to the word length, BCLK frequency and sampling rate, a sampling LSB and the next MSB.

Figure s Positive audio interface (assuming N -bit words)

Main clock and audio sampling rate

In typical numbers In the audio system, only one central clock source generates all the audio data processing of reference clocks. This clock is usually called the main clock (MCLK) of the audio system. The external main system clock can be directly applied to input pins through MCLK. In a system with many possible reference bells, it is recommended to use the minimum clock source to optimize ADC.

The main clock is used to operate digital filter and noise plastic surgery circuit. WM8782 supports 128FS, 192FS, 256FS, 384FS, 512FS, and 768FS main clock, of which FS is the audio sampling frequency (LRCLK). In the subordinate mode, WM8782 automatically detect audio sample speed. In the main mode, LRCLK is generated for the speed 256fs, unless the user changes it to 128FS to use FSAMPEN PIN Z (see Table 7 below). BCLK is also generated in the main mode.

For 256fs, bclk mclk/4; for 128fs, bclk mclk/2.

The table shows the common MCLK frequency of different sampling rate

The main clock frequency selection

In the pattern, WM8782 has one one The main detection circuit will automatically determine the relationship between the main clock frequency and sampling rate (in the +/- 32 clock). If there is an error over 32 clocks, the interface will set itself to the maximum speed (768 feet) available. Each LRCLK must have a fixed amount of MCLK, although WM8782 allows the phase change or jitter on these clocks.

WM8782 can work at the sampling rate of 8KHz to 192kHz. WM8782 uses Sigma Delta to work at a fixed frequency of 6.144MHz (48kHz at 128 X LRCLK sampling rate). For the correct operation and optimal performance of the device, users must set the appropriate ADC modulator sampling rate to enable. Settling FSAMPEN to 1 for 96kHz users in the main mode and model, for 192kHz users to set FSAMPEN to Z's main mode 192kHz, and require FSAMPEN to set to Z.

Powering and reset

WM8782 has an internal power reset circuit. Power or turn on power. Before the internal reset was removed, DOUT was forced to zero.

10 -power -on reset map

Powering and resetting time

Application information [123 ]

Recommended external component

External component diagram

The recommended external component value

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[ 123] Packaging size

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