Features

AD5337

8-guided 8-bit DAC

AD5338 , AD5338- 1

8 -guide 2 buffer 10 -bit DAC

AD5339

8 -guide 2 buffer 12 -bit DAC [123 123

]

-The low-power operation: 3 V 250 mAh, 5 v o'clock 300 mAh

-2 line (I2C compatible) serial interface

-2.5 V v To 5.5 V power supply

-The design of all code is monotonized

-The reduced to 80 mAh at 3 V, at 5 V to 200 mAh

-3 Electricity Mode

-Dual-cushioning input logic

-Outage range: 0 V to vREF

-Cap power to 0 V

-In the same update output (LDAC function)

-Software clearing facilities

-C data return device

-The on-site rail transition buffer large device

- The temperature range -40 ° C to+105 ° C

Application

Portable battery power supply instruments; digital gain and offset adjustment; programmable voltage current source; programmable attenuation; industrial process control Essence

General description

AD5337/AD5338/AD5339 is the double 8 -bit, 10 -bit, and 12 -bit buffer voltage output DAC in the 8 -line MSOP package. The working voltage is from a single 2.5 to 5.5 volts. Consumer 250 Wei'an during 3 volts. The output amplifier on the film allows rail -to -orbit output to swing, and the rotation rate is 0.7 volts/Weire. 2 -line serial interface operating clock frequency is as high as 400 kg. This interface is compatible with SMBUS when VDD LT; 3.6 V. Multiple devices can be placed on the same bus.

The reference of the two DACs originated from a reference tube foot. You can use the software LDAC function to update the output of all DACs at the same time. These components include a power -on reset circuit to ensure that the DAC output is up to 0V power, and keep there until it is effectively written on the device. The software clearance function can reset all input and DAC registers to 0 V. The power -off function can reduce the current consumption of the device to 200 NA@5 V (80 NA@3 V).

The low power consumption of these components at normal operation makes them very suitable for portable battery drivers. At 5 V, the power consumption is usually 1.5MW, 0.75 mW at 3 V, decreased as low as 1 micro -W.

Figure Figure

Absolute maximum rated value

t 25 ° C, unless otherwise explained.

The stress higher than the absolute maximum rated value may cause permanent damage to the device. This is just a stress rated value. The function of the device in these or any other conditions does not mean that the conditions shown in the operating chapters of this specification do not mean. Long -term exposure to absolute maximum rated conditions may affect the reliability of the device.

The transient current with a height of 100 mAh will not cause the crystal tube to be locked.

Term

Relative accuracy (non -linearity, INL)

For DAC, relative accuracy or integral non -linearity (INL) is a straight line that transmits the end point of the function through DAC Maximum measurement (LSBS). The typical INL and code charts are shown in Figure 6, Figure 7, and Figure 8.

Differential non -linear (DNL)

The difference between the measurement changes between any two adjacent codes and the ideal 1LSB change. The maximum specified value is ± 1 LSB, and the differential non -linearity ensures monotonicity. The design guarantees the monotonicity of the DAC. The typical DNL and code charts are shown in Figure 9, Figure 10, and Figure 11.

An error of offset

A measuring error of the offset error of DAC and output amplifier, which is represented by a percentage of a full marked range.

gain error

Measurement of DAC range error. It is a slope deviation between the actual DAC transmission characteristics and the ideal value, indicating the percentage of the full marking range.

Disposal error drift

A method of measuring offset error with temperature changes. Represented by (full range of PPM)/℃.

gain error drift

A method of measuring gain error with temperature changes with temperature. Represented by (full range of PPM)/℃.

Power suppression ratio

This means how the output of DAC is affected by the change of power voltage. PSRR is the ratio of V changes to V changes to V of DAC's full marking. The unit is decibel. V is kept at 2 V, V changes ± 10%. Examination of due diligence referees due to due diligence

DC disturbance

A DC changes in the output level at a medium -scale DAC to respond to the change of full scale code (full 0 to all 1, vice versa) And the output change of another DAC. Expressed by slightly.

Reference feed

When the DAC output is not updated, the signal amplitude amplitude of the DAC output place to the ratio of the reference input.

Use decibels.

The main code conversion fault energy

Injects the pulse energy of analog output when the code changes in the code in the DAC register. It is usually specified as a faulty area in NV-S, and in the main advancement conversion (011.11 to 100.00 or 100, 00 to 011).

Digital feedback

When the DAC output is not updated, the pulse measurement of the DAC simulation output from the digital input pins of the device. Specify in NV-S, and measure the worst case on the number of input pins, such as changing from all 0 to all 1, or vice versa.

Digital string disturbance

Full standard code changes in the input register in response to another digital modulus converter (full 0 to full 1, vice versa), transmitted to the time of winning to the standard. Failure pulse output by a digital converter. Represented by NV-S.

DAC to DAC string disturbance

Due to the changes in the digital code of a digital converter and the output change of another digital modulus, Essence This includes numbers and simulation string disturbances. It is measured by loading a DAC with a standard code to set the LDAC bit to low and monitor the output of another DAC (all 0s are changed to all 1s, and vice versa). Failure energy is represented by NV-S.

Double bandwidth

The amplifier in DAC has limited bandwidth. The frequency bandwidth is the frequency of the output amplitude below the input of 3DB. In the output, a sine wave (load the full marking code to DAC) will appear in the output.

The difference between the total harmonic distortion (THD)

The difference between the ideal sine wave and the attenuation of the sine waves using DAC. The sine waves are used as a reference of DAC. THD is a real metric in the harmony in DAC output. The unit is decibel.

Typical performance features

]

Functional description

AD5337/AD5338/AD5339 is a dual -resistance string DAC made in CMOS technology, with the resolution of 8, 10 and 12, respectively. Each contains two output buffer placing versions, and is written through the two -line serial interface. DAC's single power supply from 2.5V to 5.5V, the output buffer placing velocity provides rail -to -orbit output amplitude at a conversion rate of 0.7V/microsecond. Two DACs share a reference input pin. Each DAC has three programmable power -off modes, allowing the output amplifier to configure to 1 kΩ load to ground, 100 kΩ load -to -ground or high impedance tri -state output.

digital modulus converterPart

The structure of a DAC channel is composed of a resistance string DAC and an output buffer. The voltage of the REFIN pin provides reference voltage for DAC.

FIG. 29 shows the box diagram of the DAC architecture. Because the input encoding of the DAC is direct binary, the ideal output voltage consists of:

where: D is the decimal equivalent of the binary code, loaded to the DAC register; AD5337 is 0 to 0 to 0 –255 (8-bit); 0-1023 (10 bits) of AD5338 and AD5338-1; 0-14095 (12 bits) of AD5339.

N is the resolution of DAC:

The resistance strings are shown in Figure 30. It is just a resistor, each resistance value is R. Digital code loaded to the DAC register determine the node of the voltage of the voltage and feed into the output amplifier. By turning off a switch to connect to the amplifier to cut the voltage. Because DAC consists of a set of resistors, it is monotonous.

DAC reference input

Two DACs have a reference input pin. The reference input is no buffer. Users can have a reference voltage as low as 0.25 volts and up to five, because there is no restriction, because any reference amplifier's net empty and foot space.

It is recommended to use buffer reference in external circuits, such as Ref192. The input impedance is usually 45 kΩ.

Output amplifier

The output buffer amplifier can generate rail voltage at the output end. When the reference voltage is V, its output range is 0 V to V. The amplifier can drive a load from 2 kΩ to GND or V, which is parallel with 500 PF to GND or V. The source and exchange capacity of the output amplifier is shown in Figure 16.

The conversion rate is 0.7 V/microsecond, and the half -scale stability time is 6 microseconds ± 0.5 LSB (8 bits).

Powering reset

AD5337/AD5338/AD5339 is powered on under a definition state through the power -to -power reset function. The power -on state is normal, and the output voltage is 0V.

Input and DAC registers are filled with zero, until the device is effectively written into the sequence. This is especially useful for applications that are very important to understand DAC output status when device power power.

Serial interface

AD5337/AD5338/AD5339 controls the serial bus compatible with IC cards. DAC is connected to the bus from the device, that is, AD5337/AD5338/AD5339 DAC does not produce clocks. This interface is in v lt;3.6 V is compatible with SMBUS.

AD5337/AD5338/AD5339 has 7 digits from the machine address. Six MSB is 000110, LSB is determined by the state of A0 foot. Facilities for hard connection changes to A0 are allowed to use one or two devices on one bus. AD5338-1 has the only 7-bit slave address. The six MSB is 010001, and LSB is determined by the status of A0 PIN again. With the combination of AD5338 and AD5338-1, users can accommodate four double 10-bit devices (eight channels) on the same bus.

2 -line serial bus protocol operation is as follows:

1. When the SCL is high, when the SDA line occurs from high to low, the host will start data transmission by establishing start -up conditions. The following bytes are address bytes, consisting of 7 digits from the address, followed by an R/W bit. (This is determined that the data is determined by the device from the subordinate device or the belonging device.)

The slab that has the address corresponding to the sending address to respond by lowering the SDA during the ninth hour pulse period (this name is called For confirmation). At this stage, all other devices on the bus remain idle, and the selected device waits for the data to write or read its displacement register.

2. The data is transmitted through the serial bus in the order of 9 clock pulses (8 data bits, followed by a confirmation bit). The transition of the SDA cable must occur at the low period of the SCL and maintain stability at the high period of SCL.

3. When all the data bit has been read or writes, the stop condition will be established. In the writing mode, the host pulls the SDA cable height during the 10th clock pulse to establish stop conditions. In the reading mode, the main control is not recognized to the ninth clock pulse, that is, the SDA line remains high. Then, the host lowered the SDA cable before the 10th clock pulse, and adjusted during the 10th clock pulse to establish stop conditions.

Reading/Writing Sequence

For AD5337/AD5338/AD5339, all writing access sequences and most read sequences start with the device address (using R/W 0), followed by pointer, then the pointer byte. This refers to the data format of the needle byte and determine which DAC is accessing in the subsequent reading/writing operation. See Figure 31. Operated in writing and the data followed immediately. Use R/W 1 to send the address in the read operation, and then read the data. However, you can also send the address of only R/W 1. The previously loaded pointer settings are used to read back the operation. For graphic explanations of the interface, see Figure 32.

The table below explains that the pointer bytes are constituted.

Input displacement register

The input shift register is 16 bits wide. Enter s in the serial clockUnder the control of CL, the data is loaded into the device as the two data bytes on the serial data line SDA. The timing diagram of this operation is shown in Figure 2. These two data bytes are composed of four control bits and 8, 10 or 12 DAC data, depending on the type of device. The first two of the loaded are PD1 and PD0 bits that control the device operation mode. For a complete explanation, see the shutdown mode " section.

bit 13 is CLR