Introduction

Z8 repeat! Intersection The MCU series products are Zilog series micro -controller product based on 8 -bit EZ8CPU. Z8 repeats! The 64K series, the following is collectively referred to as Z8 ENCORE! Or the 64K series adds 8 -bit micro -controllers for the expansion series of Zilog. The flash memory function in the circuit allows faster development time and procedures in this field. The new EZ8 CPU can be compatible with the existing Z8 instructions. The rich outer setting Z8 Anke! Successfully applied to a variety of applications, including motor control, safety systems, home appliances, personal electronic equipment and sensors.

Features

20 MHz EZ8 CPU

up to 64 kB of flash memory, with in -circuit programming function

# # 8226; 4KB register RAM

12 channels, 10 -digit number converter (ADC)

The transceiver driver enable control

I2C series

serial peripheral interface

The infrared encoder/decoder up to four 16 -bit timers, with the function of capture, comparison and pulse width

(WDT)

3 channel DMA

as many as 60 I/O pins

24 with a configurable configurationable configurationable configuration. Priority interruption

debugger on the film

Voltage Browning Protection (VBO)

POR)

3.0-3.6V operating voltage, with 5V tolerance input

0 ° to+70 ° C, -40 ° to+105 ° C and- The working temperature range of 40 ° to+125 ° C

Part Selection Guide Table 1 lists Z8 re -sing! product line.

Table 1. Z8 sings! 64K series parts selection guidelines

block diagram

Figure 1 shows the architectural box diagram of Z8 ENCORE! 64K series.

Figure 1. Z8 sings! 64K series box diagram

CPU and CPU andOverview of peripheral device EZ8 CPU function

Zilog's latest 8 -bit central processor (CPU) EZ8 meets the demand for faster and more efficient microcontrollers. EZ8CPU executes the super set of the original Z8 instruction set. The EZ8 CPU function includes:

Direct register to the register structure allows each register as a cumulator to improve the execution time, reduce the required program memory

the software stack allows allowing The depth of the sub -routine calling and interrupt is much greater than the hardware stack

compatible with the existing z8 code compatibility

extended internal register file allows access to as high as 4KB

The new instruction improved the execution efficiency programming language of the code developed by higher levels, including C

New explanations of improvement performance, including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, SRL

New instructions support the 12 -bit linear addressing of the register file [ 123]

up to 10 mIPS operations

C compiler friendly

each instruction 2-9 clock cycle

For more information about EZ8CPU, please refer to the av8CPU user manual avail.

General I/O

The 64K series has seven 8-bit ports (port A-G) and a 4-bit port (port H) for general I/O (GPIO). Each pins are separately programmable. All ports (B and

H) support 5V tolerance input.

Flash controller

Flash controller programming and erase the flash memory.

10 -bit digital converter modulus modulus (ADC) converts the analog input signal to 10 binary numbers. ADC receives inputs from 12 different simulation input sources.

Each UART of the General Assembly transceiver is full -duplex, which can process asynchronous data transmission. This UART supports 8-bit and 9-digit data modes, optional spectacles and efficient bus transceivers for controlling the driver to control the multi-receiving bus (such as RS-485).

2 degrees Celsius

Internal integrated circuit (I2C?) Controller to restart the Z8!

C protocol.

C controller consists of two two -way bus, a serial data (SDA) line and serial clock (SCL) line.

Serial peripheral interface

Serial peripheral interface (SPI) allows Z8 to be reinstated! Intersection Exchange data from other peripheral devices, such as EEPROM, A/D converters and ISDN devices. SPI is a passage, synchronization, and character -oriented channels that support the four -line interface.

timer

Most of up to four 16 -bit can be re -loaded with timer can be used for timing/counting events or motor control operations. These timers provide a 16 -bit programmable reload counter and disposable operation, continuous, selection, capture, comparison, capture and comparison, and pulse width modulation

mode. There are only 3 timers (timer 0-2) of the 44-pin software package.

Interrupt controller

64K series products support as many as 24 interrupts. These interruptions consist of 12 inside and 12 general -purpose I/O pins. The interruption has a level 3 programmable interrupt priority.

reset controller

Z8 repeat! Intersection You can use reset pins, power -on reset, door dog timer for reset (WDT), stop mode exit or voltage consumption (VBO) warning signal.

The debugger Z8 on the film is repeated! Intersection With integrated debugger (OCD). Obsessive -compulsive disorder provides a set of rich debugging functions, such as reading and writing registers, programming Flash, setting breakpoints and executing code. Single -needle interface provides communication to the contact network.

DMA controller

64K series has three DMA channels. Two of these channels are RAMs between the registration channel input/output operation. The third channel automatically controls the data from ADC to memory

Table 2 determines the package style available for each device in the Z8! 64K series product line

Table 2. Z8 sings! 64K series software package options

pin configuration

shows the 64K series. For descriptions of the signal, see Table 3. Timeller 3 must not be packed in 40 stitches and 44 stitches.

Do not support the timer 3.

T2OUT is not supported.

64K series 40 -needle dual -column direct packing (PDIP)

64K series 44 -pin plastic lead chip carrier (PLCC)

Address space

Overview

EZ8CPU can access three different address spaces:

I/O port control register.

The program memory contains the address code and/or data of all memory positions with executable files.

Data memory contains the address of all memory positions that only save data. The following sections will briefly introduce these three address spaces.

The register file address space in the 64K series is 4KB (4096 bytes). The register file consists of two parts: control register and general register. when? The instruction is executed, and the register is read and written as the destination when it is defined as the source. The architecture of EZ8CPU allows all generals as accumulaers, address pointers, index registers, stack areas or notes.

The upper limit of the 4KB register file address space is preserved to control EZ8CPUs, peripheral devices and I/O ports. These registers are located from F00H to FFFH. Some addresses in the 256 -byte control register have been retained (unavailable). Read the reserved register file address and return the unfarished value. It is not recommended to write the reserved register file address, which will produce unpredictable results.

RAM on the film always starts from the address 000h in the register file address space.

This 64K series provides 2KB to 4KB of RAM according to the device. Returns the unarmed value from the register file address outside the RAM address (not in the control of the register address space). Write the address of these register files is invalid. Refer to the part selection guide on page 2 to determine the RAM amount available for specific 64K series devices.

Program memory

EZ8CPU supports 64KB program memory address space. Z8 repeats! The 64K pound series contains 16 kb to 64 kb flakes in the program memory address space, depending on the device. Reading from a program memory address outside the flash memory address will return FFH. Written these unrealized program memory addresses will not have any effect. Table 5 describes 64K series products.

Information Zone

Data memory

Z8 repeat! The 64K series does not use the 64KB data memory address space of the EZ8 CPU.

The number of bytes from FE00H to FFFFH. After enabled the information area access, the LDC and LDCI instructions will be returned to the information area data instead of program memory data instead of program memory data. By reading these address films, the test device also returns the information area data. The execution of the code continues to use the program memory correctly. The obtaining information area is read only

Control register Abstract

[ 123]

Reset and stop mode recovery

Overview

At the Z8 replay controller! 64K series control reset and stop mode recovery operation. In typical operations, the following incidents will cause resetting:

Power -powered reset (Por)

voltage attenuation (VBO)

Time -to -see the scheduler timeout (to start resetting through the WDT_RES options)

Set (OCDCTL [0] set to 1) When the 64K series device is in the stop mode, the stop mode recovers the following:

The GPIO port input tube foot conversion of the GPIO port that has been enabled to restore the source

DBG pin driving low

Reset type

64K series Provide two different reset operations (system reset and stop mode recovery). The reset type is 64K series equipment and reset source. Table 8 lists the reset type and its operating characteristics.

System reset

During the system reset process, the 64K series equipment was connected to the 16 -cycle system clock after watching the scheduler oscillator. At the beginning, all GPIO pins are configured to input.

During the reset process, the EZ8 CPU and the peripheral equipment on the tablet are in a state of idle; however, the crystal oscillator and the timer of the door of the door continue running. The system clock starts working after watching the scheduler scheduler oscillator cycle. The EZ8 CPU and the periphery equipment on the film remain idle within 16 cycles of the system clock.

After the reset, the register file with a defined reset value in the register file loads their reset value. After reset, other control registers (including stacking pointers, register pointers and signs) and universal RAM are not defined. EZ8CPU obtains the reset vector at 0002H and 0003h and loads the value in the program counter. The program executes the address from the reset vector.

Powering and reset

Each device in the 64K series contains an internal power -power reset (POR) circuit. This POR circuit monitor the power supply voltage and keep the equipment in the reset state until the power supply voltage reaches the level of safe operation. The power supply voltage exceeds the POR rear table. Reset source and result reset type Operation mode Reset source Reset type Normal or stop

mode

Powering/voltage browning system resetting the door dog timer timeout to configure it to be configured as When resetting, the system reset and reset the PIN assertion system reset film upper adjustment test reset (OCDCTL [0] set to 1) System complexIn addition to the debug device on the film, it is not affected by resetting the stop mode. Reset reset/voltage browning system reset and reset the PIN assertion system reset the DBG pins drive. 64K series

Product specifications

Voltage threshold (VPOR), enable the POR counter, and count the 66 cycles of the Watch DOG timer oscillator. After the POR counter is overtime, the XTAL counter will enable a total of 16 system clock pulse. The device is kept in a reset state until the POR counter and the XTAL counter areout. After the 64K series device exits, the power reset is used, and the EZ8 CPU obtains the reset vector. After the power -on reset, the POR status bit in the WDTCTL register is set to 1.

The figure shows the power -on reset operation. Reference electrical characteristics POR threshold voltage (VPOR) chapter.

Figure. The power -on reset operation

Voltage browning 64K series equipment provides low -voltage brown output (VBO) protection. When the power supply voltage drops to the unsafe level (below VBO), the VBO circuit will sensor the threshold voltage) and enforce the device into a reset state. The power supply voltage is kept below the power -on resetting voltage threshold (VPOR), and the VBO block is kept in a reset state.

When the power supply voltage exceeds the upper -power resetting voltage threshold again, the device is based on the power -on reset seconds, and the progress of the complete system reset sequence is based on the progress of the system. After the power -on reset, the POR status position (WDTCTL) register in the Dog Dog timer control is set to 1. The figure shows the voltage browning operation. Refer to VBO and Por threshold voltage (VVBO) electrical characteristics chapters and VPOR). In the stop mode, the voltage brown output circuit can be enabled or disabled. The operation during the stop mode is set by the VBO_AO option.

Voltage brown reset operation watching the door dog timer reset. If the device is in normal or stop mode, you can start the system when you see that the WDT_RES option is set to 1 Then reset at timeout. This feature is the default (unlikely) setting of the WDT_RES option. The WDT status position in the WDT control register is set to indicate that the reset is started by the timer of the door dog.

The external pins reset and reset pins have a digital filter with Schmidt trigger input, internal pull, simulation filter and noise. Once the reset pin of at least 4 system clocks is asserted

, the device is carried out in the order of system resetting. When the restraint input pin is assertive, the 64K series equipment continues to be restored. If the reset pin is kept low after the system reset, the device withdraw from the reset state is immediately reset the pin to cancel the pin.Configuration. In the external reset pin, the external state position of the door dog timer control (WDTCTL) register is set to 1. The debugger on the film can be used to use the film to control the register by the obsessive -compulsive disorder. The debugger block on the film is not reset, but the rest of the chip for normal system resetting. During the system operation, the first place was automatically cleared and reset. After the system is reset, set the POR bit in the WDT control register.

Stop mode recovery

The stop mode enters from the EZ8 of the execution stop instruction. For detailed stop mode information, please refer to the low -power mode of page 49. When the stop mode recovers, the device reset the 66 -cycle -to -door dog timer oscillator follows the 16 system clock cycle. The stop mode recovery only affects the content of the cermiars to control the register. The restoration of the stop mode does not affect the value in any other register file, including stack pointer, register pointer, logo, peripheral control register and general RAM.

EZ8CPU obtains the reset vector at 0002H and 0003h and loads the value into the program counter. The program executes starts with the reset vector address. After the stop mode is restored, the stop set of the door dog timer controls the stop bit to 1. Table 10 lists the source and results of the stop mode. The following text provides a source of detailed information about each stop mode.

The stop mode of the timer overtime using the door watching dog is restored. If the door dog timer is over time in the stop mode, the device will stop the mode recovery sequence. In the watch dog timer control register, the WDT and Stop bit are set to 1. If the timer configuration of the door dog is generated to generate interruption at time, and the 64K series device is configured to a response interrupt, after the normal stop mode is restored, the EZ8 CPU Ser will receive Essence

The GPIO port PIN conversion pause is suspended for the stop mode to restore each GPIO port pin to the stop mode to restore the input source.

In any GPIO tube foot that enables to stop mode recovery source, the change value of the input pin (from high to low or from low) starts the stop mode recovery. GPIO filters the restoration signal of the stop mode to refuse the pulse that is less than 10NS (typical) within the duration. In the door -to -door timer control register, the stop bit is set to 1. In the stop mode, the GPIO port input data register (PXIN) is disabled.

The port input data register is kept on the port PIN only at the end of the signal at the end of the signal. Therefore, the short pulse on the port PIN can start the stop mode recovery, and the OUT is written into the port input data register, or the IN interrupt is not activated (if the PIN is enabled).

Low power mode

Overview

64K series products have power saving functions. The highest level of power is provided by the stop mode. The power reduction of the next level is a stop mode.

Stop mode

The stop instruction of executing the EZ8CPU puts the device in the stop mode. In the stop mode, the working characteristics are:

main crystal oscillator stop; XIN pin is driven high, and the XOUT pin is driven high.

System clock stop

EZ8 CPU stop

program counter (PC) stopping

See the door dog timer and its internal RC oscillator to continue working, if the operation in the stop mode is enabled.

voltage browning protection circuit continues to work.

All other films on the peripheral equipment are in a free state.

In order to minimize the current in the stop mode, all the GPIO pins configured to digital input must be driven to one of the power rails (VCC or GND). Timer. The device can bring the use stop mode to resume exit stop mode. For detailed information recovery of the stop mode, please refer to the reset and stop mode recovery chapter starting from page 43.

When using the following device to drive the 64K series device, the external clock driver source shall not be used to use the stop mode.

Stop mode

Halt instructions for executing the EZ8 CPU put the device in the Halt mode. In the stop mode, the work characteristics are:

The main crystal oscillator has been enabled and continued to work

System clock has been enabled and continued to run

EZ8 CPU stops

Program counter (PC) stops increasing

Internal RC oscillator of the door dog timer continues to work

[[

123] If you enable it, watch the Dog Timer continues to work

All other films on the peripheral equipment continues to run EZ8 CPU to exit the stop mode through any of the following operations:

Interrupt

See the timer timeout (interrupt or reset)

Voltage browning and reset

external reset pins broken words

In order to be temporarilyThe minimum current in the shutdown mode, all configured GPIO pins input must drive to one of the power rails (VCC or GND).

General I/O

Overview

64K series products support up to seven 8-bit ports (port A-G) and a 4-for general input/output (I/output O) Operation port port (port H). Each port contains control and data registers. The GPIO control register is used to determine the direction of the data, leakage, output drive current and spare pins function. Each port pin is separate programming. All ports (except B and H) support 5V tolerance input.

Building

Figure shows the simplified box diagram of the GPIO port pins. In this figure, the ability description of the ability to adapt to the substitution function and variable port current driving strength.

GPIO port pins frame diagram

GPIO spare function. Many GPIO port pins can be used as general I/O, or you can provide access to the periphery of the access to the film on the film. The function of the device, such as timer and serial communication equipment. This port A -H spare function sub-register configures these tube feet to universal

z8x6421 40 shots [7: 0] [7: 0] [6: 3, 1: 0]- -

Z8X6421 44 needle [7: 0] [7: 0] [7: 0] [6: 0] ---

Z8X6422 64 and 68 stitches [7: 0] [7: 0] [7: 0] [7: 0] [7: 0] [7: 0] [7] [3: 0]

z8x6423 80 shots [7: 0] [7: 0] [7: 0] [7: 0] [7: 0] [7: 0] [7: 0] [3: 0]

Table

List port availability (continued) Schmidt trigger PS019915-1005 GM icenses! 64K series product specifications I/O or spare function operation. When the needle is configured to the spare function, the control of the pipe foot (input/output) is transmitted from the port A -H data direction register to the spare function assigned to the foot from the port A -H data direction register. Table 12 lists the alternative function

to be associated with each port.

GPIO interrupt

Many GPIO port pins can be used as a source of interruption. Some port pins can be configured to generate interrupt requests input signals on the rising edge of the pins or decrease. Other ports of PIN interruption occur at any edge (two) interruptions and declines). For more information, please refer to the interrupt controller chapter to use GPIO pins to interrupt.

GPIO control registers define the four registers of each port to provide access to GPIO control, input data and output dataEssence

Table 13 lists these port registers. Use port A -H address and control registers to provide access to port configuration and control sub -registers.

Interrupt controller

Overview

The interrupt controller on the 64K series of products is prioritized from the peripheral equipment and GPIO port pins. The characteristics of the interrupt controller include the following content:

24 unique interrupt vectors:

- 12 GPIO port pins interrupt sources

- 12 of them Peripheral interruption source

Flexible GPIO interruption

—8 optional rising and decrease along GPIO

─ 4 bilateral interruption [ 123]

Level 3 separate programming interrupt priority

Methods and forced CPU to start interrupt service programs (ISR). Generally, this interrupt service program involves the exchange of data, status information or control information between CPU and interrupt peripherals. When the service routine is completed, the CPU returns to interrupt its operation. EZ8CPU supports vector and rotation interruption. Regarding the interruption of rotation inquiries, the interrupt control has no effect on the operation.

Interrupt vector list

Tables list all available interrupts according to the priority. The interrupt vector is the minimum effective byte (LSB)

building with the maximum effective byte (MSB) in the parity program memory address and the following odd number program memory address.

Interrupt controller box diagram

Operation

Main interrupt enabled interrupt control register The main interrupt opening position (IRQE) global enabled and enabled and enabled and enabled and enabled and enabled and enabled and enabled and enabled and enabled and enabled and enabled enabled. Disable interruption. The interrupt can be enabled through any operation below:

execute the EI (enabled interrupt) instruction

execute IRTT (from interruption) instruction

Write 1 into the IRQE bit in the interrupt control register

The interrupt is banned by any operation by the following operations:

123] EZ8 CPU confirmed that the interrupt service request controller from the interrupt

write 0 to the IRQE bit in the interrupt control register

reset [ 123]

Execution trap instruction

illegal instruction trap

Interrupt vector and priority interrupt controller support the three -level interrupt priority. The third level is the highest priority, level 2 is the second high priority, and level 1 is the minimum priority. If all interrupts are enabled by the same interrupt priority (all interruptions are 2 interrupts, for example), the interrupt priority will be based on

. The priority of the 3 -level interrupt is always higher than the 2 -level interrupt. In the turn, it is always higher than the first -level interrupt. In each interrupt priority internal level (level 1, level 2 or level 3), the priority is allocated according to the provisions of Table 23. Reset, look at the scheduler timer interrupt (if enabled) and illegal instruction traps are always the highest priority.

Interrupt assertion

The interrupt source of the interrupt source is only a single system clock cycle (single pulse). When the EZ8CPU confirms the interrupt request, the corresponding position in the interrupt request register is cleared until the next interrupt occurs. Write a 0 to interrupt request register, which also clear the interrupt request.

The following is not recommended to clear the interrupt request register median encoding method. The execution of all the first LDX commands and the last LDX command received between the receiving interruptions between them will be lost. It may lead to the bad coding style of the loss request: LDX R0, IRQ0, and R0, the mask LDX IRQ0, R0 to avoid loss of interruption, the following types of code are used to clear the recommended interrupt request 0 register: good encoding style to avoid loss interrupt request requests requests loss interrupt requests : Andx IRQ0, the mask software interrupt assertion program code can be generated directly. In the interruption, the required request requested register is triggered to trigger the interrupt (assuming the interrupt is enabled). When the EZ8CPU confirms the interrupt request, the bit in the interrupt request register is

automatically cleared to 0.

The software interrupt is generated by setting the following types of code. It is not recommended to interrupt the bit in the request register. All the LDX command received between the interruption between the first LDX command was lost between the first LDX command.

Permanent coding styles that may cause interrupt requests: LDX R0, IRQ0 or R0, mask LDX IRQ0, R0 In order to avoid loss of interruption, the following types are used to use interrupt request register: good coding style Avoid loss interrupt requests: ORX IRQ0, mask interrupt control register definition definition for all interruptions except the timer interrupt of the door, the interrupt control register enables a single interrupt, sets the interrupt priority, and indicates the interrupt request.

Interrupt request 0 register

Interrupt request 0 (IRQ0) register (Table 24) stores the interrupt request vector and rotation inquiry interrupt in two cases. When the request is proposed to the interrupt controller, the corresponding bit of the IRQ0 register becomes 1. If the interrupt is enabled by the global (VEC storage interrupt), the interrupt controller will be in ChinaDispel request passed to the EZ8 CPU. If the interrupt is banned by the global (round -up interrupt), the EZ8 CPU can read the interrupt request 0 register to determine whether there are any interrupt requests to hang

T2I timer 2 interrupt request

0 timing of time Device 2 did not hang the interrupt request.

1 The interrupt request of timer 2 is waiting for the service.

T1I timer 1 interrupt request

0 timer 1 did not hang the interrupt request.

1 The interrupt request of the timer 1 is waiting for the service.

T0i timer 0 interrupt request 0 timer 0 did not hang the interrupt request.

1 The interrupt request from the timer 0 is waiting for the service.

U0RXi-UART 0 receiver interrupt request 0 No interrupt request waiting for UART 0 receiver.

1 The interrupt request from the UART 0 receiver is waiting for the service.

U0TXI-UART 0 transmitter interrupt request 0 No interrupt request waiting for UART 0 transmitter.

1 The interrupt request from the UART 0 transmitter is waiting for the service.

Confidential range -I2C interrupt request

0 I2C did not hang an interrupt request.

1 Interrupt request C from i2 is waiting for the service. SPII-SPI interrupt request

0 SPI did not hang the interrupt request.

1 Interrupt request from SPI is waiting for the service.

ADCI-ADC interrupt request 0 analog-digital converter does not wait for an interrupt request.

1 The interrupt request of analog to a digital converter is waiting for the service.

Interrupt request 1 register

Interrupt request 1 (IRQ1) register (Table 25) The interrupt request of storage vector storage and rotation interrupt. When a request to the interrupt controller, the corresponding bit of the IRQ1 register becomes 1. If the interrupt is enabled globally (vector storage

interrupt), the interrupt controller will pass the interrupt request to the EZ8 CPU. If the interruption is prohibited globally (rotating interruption), the EZ8 CPU can read the interrupt request 1 registration to determine whether there is any interrupt request to hang.

The timer box diagram

Operation

The timer is a 16 -bit incremental counter. Set the minimum time delay 0001h by loading value. Enter the timer to reload the high byte and low byte registers and set the