Features

2 singles+3.3V power supply

High signal -to -noise ratio: 61.7dbfs

Total Power Consumption: Internal Reference: 366MW

External parameters: 330MW

Internal or external reference

Low DNL: ± 0.1LSB

Flexible input range: 1.5VPP to 2VPP

tqfp-64 pack

# 8226; communication mid -frequency processing

Communication base station

Test equipment

Medical imaging

# 8226; Video Digitalization

CCD Digitalization

Explanation

ADS5237

is a dual high -speed high -dynamic range 10 -bit assembly line modulus conversion conversion Instrument (ADC). This device includes a high -bandwidth sampling holder, which has excellent bruises that are high or exceeded the Naquist rate. Sampling maintains the differential characteristics of the amplifier and the ADC circuit to minimize the even digital harmonic and provide excellent co -model noise resistance.

ADS5237 provides the full marking range of the settings of the converter without any external reference circuit. Internal reference can be disabled, allowing low -driving and external reference in the multi -channel system to improve tracking.

ADS5237 provides an over -range indication sign to indicate the input signal beyond the input range of the converter's full marker input range. This flag can be used to reduce the gain of the front -end gain control circuit. There is also an output enable pipe foot, allowing multiple reuse and testing on the printing circuit board (PCB).

ADS5237 uses digital error correction technology to provide excellent differential lineivity for demanding harsh imaging applications. ADS5237 is provided in the TQFP-64 software package.

Please note that the availability, standard guarantee and use of standard guarantees, and the use in key applications, and the important notice of the exemption declaration in the key application of Texas instrument appear at the end of the data table.

The definition of specifications

Simulation bandwidth

The analog input frequency, at this frequency, the spectrum power of the base frequency (determined by FFT analysis) is reduced by 3DB.

Pore diameter delay

The time delay between the actual time between the sampling clock rising edge and the sampling.

Pole diameter uncertainty (jitter)

Sample changes between the aperture delay.

The clock occupation ratio

High pulse width is ADCLK pulse maintained logic 1 " state to achieve the minimum amount of rated performance. Low pulse width is the shortest time (logic "0 ") that ADCLK pulse should maintain low state. At the given clock rate