Features

Double, the minimum sampling rate is 105 mps; channel isolation, gt; 80 decibels; including exchange coupling signal adjustment; gain flatness reaches Naquist: lt; 0.2 decibel; Bobby 1.1: 1 to Naquist; 80 decibels have no mixed dynamic range; two -supplement output format; 3.3 V or 5 V CMOS compatible output level; 0.850W per channel; military industry level.

Application

Radar medium frequency receiver; phase control array receiver; communication receiver; security communication; GPS anti -interference receiver; multi -channel multi -mode receiver.

Product description

AD10200 is a full -channel ADC solution with a module signal adjustment function, which can improve the channel performance of dynamic performance and complete matching. The module includes two wide dynamic range ADC. Each ADC has an front end of a transformer coupling, which is optimized to directly sample. The AD10200 has intra -film tracking and maintenance circuits, and uses an innovative architecture to achieve the performance of 12 -bit 105 MSPS. The AD10200 uses an innovative high -density circuit design. While maintaining good isolation, it will achieve excellent matching and performance, and provide significant board area saving.

AD10200 uses a 5.0V power supply for mold conversion. Each channel is completely independent, allowing independent encoding and simulation input to operate. AD10200 is packaged in the 68 lead ceramic chip carrier packaging. The manufacturing line (QML) and components of the manufacturing of-38534 on MIL MIL companies can reach H Class (–55 ° C to+125 ° C).

Product Highlights

1. The guarantee sampling rate is 105 MSPS.

2. Input signal adjustment, the full power bandwidth is 250 MM.

3. Fully test/represent performance under 121 MMIN AIN.

4. Optimization of medium frequency sampling.

Function box diagram

Simulation bandwidth specification definition

Simulation input frequency. At this frequency, the spectrum power of the base frequency (from FFT by FFT Analysis and determination) Reduce 3dB.

Pore diameter delay

The encoding command rises between 50%point and the delays between the upper part and the simulation input sampling time.

Pole diameter uncertainty (jitter)

Sample changes between the pore diameter delay.

Fortune non -linearity

Any bias of any code from the ideal 1LSB step.

Coding pulse width/duty ratio

High pulse width is coding pulse to maintain logic 1 " stateTo achieve the minimum amount of rated performance; low pulse width is the minimum amount of coding pulse to maintain low state. At a given clock rate