Introduction

TVP5147 is a high -quality single -piece digital video decoder. It digitizes all popular baseband simulation video formats and decodes into digital component videos. The TVP5147 decoder supports the modulus conversion of the YPBPR signal, and NTSC, PAL, SECAM composite, and S-Video to the modulus of the weight YCBCR model conversion and decoding. The decoder includes two 10-bit 30-MSPS A/D converters (ADC). Before each ADC in the device, the corresponding analog channel contains an analog circuit, which will be cut into the reference voltage and apply a programmable gain and offset. A total of 10 video input terminals can be configured to configure a combination of YPBPR, CVBS or S-Video video input.

The composite or S video signal is sampled at 2 × square pixels or ITU-R BT.601 clock frequency, locks alignment, and then draws 1 × pixel rate. CVBS decoding uses five elements of adaptive comb filtations for Luma and Chroma data paths to reduce cross -luma and cross chroma pseudo -shadows. It also provides a color trap filter. At the CVBS and S-Video input terminals, users can control the video features through the IC host port interface, such as contrast, brightness, saturation, and color. In addition, it also includes the peak (sharpness) with a programmable gain and the color improvement (CTI) circuit that obtains patented chroma.

You can select the following output format: 20 digits 4: 2: 2 YCBCR or 10 -bit 4: 2: 2 YCBCR.

In addition to generating digital video output, TVP5147 decoder also generates synchronization, elimination, field, activity video window, horizontal and vertical synchronization, clock, GenLock (for downstream video encoder synchronization), host CPU interrupt And programmable logic I/O signal.

TVP5147 decoder includes methods for retrieval for high -level vertical removal interval (VBI) data retrieval. VBI data processor (VDP) perform slices, analysis and error checks on Teletext, closed -circuit subtitles (CC) and other VBI data. A built -in FIFO stored more than 11 lines of Teletext data. Through the proper host port synchronization, a full -screen Teletext retrieval can be performed. The TVP5147 decoder can process the host -based VBI processing by the original Luma data of the output format 2 × sample.

The main blocks of the TVP5147 decoder include:

steady synchronization detection of weak and noise signals and VCR technical modes

-D 5 line self -adaptive comb or chroma trap filter to achieve Y/C separation

The 10-bit 30-MSPS A/D converter of the device [clamp and automatic gain control (AGC)

analog video output

brightness processor [123 ]

Performators

clock/time processor and power off control

123] output formatting program

IC host port interface 2

VBI data processor

macrovision #63722; Copy the protection detection circuit (type 1, 2, 3 and independent color band detection)

3.3-v fault tolerance number I/O port

Detailed function

two 30-MSPS, 10-bit A/D channel, with programmable gain control

, G, H, I, M, N, NC, 60) and SECAM (B, D, G, K, K1, L) CVB and S-Video

The simulation component ypbpr video format

10 analog video input terminals are used for multi -source connection

Support simulation video output

# 8226; User's programmable video output format

-10 ITU-R BT.656 4: 2: 2 YCBCR, with embedded synchronization

-10 bits 4: 2: 2 YCBCR and with Synchronous-20-bit 4: 2: 2: 2: 2 YCBCR and separate synchronization

-2 × The sampling raw VBI data in the active video during the vertical elimination period

-D. Slot VBI data (full -field mode)

Hsync/vsync output with a programmable location, polarity, width and field ID (FID) output

Composite and S-Video Processing

-The adaptive 2-D 5 line adaptive comb filter for composite video input; providing color trap

-Orior video standard detection (NTSC /PAL/SECAM）和切换

-具有可编程增益的Luma峰值

-获得专利的色度瞬态改善（CTI）

专利架构，用于Lock, Noise or unstable signal

-The 14.31818-MHz single reference crystal suitable for all standards (ITU-R.BT601 and square pixel sample)- Generate

-GenLock output RTC format for downstream video encoder synchronization

certified macrovision #63722; copy protection test

VBI data processor

-In NABTS (NABTS, WST)

-CC and Extended Data Services (EDS)

-Wide-screen signal (WSS)

Copy generate Management System (CGMS)

Video Program System (VPS/PDC)

-Vertical interval time code (VITC)

-Gemstar #63722; 1 ×/2 × mode mode

-V chip decoding

-The registers of CC, WSS (CGMS), VPS/PDC, VITC, and Gemstar 1 ×/2 × Sicida data

IC host port interface 2

reduce power consumption: 1.8 V digital core, 3.3 V digital I/O and 1.8 V/3.3 V simulation core, with a power -saving and power -off mode [ 123]

80 terminal TQFP power board #63722; package

1.2 TVP5147 application

DLP projector

#8226 Digital TV

LCD TV/Display

DVD burning machine

PVR

#8226 ; Pc video card

Video capture/video editor

Video conference

Figure Figure

]

terminal allocation

Function description

Simulation processing and A/D converter

Figure simulation processor The functional chart of the A/D converter, they provide analog interface for all video input. It accepts up to 10 inputs, and performs source selection, video clamping, video amplification, A/D conversion, gain, and offset adjustment to make digital video signals center. TVP5147 supports selected simulation input videosAn analog video output.

Simulation processor and A/D converter

Video input switch control

TVP5147 decoder has two analog channels, at most the most Can accept 10 video input. Users can configure the internal simulation video switch through the IC interface. 10 analog video input can be used for different input configurations, some of which are:

up to 10 optional separate composite video input

as many as four up to four One optional S-Video input

up to three optional simulation ypbpr video input and a CVBS input

up to two optional simulation ypbPR Video input, two S video inputs, and two CVBS input

Input Select the input register execution (see Section 2.11.1) at 00h at 00h of the IC child address (see Section 2.11.1).

Simulation input clamping

The internal clamp circuit restores the communication coupling video signal to a fixed DC level. The clamp circuit restores the video synchronization level to a fixed DC reference voltage. TVP5147 decoder automatically executes the choice between the bottom and the middle clamping.

Automatic gain control

TVP5147 decoder uses two programmable gain amplifiers (PGA), each channel. PGA can zoom the voltage input compliance with a signal of 0.5-V to 2.0-V to the full marked 10-bit A/D output code range. The 4 -bit code sets a rough gain through the individual adjustment of each channel. The minimum gain corresponding code 0x0 (2.0-v full marking input, -6-DB gain), the maximum gain corresponding code 0xf (0.5 V full standard,+6-DB gain). The TVP5147 decoder also has 12 fine gain control for each channel, and is applied to rough gain control independently. For composite video, the amplitude of the input signal can change significantly from the nominal level of 1V. The TVP5147 decoder can automatically adjust its PGA settings: it can enable automatic gain control (AGC), and can adjust the signal amplitude to reach the maximum range of ADC without limit. Some non -standard video signals include the peak white level of ADC saturated. In these cases, AGC will automatically reduce gain to avoid cutting waves. If AGC is opened, the TVP5147 decoder can read the current gain. Polypropylene polypropylene polypropylene

TVP5147 AGC includes the back -end AGC of the front end AGC and Y/C separation before the Y/C separation. When the compound peak (only before the Y/C separation), the benchmark for force the front end AGC to set the gain too low, and the back -end AGC restores the best system gain. forwardThe end and back -end AGC algorithm can use up to four amplitude reference: synchronous height, color sudden amplitude, peak of synthetic and Luma.

The specific amplitude benchmark used by the front and back -end AGC algorithm can use the AGC Baifeng processing register at the sub -address 74h for independent control. TVP5147 gain incremental speed and gain increase delay can be used to use the AGC incremental velocity register at the sub -address 78h and an incremental delay register located at the sub -address 79h.

Analog video output

The simulation video output terminal provides an analog input signal, which is the input sharing of the selection of the IC register. The signal of this terminal must be buffered by the source follower. The nominal output voltage is 2V P-P, so the signal can be used to drive the 75Ω line. Maintain the amplitude by 16 -step AGC controlled by the TVP5147 decoder. To use this function, the terminal vi_1_a must be set to the output terminal. The input mode selects the register and also selects the activated analog output signal. 2

A/D converter

All ADCs have 10 -bit resolution, which can run up to 30 MSPS. All A/D channels receive the same clock from the chip lock ring (PLL), with frequency between 24 MHz and 30 MHz. All ADC reference voltage is generated inside.

Digital video processing

Figure 2-2 is a box diagram for TVP5147 digital video decoder processing. This module receives digital video signals from ADC and enters CVBS and S-Video input to perform composite processing, and enhances the YCBCR signal enhancement to CVBS and S-Video input. It also generates horizontal and vertical synchronization and other output control signals, such as GenLock for CVB and S video input. In addition, it can also provide indicator signals on -site recognition, horizontal and vertical locking, vertical elimination, and activity video window. Digital data output can be programmed in two formats: 20 -bit 4: 2: 2 Synchronous or 10 -bit 4: 2: 2 Embedded/Independent synchronization. This circuit detects the pseudo -mobilization, AGC pulse and ribbon in the replication protection material of macro visual codes. You can retrieve the information existing in the VBI interval and insert it into the ITU-R BT.656 output as an auxiliary data, or store it in the internal FIFO and/or registers to retrieve it through the host port interface.

Digital video processing box diagram

2 × extraction filter

All input signals are usually excessive sampling (27MHz). The A/D output was initially reduced by extracting the filter, and the data rate was reduced to double the pixel rate. The extraction filter is a half filter. Excessive sampling and extraction filtering can effectively increase the overall signal -to -noise ratio of 3 decibels.

Composite processor

The figure is the frame diagram of the TVP5147 digital composite video processing circuit. The processing circuit receives digital composite or S-Video signals from ADC, and executes Y/C separation (S-Video input bypass), Pal/NTSC, and SECAM chroma, and the YUV signal enhancement.

The 10 -bit composite video was multiplied by the sub -carrier signal in the orthodox demodulator to generate color difference signal U and V. The U and V signals are then sent to a low -pass filter to obtain the required bandwidth. A adaptive 5 -line combic filter separates ultraviolet and Y according to the unique features of the color phase shift between lines and lines. Re -adjust the chroma by the orthogonal regulator, and subtract the chroma from the delayed composite video to generate Luma. This form of Y/C is completely complementary, so it will not lose information. However, in some applications, the U/V bandwidth needs to be limited to avoid string disturbances. In this case, you can open the trap filter. In order to adapt to some viewing preferences, the Luma path also provides peak filters. The contrast, brightness, clarity, color tone and saturation control can be programmed through the host port.

Synthetic and S-video processing box diagram

1 color low-pass filter

High filter bandwidth can maintain clear colors Convert and produce a clear color boundary. However, for non -standard video sources with asymmetric U and V side bands, the filter bandwidth needs to be limited to avoid UV strings. Color low -pass filter bandwidth can be programmed to enable one of the three wave filters. The picture represents the frequency response of the broadband color low -pass filter.

Brightness processing

Digital composite video signal through a brightness comb filter or a chroma trap filter, wherein a filter removes the color information from the composite signal to generate the brightness signal. The brightness signal was then entered into a peak circuit. The picture illustrates the basic function of the bright data path. In the case of S video, the brightness signal bypass the combic filter or color trap filter and directly feed to the circuit. The high frequency component of the peak filter (edge enhancer) enlarged the brightness signal. The figure shows the characteristics of the four different gains that users can program through IC interface programming

Color transient improvement

Color transient improvement (CTI) enhances horizontal color transient transient transient transient Essence The transition point of the color difference signal is maintained, but the edges are enhanced for signals with bandwidth restrictions.

Clock circuit

Internal circuit locks the phase ring to produce a system clock and pixel clock. The driver's loop requires 14.318 MMS clock. This can be input to the TVP5147 decoder at 1.8-V level on the terminal 74 (XTAL1), or connects the 14.318-MHz basic resonance frequency between the terminal 74 and 75 (XTAL2). If the parallel resonance circuit as shown in Figure 2-16 is used, the external capacitor must have to haveBelow Relationship:

CL1 CL2 2Cl--CSTRAY,

Among them, C is a terminal capacitor relative to the ground. Figure 2-16 shows the benchmark clock configuration. TVP5147 decoder generates DataCLK signal for data

VBI FIFO and Auxiliary Data in the video stream

Slip VBI data can be in ITU in ITU -R BT.656 mode as auxiliary data output in the video stream. During the horizontal disappearance period, VBI data output on the terminal of Y [9: 2]. Table 2-7 shows the head format and sequence of the auxiliary data inserted into the video stream. This format is also used to store any VBI data into FIFO. The size of FIFO is 512 bytes. Therefore, FIFO can use the NTSC-NABTS standard to store up to 11 lines of text data.

Table auxiliary data format and sequence

Note: The number of bytes (m) varies from VBI data services.

European Pharmacopoeia:

D0-D5's even-bizari, NEP: negative number strangeness

91H: VBI line slicing data of the first field

[

[ 123] 53H: Slice the data of line 24 to the end of the first field

55h: Slip data of the second field VBI line

97h: Slice the data of line 24 to At the end of the second field

SDID number:

This field saves the data format obtained from the corresponding line mode storage position [2: 0].

The number of datawords starting from byte 8 to 4n+7. Note that this value is a DWORD number of 4 bytes per DWORD.

IDID0:

Trading video line number [7: 0]

bit 0/1 transaction video line number [9 9 [9 9 [9 9 [9 9 [9 9 [9 9 [9 9 [9 9 [9 9 [9 9 [9 9 : 8]

bit 2 matching 2 logo

bit 3 matching 1 logo

If the error is detected in the EDC block, the bit 4 1. If the error is not detected, it returns 0.

Anti-terrorist elite:

The sum of the first data to the last data byte D0-D7.

Filling bytes:

Filling bytes are 4 bytes from byte 0 to the last. For graphic TV mode, byte 8 is synchronous mode byte. Byte 9 is the first data byte.

VBI original data output

TVP5147 decoder can be twoOutput of the original A/D video data of the sampling rate of the external VBI section. This is sent as auxiliary data block, although it is different from the method of sending sliced VBI data in FIFO format described in Section 2.7.1. Part of the activity of the sampling line. VBI raw data uses ITU-R BT.656 format, only Luma data. Use Luma sample to replace the color sample. The TVP5147 decoder inserts the four -byte front guide code 000H 3ffh 3ffh 180H before the data starts. There are no verification and bytes and bytes in this mode.

Adjust the external synchronization

The correct order of programming the following external synchronization is:

Mode):

-Set the video standard to NTSC (register 02H)

-Set Hsync, Vsync, VBLK, and AVID outer synchronization (register 16h to 24h)

To set PAL, PAL-N, SECAM (625 line mode):

-The video standard to PAL (register 02H)

-The set Hsync, vsync, VBLK, AVID External synchronization (register 16h to 24h)

For automatic switch, set the video standard to automatic switch (register 02H)

Internal control registration

tvp5147 decoding decoding The device is initialized and controlled by a set of internal registers. These registers define the operating parameters of the entire device. As mentioned earlier, the communication between the external controller and the TVP5147 is performed through the standard IC host port interface. Table 2-10 shows the summary of these registers. The following sections describe the detailed programming information of each register. The additional register can access through the indirect process, including VBUs with an internal 24 -bit address range. Table 2-11 shows the summary of the VBUS register. 2

Note: Do not write to the retaining register. Unless there is another explanation, any retention in any defined register must be written in 0.

Register setting example

The sample of the register setting below is only provided as a reference. Given the assumption of the input connector, video format and output format. These settings set the TVP5147 decoder and provide video output. No other features and VBI data processor register setting examples are provided here.

Example 1

Assuming

Enter the connector: composite (vi_1_a) (default)

Video format: NTSC (J, M), PAL ( B, g, h,I, n) or sex (default)

Note: By default, NTSC-443, PAL NC and Pal-M are automatically switched by the process. See the automatic switch shielding register at the address 04h.

Output format: 10-bit ITU-R BT.656 (default)

Recommended IC writing: For given assumptions, IC writing: For given assumptions, Just write it once. Set up all other registers by default. 2

IC register address 08h Brightness processing control 3

IC Data 00h Optimize the wave filter of NTSC and PAL. Color treatment control 2 register 2

IC DATA 04H Optimize the colorful filter of NTSC and PAL Select 2

IC register address 34h Output formatting program 2

[

[

[

[

[

[

[

123] IC data 11h enable YCBCR output and clock output 2

Note: By default, HS/CS, VS/VBLK, AVID, FID, and GLCO are logical input. Please refer to the output formatting program 3 and 4 registers at the address 35h and 36h.

示例

假设

输入接口：S-video[VI_2_C（luma），VI_1_C（chroma）]

视频格式：NTSC（J， M, 443), PAL (B, D, G, H, I, N, NC, 60) or SECAM (default) output format: 10-bit ITU-R BT.656, with discrete synchronous output

Recommended settings

The recommended IC writing: This setting requires additional writing to the output discrete synchronization 10 -bit 4: 2: 2 data, HS and VS, and automatically switch between all the video formats mentioned above. 2

Register Setting Example

IC register address 00h Enter select Selection Register 2

IC Data 46h Set luma to vi_2_c, set chroma to vi_1_c2

123] IC register address 04h automatic switch shielding register 2

IC data 3FH including NTSC 443 and PAL (M, NC, 60) 2

IC register address 08h Brightness processing control 3 register 2

IC Data 00h Optimized NTSC and PAL trap filter selection 2

IC register address 0eh colorDevelopment control 2 register 2

IC Data 04H Optimized colorful filter of NTSC and PAL Select 2

IC register address 33h Output formatting program 1

] IC data 41H Select 10 -bit 4: 2: 2 Output format 2

IC register address 34h Output formatting program 2

IC data 11h enable YCBCR output and clock output and clock output 2

IC register address 36h output formatting program 4

IC data 11h Enable HS and VS synchronous output 2

Example

Assuming assumptions

Enter the connector: component [vi_1_b (pb), vi_2_b (y), vi_3_b (PR)]

Video format: NTSC (J, M, 443), PAL (B, D, D, d , G, H, i, N, NC, 60) or SECAM (default) output format: 20 digits of ITU-R BT.656, with discrete synchronization output

Recommended settings

Suggestion recommended IC writing: This setting requires additional writing to output discrete and synchronization 20 -bit 4: 2: 2 data, HS and VS, and automatically switch between all the above video formats. 2

Register setting example

IC register address 00h Enter select Selection Register 2

IC DATA 95H Set the PB to VI_1_B, Y set to vi_2_b, PR set to vi_3_b2

IC register address 04h Automatic switch shielding register 2

IC data 3FH including NTSC 443 and PAL (M, NC, 60) 2

IC Register address 08h Brightness processing control 3 register 2

IC Data 00H Optimized NTSC and PAL trap filter selection 2

IC register address 0eh color sensor processing control 2 [ 123]

IC DATA 04H Optimized chroma filter of NTSC and PAL 2

IC register address 33h Output formatting program 1

IC data 41H select 20 20 Bit 4: 2: 2 output format 2

IC register address 34h Output formatting program 2

IC data 11h enable YCBCR output and clock output 2

IC register address 36h output formatting program 4 register 2

iC data AFH Enable HS and VS synchronous output 2

register setting example

Application information

Application information

[ 123] Application circuit example

Application information

Use PowerPad device design

TVP5147 device packaged in a high -performance, hot -enabled 80 -end PowerPad package (TI packaging instruction Character: 80PFP). PoWERPAD packaging does not require any special considerations, unless you pay attention to the thermal pads (the exposed mold pad at the bottom of the device) is a metal heat conductor and conductivity. Therefore, if the PowerPad PCB function is not implemented, it is necessary to use welded mask (or other assembly technology) to prevent the short circuit of the exposed thermal pads of connecting etching or passing holes under the packaging. However, the recommended choice is not to run any etching or signal pores under the device, but only the grounding hot pad, as described below. Although the actual size of the exposed mold pads may be different, the minimum size required for the 80 terminal PFP power pads is 8 mm × 8 mm. It is recommended to have a hot welding area under the power board component, which is a bronze area. According to the POWERPAD packaging, PCB structure, and calories that need to be removed, the size of the heat sink is different. In addition, according to the structure of the PCB, the hot zone may contain many heat -passing holes. For the TVP5147 device, the hot pad must be grounded to the low impedance ground plane of the device. This not only improves the thermal performance of the equipment, but also improves the electrical grounding of the equipment. It is also recommended to connect the equipment grounding terminal directly to the grounding heat landing. The ground size must be as large as possible, not to connect the signal terminal of the device. The thermal welding rings can be welded on the exposed hot pads with standard return welding technology. Although the thermal pad can float and configure the heat to transfer the heat to the external radiator, it is recommended to connect the heat pad to the low impedance ground plane of the device. More information can be obtained from the TI application comment PHY layout (SLLA020).