Features

Ultra-low noise: 0.95NV/√Hz, 2.6Pa/√Hz; ultra-low distortion; second harmonic RL 1kΩ, g +2; Three harmonic RL 1kΩ, G +2; -10 MMS is 105 decibels; high speed; gain bandwidth (GBWP): 3.8GHz; -3 decibel bandwidth; 700 MMC (G +2); +10); Rotate rate; 475 volts/microseconds (g +2); 1350 volts/microsecond (gram +10); New Bino; customized external compensation, gain range -1,+2 to++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++aring of 10; power supply current: 15 mAh; offset voltage: maximum 0.5 MV; width power supply voltage range: 5 V to 12 V.

Application

front placedrior; receiver; instrument; filter; mid -frequency and baseband amplifier; simulation to digital drive; digital modulus (DAC) buffer; optical electronics.

General description

AD8099 is an ultra-low noise (0.95 nv/√Hz) and distortion (10 MHz-92 DBC) voltage feedback computing amplifier The combination of the two makes it very suitable for 16 -bit and 18 -bit system. AD8099 has a new, high linear, low -noise input level, increased full power bandwidth (FPBW) at low gain and high conversion rate. Simulation equipment company, the proprietary next -generation ultra -fast complement bipolar (XFCB) process, allows this high -performance amplifier to have relatively low power.

AD8099 has an external compensation function, allowing users to set up gain bandwidth products. External compensation allows the gain from +2 to +10, while the bandwidth is the smallest. The AD8099 also has a very high conversion rate of 1350V/microsecond, allowing designers to flexibly use the entire dynamic range without having to sacrifice bandwidth or distortion. AD8099 dropped to 0.1%in 18ns, recovering from a speeding gear within 50ns.

AD8099 drives a 100Ω load at a breakthrough performance level, and the power supply current is only 15 mAh. AD8099 has a wide power voltage range (5V to 12V), low offset voltage (0.1MV typical value), width bandwidth (G +2 is 700MHz), and GBWP up to 3.8GHz. It is designed for multiple applications.

AD8099 has a 3mm × 3mm lead frame chip -level packaging (LFCSP), with a new pin, which is specially optimized for high -performance and high -speed amplifiers. The new LFCSP and Pinout realize the breakthrough properties that previous amplifiers cannot achieve. AD8099 can work within the extended industrial temperature range with a range of -40 ° C to+125 ° C.

Absolute maximum rated value

The stress greater than or equal to the absolute maximum rated value may cause permanent damage to the product. This is just a stress level; it does not imply that the product operates the conditions described in the operation part of this specification or the above conditions. Long -term operation that exceeds the maximum operation may affect the reliability of the product.

Maximum power consumption

The maximum security power consumption of AD8099 is subject to the related elevation limit of chip temperature (TJ). The plastic of the local packaging mold reaches the connection temperature. Under about 150 ° C (that is, the temperature transition temperature), plastic will change its performance. Even if this temperature limit is temporarily exceeded, it may change the stress of the packaging to the mold and permanently change the parameter performance of AD8099. The knot temperature that exceeds 150 ° C for a long time can cause changes in silicon devices and may cause failure. The static air thermal characteristics (θ), ambient temperature (TA) and total power consumption (PD) in packaging determine the chip temperature of the chip. The knot temperature can be calculated as:

The power consumption (PD) in the packaging is the sum of the power consumption in the packaging due to the static power consumption and the load drive of all output. The static power supply is the voltage between the power supply foot (V) and the static current (IS). Assuming the load (RL) refers to the middle load, the total driver power is VS/2 × IOUT, some of which dissipate in the package, and others are dissipated in the load (VOUT × IOUT). The difference between the total driver and the load power is the driving power consumed in the package.

The RMS output voltage should be considered. If in a single power supply, RL refers to VS-, the total driver power is VS × IOUT.如果均方根信号电平不确定，考虑最坏情况，当VOUT VS/4时，RL至中供：

在RL参考VS-的单In the power operation, the worst situation is VOUT vs/2.

The airflow increases heat dissipation and effectively reduce θJa. In addition, more metals directly contact the packaging wires, reduce θJa from metal traces, holes, ground, and power planes. Welding exposed leaves can significantly reduce the overall thermal resistance of the packaging on the ground surface. Pay attention to minimizing the parasitic capacitance of the input of the leader in the high -speed computing amplifier, as described in the PCB layout.

FIG. 4 shows the maximum safety power consumption and exposed blades (EPAD) SOIC-8 (70 ° C/W) and LFCSP (70 ° C/W) in the package 4 layer boards of the Jedec standard. The relationship between ambient temperature. The θ value is approximate.

Typical performance features

Default conditions: vs ± 5 v, TA 25 ° C, RL 1 kΩ, unless there are other instructions. See Figure 63 to 66 component values and gain configuration.

] Operation theory AD8099 is a voltage feedback computing amplifier, using a new highly linear low noise input stage. Using this input level, AD8099 can get a 2V P-P with a reference voltage noise of less than 1NV/√Hz, and the 10MHz output signal to obtain distortion of 90dB. This noise level and distortion performance can only be achieved in completely without compensation amplifier. The gain of AD8099 is as low as +2, reaching this performance level. This new input level also increases the achieveable conversion rate triplet, used to compare the compensated 1NV/√Hz amplifier. The simplified AD8099 topology is shown in Figure 58. The amplifier is a single -increasing benefit level with a unit gain output buffer. AD8099 has an open -loop gain of 85 decibels and maintains accuracy indicators such as CMRR. PSRR, VOS, and △ VOS/△ T are associated with two or more gain -level topology.

AD8099 can be used by using RC network from external compensation to 2. The above gain 15, no external compensation network is required. In order to achieve the full gain bandwidth of the AD8099, any PCB trajectory should not be connected to the external compensation foot or near it to obtain as low as possible.

External compensation allows users to optimize the closedLoop response to obtain the minimum peak, and at the same time increase the gain bandwidth to the higher gain, reducing the more prominent distortion errors in the internal compensation part usually in higher gain. For fixed gain bandwidth, broadband distortion products usually increase by 6 decibels, from a closed -loop gain from 2 to 4. Increasing the gain bandwidth of AD8099, with the increase of closed -loop gain, this impact has been eliminated.

AD8099 has two models: SOIC and LFCSP, and each model has a hot pad to reduce the working temperature. In order to avoid this internal layout of the board, the two packets on the other side of the bag have an additional output tube foot to connect the feedback network to the input terminal. The secondary output pin also isolated from the feedback circuit of the output and self -feeling packaging and key line. When using secondary output as feedback, the inductance in the primary output now helps to separate the capacitance load from the output impedance of the amplifier. Because SOIC's output is high, SOIC can drive capacitance loads more than LFCSP. Use the main output as feedback in two packaging, so that LFCSPDrive the capacitance load better than SOIC.

LFCSP and SOIC pins are the same, except for all pins rotating a pins on the back of LFCSP. This will beolate the input from the negative power supply feet, eliminating the most prominent interdependent coupling when the driver is loaded. Therefore, when driving a large load, LFCSP's second harmonic is significantly better than SOIC.

AD8099 provides a three -state input pin for high impedance power loss and optional input bias current elimination circuits. High impedance output allows multiple AD8099 devices to drive the same ADC or output line time interval-leave. It will be disabled to activate the high impedance state. See Table 5 at the threshold level. When the pin is prohibited, the AD8099 work is normal. When the disable pins are pulled to the positive power range of 0.7V, an optional input bias current eliminating circuit is turned on, thereby reducing the input bias current to less than 200NA. In this mode, users can use high DC impedance to drive AD8099, and still maintain the minimum output reference bias without having to use impedance matching technology. In addition, AD8099 can be coupled when setting the bias point of the input end of the high DC impedance network. The input bias current offsets the circuit to double the input reference current noise, but as long as the broadband impedance remains low, the effect is the minimum (see Figure 48 and Figure 51).

A pair of internal connected diode restricting the differential voltage between non -vertical input and reverse input of AD8099. Each set of diode has two tandem diode, which is connected to the anti -merger. This limits the differential voltage between the input end to about ± 1.8 V. All AD8099 pins are protected by ESD, and the voltage restrictions are connected between two orbit. Protecting the diode can handle a steady -state current of 5 mia. By using series restricted resistors, the current should be limited to 5 mAh or less.

Application information

Use AD8099

AD8099 to provide unparalleled noise and distortion performance in the low signal gain configuration. In low -gain configuration (less than 15), AD8099 needs external compensation. The amount of gain and performance required determines the compensation network.

Understanding the subtlety of AD8099 allows users to understand how to accurately achieve its highest performance. The component value and circuit configuration displayed in the Application Information " section are used as the starting point of the design. A specific circuit application specifies the final configuration and value of the component.

Circuit component

Circuit component is shown in Figure 59