Features and advantages

#9642; n channel MOSFET full -bridge large current grid drive

#9642; independent control of each mosFet

# 9642; The charge pump running in the low power supply voltage

#9642; Cross -conducting protection of the dead zone time

#9642; 5.5 to 50 V power supply voltage range

] #9642; diagnostic output

#9642; Low -current sleep mode

Packaging: 24 -pin Tssop, with exposed heat pads (suffix LP)

Explanation

A4940

is a full bridge controller for external N -channel power MOSFET, which is specially loaded for automotive applications and high -power inductors, such as a DC motor Essence

A unique charged pump regulator provides a complete ( gt; 10V) meter driver, the battery voltage is low to 7V, and the A4940 operation and lower gate driver are allowed to be as low as 5.5V.

The self -raising capacitor is used to provide the above battery supply voltage required by N -channel MOSFET. A unique self -raising management system ensures that the self -raising capacitor is always fully charged to supply high -voltage side grille drive circuits.

Each power MOSFET is controlled independently, but all MOSFETs are protected and are not affected by the dead zone time of the external resistance configuration.

Comprehensive diagnosis provides under pressure and ultra -temperature failure instructions.

A4940 uses a 24 -pin TSSOP power package to supply power, with an exposed pad to enhance the heat dissipation (packaging type LP). Without lead, 100%matte tin drain frame electroplating (suffix-T).

Typical application

function box diagram

door drive time sequence map

Functional description

A4940 is a full -bridge MOSFET drive (front drive), which requires 7 to 50 volts without adjustment power and logical power supply from 3 to 5.5 volts.

The four gate drivers can drive a wide range of N -channel power MOSFET and configure two high -end drives and two low -end drives. The A4940 provides all the necessary circuits to ensure that the voltage of the gate source of the high -voltage and low -voltage side MOSFET is higher than 10 V, and the power supply voltage is reduced to 7 V. For extreme battery voltage conditions, the power supply voltage drops to 5.5 V, but the grid driving voltage decreases, which can ensure normal work.

A4940 provides the interface between the logical grade output of the microcontroller and the high current of the N -channel power MOSFET configured by the full bridge. Generally, the power full bridge will be used for brush DC motor control or other large current inductance loads. Each MOSFET in the bridge is controlled by an independent logical level input, which is compatible with 3.3 or 5V logical output. Cross -conductors in the external bridge can be avoided by time -capable areas.

Low -power sleep mode allows A4940, power bridge, and load to keep connecting the power supply with the battery of the vehicle without extra power switches.

A4940 provides a single fault logo to indicate the lack of pressure and ultra -temperature conditions.

Power supply

The two power supply is required, one for logical interface, and the other for simulation and output driver. The logic power supply connected to the VDD allows the flexibility of 3.3 or 5 V logic interfaces. The main power supply should be connected to VBB through the reverse voltage protection circuit. Both power supply should be separated from the ceramic capacitor connected to the power supply and ground pins.

A4940 works within the specified parameter range. The voltage range of the VBB power supply is 7 to 50 V, and the power supply voltage is low to 5.5 V. This provides a very solid solution for the use of a harsh car environment.

Door drive

A4940 Design is used to drive external, low -conducting resistance, power N channel MOSFET. It provides a large transient current required for fast charging and discharge to reduce the internal loss of MOSFET during the switch. The charging and discharge rate can be controlled by the external resistance connected to the MOSFET gate.

The gate driver voltage regulating grid drive is powered by an internal regulator, which limits the power supply of the driver to limit the maximum gate voltage. When the VBB power supply is greater than 16V, the regulator is a simple linear regulator. When it is less than 16V, the voltage voltage power supply is maintained by the charge pump boost converter. The converter needs to connect a pump capacitor between the CP1 and CP2 pin. The minimum value of the capacitor must be 220 nf, usually 470 nf.

Get a 13 V adjustment voltage on the Vreg pin. A sufficient large storage capacitor must be connected to this tube to provide transient charging current to the low -end drive and guide capacitors.

GLA and GLB needles are low -end gate drivers for external N -channel MOSFETs. The external resistance of the grid drive output and the grid to the MOSFET connection (as close as possible as possible) can be used to control the conversion rate seen at the gate, thereby providing DI/DT and DV/DT output to SA and SB output Some control. GLX will open the upper half of the drive, and provide current to the low -side MOSFET gate in the external power supply bridge, andOpen it. GLX turns low, and the lower half of the driver will be turned on. From the external MOSFET gate circuit to the GND pins, the MOSFET is turned off.

SA and SB Pinsgha and GHB PINS are directly connected to the motor, the voltage on these terminal sensing loads. These terminals are also connected to the negative electrode of the self -lifting capacitor, which is the negative electrode power connection of the floating high -end drive. The discharge current flowing from the high -side MOSFET gate capacitance flows through these connections, which should have a low impedance circuit connection to the MOSFET bridge. These terminals are high -end gate drivers for external N -channel MOSFETs. The external resistance between the grid drive output and the grid to the MOSFET connection (as close as possible as possible) can be used to control the conversion rate seen at the gate, thereby controlling the DI/DT and DV/DT output of SA and SB output. GHX high -power operation will open the upper part of the driver, provide a current to the gate of the MOSFET in the middle and high side of the external motor driving bridge, and open it. GHX turns lowly to open the lower half of the drive, injects the current from the external MOSFET gate circuit to the corresponding SX pin, and close the MOSFET.

CA and CB pins are high -voltage side connections of self -raising capacitors, and the positive power supply of high -voltage side grid drives. When the related output SX terminal is low, the capacitor is charged to about VREG. When the SX output has a high oscillation, the charge on the capacitor makes the voltage on the corresponding CX terminal increased with the output to provide the voltage grille voltage required by the high side MOSFET.

RDEAD pin controls the internal generation of the dead area during the MOSFET switch. The gate -drive circuit prevents cross -conductors, and introduced TDEAD between the dead area between a MOSFET and opening a complementary MOSFET.

When the external resistance connected between RDEAD and agng is greater than 3 kΩ, the dead area is worth emerging by the resistance.

When RDEAD is directly connected to VDD, the default value of the TDEAD is 6 μs (typical values).

Logic control input

Four low -voltage level digital inputs provide control to the gate drive. These logical inputs all have a typical 500 millivol to lag to improve noise performance. They provide a separate direct control of each power MOSFET to prevent cross -transmission and can be used together to provide fast attenuation or slow attenuation of high or low -side re -cycle.

AHI, ALO, BHI and BLO Pins directly control the door drive. XHI input controls high -end drives and XLO input control low -end drives. Internal locking logic ensures that high -voltage side output drivers and low -voltage side output drivers cannot be activated at the same time. Table 1 shows the logical true value table.

Rebating pin This is a activated low input, when activationA4940 is allowed to enter the sleep mode. When the reset is kept at low, the regulator and all internal circuits are disabled, and the A4940 enters the sleep mode. Before entering the sleep mode, there is a short delay when the regulator decoupling and the storage capacitor discharge. This usually requires a few milliseconds, depending on application conditions and component values.

In the dormant mode, the current consumption of the VBB power supply to the minimum level. In addition, locking faults and corresponding fault marks are cleared. When the A4940 is out of the dormant mode, the protective logic ensures that the grid drive output is turned off until the charge pump reaches its correct working state. Under nominal conditions, the oil supply pump is stable within about 3 ms.

Reset can also be used to clear the locking fault logo without entering the sleep mode. To this end, keep a low reset in TRES at the time of reset pulse. This will clear the lock -locking capacitor under pressure failure, and the failure will be disabled out of the output.

Note that the A4940 can be configured to start without any external logic input. For this reason, please pull the reset to VBB through the external resistor. The resistance value should be between 20 and 33 kΩ.

Diagnosis

A4940 integrated some diagnostic functions to provide fault state instructions. In addition to the failure within the system, such as under pressure and overheating, the A4940 integrates each self -lifting voltage monitor of each self -lifted capacitor.

Failure pins This is an open leak output fault sign, indicating the fault status through its status, as shown in Table 2. The external resistance (usually 10 to 47 kΩ) must be pulled to VDD.

Failure status

If the joint temperature exceeds exceeding the temperature threshold (typical value 170 ° C), the A4940 will enter the over -temperature fault state, and the fault will be lower. TJF -TJFHYS is removed when the temperature failure state and failure will be removed when the temperature drops to the following definition.

No circuits will not be prohibited. The external control circuit must take action to restrict power consumption in some way to prevent overheating damage to the A4940 chip and unpredictable device operations.

VREG underwritten VREG provides low -end door drives

and guide charge current. Before enable any output, it is crucial to ensure that the voltage is high enough. If the voltage at VREG and VREG is lower than the drop of VREG underwriting lock threshold VreguVOFF, the A4940 will enter the VREG underwriting failure state. In this state of failure, the failure will be low and the output will be disabled. When Vreg rises to VREGUVON higher than the VREG underwriting threshold, Vreg's underwriting failure state and fault sign will be cleared.

VREG underwriting monitoring circuit is in an active state during power, A4940 remains in VregThe underwriting failure state is not until Vreg Vreg's underwriting lock threshold Vreguvon.

Self-lifting capacitor owl voltage A4940 monitors a single self-lifted capacitor voltage to ensure that they have enough charge to provide current pulse-Table 2 for high voltage. Driver of fault definition. Before turning on the high -voltage side drive, the voltage on the relevant guidance capacitors must be higher than the opening voltage limit. If not, the A4940 will start the guidance charging cycle by activating the auxiliary low -end drive. Under normal circumstances, this will be charged to the boot capacitor to turn on the voltage in a few micro seconds, and then the high -end drive will be enabled.

When the high -voltage side drive is activated, the guidance voltage monitor is maintained. If the voltage drops to the lower voltage, the charging cycle will be activated.

In any case, if there is a failure to prevent the charging of the guidance capacitor, the charging cycle will time out, the failure will be low, and the output will be disabled. Guide the underwriting failure state keeps locking until the reset is set to low.

VDD owed pressure monitoring VDD logical power supply to ensure the correct logical operation. If the voltage at VDD at VDD is lower than the decreased VDD underwriting threshold, VDDUVOFF, the A4940 will enter the VDD under pressure failure state. In this state of failure, the failure will be low and the output will be disabled. In addition, due to the unable to guarantee the state of the report, all the failure status will be reset and replaced with a VDD under pressure failure state. For example, VDD owed pressure will reset the existing Boostrap underwriting failure condition and replace it with VDD under pressure failure. When VDD rises to VDDUVOFF+VDDUVHYS definition, the VDD under pressure lock threshold is above, the VDD owed pressure fault status and fault sign will be cleared.

The VDD under pressure monitoring circuit is in an activation state during power, and the A4940 is maintained in the VDD under pressure failure state until the VDD is greater than the rising VDD underwriting threshold VDDUVOFF +VDDUVHYS.

Application information

Death time

In order There is a dead area delay TDEAD between high or low -side offsers and the next complementary incident. When any complementary high -side and low side MOSFET is switched at the same time (for example, when using a synchronous rectification or after a self -lifting capacitor charging cycle), cross -conducting potential will occur. In the A4940, the two -phase dead area time is set up between RDEAD and AgND pins by RDEAD in a dead area.

For the value of RDEAD between 3 #61472; and 240 kΩ at 25 ° C, the value of TDEAD (NS) may be approximately:

The RDEAD is KΩ. Figure 1 illustrates the relationship between TDEAD and RDEAD. The RDEAD value is obtained between 6 and 60 kΩ #61472;

IDEAD current can be estimated in the following ways:

By connecting the RDEAD pin directly to the VDD, you can set the maximum deadline of 6μs.

Or, you can disable the dead zone time in A4940 by connecting the RDEAD pin directly to GND. In this case, the required dead area must be provided by the external controller.

The choice of power MOSFET and outer collar pole resistance determines the choice of resistance RDEAD in the dead area. The dead area should be long enough to ensure that a MOSFET in a phase has stopped conductive before completing MOSFET. This should also take into account the tolerance and change of the MOSFET grid capacitor, series grid pole resistance, and A4940 internal drive resistance.

Only a MOSFET appeared in TDEAD after its OFF command of its complementary MOSFET. In the case of permanent closure of the phase driven side, for example, when using a slow decaying diode rectification, there will be no dead zone time. In this case, after the corresponding phase input becomes high, the gate drive will be opened within the specified transmission delay. (Reference door drive timing map.)

braking

A4940 can be used to execute dynamic braking, forced all low -voltage side MOSFET opening and high -voltage side MOSFET closure (alo blo 1, AHI 1, AHI 1, AHI BHI 0), or opposite, forced all low -voltage side shutdown and high -voltage side opening (alo blo 0, AHI BHI 1). This effectively short -circuited the electromotive force of the motor and generated a disconnected torque.

During braking, the load current may be approximately:

Among them, VBEMF is the voltage generated by the motor, and RL is the resistance of the phase winding.

Be careful when braking to ensure the maximum rated value that does not exceed the power MOSFET. Dynamic braking is equivalent to the slow attenuation of synchronous rectification.

The choice of self -lifting capacitors

must be correctly selected to guide the capacitor CBOOTX to ensure the normal work of A4940. If the capacitance is too high, the charging capacitance will waste time, thereby limiting the maximum duty cycle and pulse width. If the capacitor is too low, when the charge is transferred from CBOOTX to the MOSFET gate, there will be a large voltage drop due to the charge sharing.

In order to keep this voltage drop, the charge in the self -raising capacitor QBOOT should be much larger than the charge required for the grid qgate of MOSFETEssence Coefficient 20 is a reasonable value. You can use the following formula to calculate the value of CBOOT:

Among them, VBoot is the voltage on the capacitor.

When the MOSFET is turned on, the voltage drop on the capacitor can be approximate:

So for the factors of 20, ΔV is about 5 of VBOOT 5 %.

Under normal working conditions, the maximum voltage of the capacitor is VREG (MAX). In most applications, there is a good ceramic capacitor, and the working voltage can be limited to 16 volts.

Self -lifting charging

Before the high voltage side pulse width modulation cycle is required, it is best to ensure that the high -voltage side self -raising capacitor is fully charged. The time required for capacitors charging TCHARGE (μs) is approximate:

Among them, CBOOT is the value of the capacitor, the unit is NF, and ΔV is the need for self -raising capacitors to lift the capacitor needs Voltage.

After the driver is disabled for a long time, the guide capacitor can be completely discharged. In this case, ΔV can be regarded as a full -high drive voltage, 12 V. Otherwise, ΔV is the amount of voltage drop during the charge transfer process, and it should be 400 mv or smaller. When the SX pin is pulled down and the current flows to the CBOOT through the internal guidance of the diode circuit through the VREG, the capacitor is charged.

Self -service charging management

A4940 provides automatic guide capacitor charging management. Self -lifting capacitors per phase of each phase are continuously inspected to ensure that it is higher than the self -raising voltage threshold VBOOTUV. If the voltage of the self -lifting capacitor is lower than this threshold, when the corresponding high -voltage side activates, the A4940 will open the necessary low -voltage side MOSFET and continue to charge until the self -raising capacitor exceeds the underwriting threshold plus the lag, VBOOTUV+VBOOTUVHYS.

If the voltage of the guide capacitor is lower than the threshold, when the corresponding high -voltage side is commanded by the command, the A4940 will not try to open the high -voltage side MOSFET. More than the underwriting threshold plus lag.

The minimum charging time is usually 7 μs, but for a very large self -raising capacitor value ( gt; 1000NF), the charging time may be longer. If the self -lifting capacitor voltage does not reach the threshold within about 200 μs, the underwriting failure will be marked.

The selection of Vreg capacitors

Internal reference voltage VREG provides current to the low -voltage side grille drive circuit, providing a charging current for self -lifting capacitors. When the low side MOSFET is opened, the gate driver circuit will provide the gate with high transient current required to quickly open the MOSFET. This current can be hundreds of centsAnn, it cannot be directly provided by the limited output of the VREG regulator. It must be provided by an external capacitor connected to the VREG pin.

The informal current of high -sides MOSFET is similar to that of the low -side MOSFET, but it is mainly provided by self -raising capacitors. However, self -raising capacitors must be recharged from the Vreg regulator. Unfortunately, guiding charging may occur after a short period of time, and the low -voltage side opens. This requires that the capacitance value connected between Vreg and agng should be high enough to reduce the transient voltage on the VREG to minimize the low -voltage side MOSFET power -power and self -lifting capacitor charging. 20 × CBOOT is a reasonable value. The maximum operating voltage will never exceed Vreg, so the rated voltage of the capacitor can be as low as 15 V. The capacitor should be placed as close to the Vreg pin as possible.

The power supply is decoupled

Because this is a switch circuit, all the power supply at the switch point has a current peak. Like all such circuits, the power connection should be separated from the ceramic capacitor (usually 100 NF) between the power pins and the ground. These capacitors should be as close to the device's power pitch, VDD and VBB, and ground pins, GND.

Power consumption

In applications with high environmental temperatures, the power consumption may become a key factor. Pay attention to ensure that the operating conditions are allowed to keep the A4940 within the safe range of connecting temperature.

A4940, PD consumption power can be estimated in the following ways:

Among them N is the number of MOSFET switches in a PWM cycle. N 1 means that the diode is degraded slowly, n 2 means synchronous rectification and decay or diode recurrence fast decay. N 4 means synchronous fast decay.

Suggestions

When designing high -frequency, fast switch, large current circuit, you must carefully consider the PCB layout. Here are some of the suggestions on consideration:

A4940 ground, grounding, and high -current circuit of the external MOSFET should be returned to the negative electrode of the motor power filter capacitor. This will minimize the effects of switch noise on the logic and simulation reference of device.

The exposed thermal pad should be connected to the ground pins, and it may constitute part of the power supply of the controller (see Figure 2).

By using short and wide copper wires on all power MOSFETs and source extremes, the mixed inductance feels to the lowest. This includes a public power supply for motor lead, input power bus, and low -voltage side power MOSFET. This will minimize the voltage generated by fast switching large load current.

Considering the use of small (100NF) ceramic capacitors between the source and drain of the power MOSFET to limit the rapid transient voltage peak caused by the inductance of the circuit trajectory.

RDEAD's grounding connection should be directly connected to the AGND pins independently.This sensitive component shall not be directly connected to the power supply public line or public ground plane.It must directly quote Agnd Pin.

VBB, Vreg, and VREG, and VDD power supply decouples are connected to the controller power supply ground, and the controller's power supply is connected independently near the ground pins.The decoupling capacitor should also be as close to the relevant power supply as possible.

Please note that the above is just suggestions.Each application is different and may encounter different sensitivity.A driver running a few ampels is less likely to be affected than a driver running 150 amp. Each design should be tested at the maximum current to ensure that any parasitic effect is eliminated.

Input Output Structure

Packaging LP 24 -pin Tssop, with exposed heat pads