Features

2, 3 or 4 units in series protection control

Provide a separate battery voltage and battery voltage for the battery management host

Integrated unit balance driver

I2C compatible user interface allows access battery information

The programmable threshold and delay charging are overloaded and short -circuit discharge procedures

System alarm interrupt output

Host control can start the dormant power mode and ship mode and ship mode.

Integrated 3.3-v, 25 mAh LDO

the power supply voltage range is 4.5 v to 25 v

typical ones 60-low power supply current of Weian

BQ29312A

and BQ29312 completely compatible

laptop computer

]

Medical and testing equipment

Portable instrument

Instructions

BQ29312A is a 2, 3 or 4 -core lithium -ion battery The group protection simulation front end (AFE) integrated circuit integrates a 3.3 volt and 25 mAh low -voltage differential regulator (LDO). BQ29312A also integrates the i2C compatibility interface to extract battery parameters, such as battery voltage and control output state. Other parameters, such as current protection threshold and delay, can be programmed to BQ29312A to increase the flexibility of the battery management system.

BQ29312A provides safety protection under the battery management host for overcharge, overload, short circuit, overvoltage, and underwriting conditions. In the case of overloading and short circuits, BQ29312A automatically turn off the FET driver based on the internal configuration.

The system partition diagram

The communication interface allows the host to observe and control the current status of BQ29312A, realize the balance of the community, enters different power modes, sets overload levels , Set up overloaded hidden delay time, set the short -circuit threshold level of charge and discharge, and set short -circuit hidden delay time.

The unit balance of each unit is performed through the unit bypass path. The path is enabled by internal control registers that can be accessible through the I2C compatible interface. The maximum bypass current is set through the external series resistance and the internal FET drive resistance (typical 400Ω) settings.

(1), the most relatedFor new packaging and ordering information, see the packaging at the end of this document.

(2), BQ29312A can be ordered by adding suffixes in the ordering part number, which are ordered in the form of tapes and rolls, namely: BQ29312APWRBQ29312Anthr.

(3), the QFN package also provides mini rolls, adding suffix T to an orderly part number, namely: BQ29312Antht.

Figure Figure

Status Figure

Function description

Low pressure difference difference The regulator

The input of this regulator can be obtained from the battery pack (BAT) or the battery pack positive extremes (PACK). The output is usually 3.3 V. The minimum output capacitor running stable is 4.7 μF, and the internal current is limited. During the normal operation, the regulator restricted the output current to usually 50 mAh.

Initialization

BQ29312A's internal control circuit is powered by REG voltage, and it also monitors REG voltage. When the voltage of REG is lower than 2.3V, the internal circuit is turned off and all controllable functions, including REG and TOUT output. Robit is not started, unless the voltage is higher than V (startup) to the component terminal. After the stabilizer starts, based on the battery pack voltage, even if the battery pack voltage is removed, it still keeps working through the battery input. If the BAT input is lower than the minimum working range, if the power input of the component is disconnected, the BQ29312A will not work. After starting, when the REG voltage is higher than 2.4V, the BQ29312A is in normal mode.

The initial status of CHG output depends on PMS input. If PMS Pack, CHG ON, but if PMS GND, CHG OFF.

Overload detection

overload detection is used to detect abnormal currents in the direction of discharge. This function is used to protect PASS FET, battery, and any other inner joint components from excessive current conditions. The detection circuit also includes an anti -hidden delay, and then drives the control of the control to the shutdown state through FET. The overload detection voltage is set in the OLV register, and the delay time is set in the OLT register. The overload threshold can be programmed between 50 MV and 205 MV, with 5 MV as a step, the default value is 50 MV, and the lag is 10 MV.

Short -circuit detection

Short -circuit detection is used to detect abnormal currents in charging or discharge direction. This security function is used to protect PASS FET, battery, and any other inner associated components from excessive current conditions. The detection circuit also includes an anti -hidden delay, and then drives the control of the control to the shutdown state through FET. The short -circuit threshold and delay time are in SCCSet in the SCD register, where SCC is used for charging and SCD is used for discharge. The short -circuit threshold can be programmed from 100 MV to 475 MV in the 25 MV steps, and the default value is 100 MV, which is lagging behind 50 MV.

overload and short -circuit latency

overload delay (default value 1 ms) allows the system to accept high current state instantly when the load power supply is continuously turned on. The delay time can be increased through the OLT register. The register can be programmed from a range of 1 ms to 31 ms and the step length is 2 ms.

Short -circuit delay (default value 0 microsecond) can be programmed in SCC and SCD registers. This register can be programmed from 0 microsecond programming to 915 microseconds through 61 microseconds.

overload and short -circuit response

When the overload or short -circuit failure is detected, the FET is closed. Status (B0 ... B2) register report short -circuit (charging), short -circuit (discharge) and overload details. The corresponding state (B0 ... B2) bit is set to 1, and the Xalert output is triggered. This state is locked until the control (B0) is set and then reset. If the FET is turned on by reset control (B0), and there are still error conditions on the system, the device will re -enter the protective response state.

Battery voltage

The battery voltage is converted to a single series component that allows the system host to measure the battery. The voltage of series components is converted to a GND -based voltage, which is equal to 0.15 ± 0.002 of the voltage of the series components. This provides the range from 0 V to 4.5 V. The translation output is inversely proportional to the input of the following squares.

Among them, V (unit output) - k × v (unit input) +0.975 (v)

Programming unit (B1, B0) select a single series elements. Unit selection (B3, B2) selects voltage monitoring mode, unit monitoring, offset, etc.

The calibration of the cell voltage monitoring amplifier gain

The battery voltage monitor amplifier has a offset. In order to improve the accuracy, it can be calibrated.

According to the calibration, there are several ways.

The following procedures take the measurement and calculation offset and gain as an example.

Step 1

- Set CAL1 1, CAL0 1, Cell1 0, Cell0 0, VMEN 1

--vref at ± 1 at ± 1 The range is adjusted to 0.975 V, and the measuring VREF can eliminate its error.

- Directly measure the internal reference voltage VREF directly from Vcell.

--vref The reference voltage measured

Step 2

- Set CAL1 0, CAL0 0,Cell1 0, Cell0 1, VMEN 1

-The output voltage includes offset, indicating: vo (4-5) vRef+(1+k) × vos (v)

[ 123] Among them, K cell ratio factor

-vos internal computing amplifier input terminal offset voltage

Step 3

- Set CAL1 1, CAL0 0, Cell1 0, Cell0 0, VMEN 1

- Reference voltage of the measuring label measurement through VCell amplifier.

-The output voltage includes the marking factor error and offset, which is expressed as:

v (outr) vREF+(1+K) × VOS × VREF (v)

Step 4

-Calculation (VO (4-5) --v (OUTR)/VREF

-The result is the actual proportional factor K (ACT), which is indicated as it is indicated as it is indicated as it is indicated that it is expressed as a representation. :

k (action) (vo (4-5) --v (outr))/vRef (vREF+(1+K) × VOS)-(VREF+(1+K) × Vos — K × VREF)/VREF K × VREF/VREF K

Step 5

- Calculate the actual offset value, where:

VOS (ACT) (VO (4-5) -vref)/(1+K (ACT))

Step 6

-The calculation method of calibration battery voltage is as follows:

VCN -vc (n+1) {vREF+(1+K (Act)) × Vos (ACT) —V (Cellout)}/k (Act)-{VO (4-5) —V (CELLOUT )}/K (ACT)

In order to improve the measurement accuracy, the VOS (ACT) of each battery voltage should be measured.

0, cell0 1, vmen 1

Set CAL1 0, CAL0 0, CELL1 1, Cell0 0, VMEN 1

Set CAL1 0, CAL0 0, Cell1 1, Cell0 1, VMEN 1

Measure VO (3-4), VO (2-3), VO (1-2), [123 ]

vc4 –vc5 {vo (4-5)}/k (Act)

vc3 –vc4 {vo (3-4)}/k (Act)

vc2 {vo (2-3) --v ( Celtic)}/k (ACT)

vc1 {vo (1-2) -v (cello)}/k (Act)

Cell balance control [ 123]

Unit balanced control allows to control a small bypass path for any series component. The purpose of this bypass path is to reduce the current that enters the battery during the charging, so that the series components can reach the same voltage. The series resistors between the input pins and the nodes of the positive tandem component control the bypass current value. Use the unit to select the position 4 of the register 4 for a single series element selection.

Thermistor Driven Circuit (TOUT)

TOUT pin can drive the thermistor of REG. At 25 ° C, the typical thermistor resistance is 10 kΩ. The default state is to close to save power. The maximum output impedance is 100Ω. TOUT is enabled in a function CTL register (bit 5).

Opening drive circuit (OD)

The leakage output has a 1-MA current source drive, and the maximum output voltage is 25 V. OD output is enabled or disabled by the output control register (bit 4), and the default state is closed.

Salut (Sharete)

When the OL or SC current failure is detected, if the Sleep Pin changes the status or the door -to -door dog failure, Xalert will be driven low. To remove xalert, switch (from 0, set to 1, and then reset to 0) output CTL (bit 0), and then read the status register.

清 lock removal (LTCLR)

When a current limit failure or the door dog timer failure, the state is locked. To remove these faults, switch (from 0, set 1, and then reset to 0) LTCLR in the output CTL register (bit 0).

FIG. 1 is an example of the removal of LTCLR and XALERT after short circuit.

2, 3 or 4 units configuration

In the 3 unit configuration, VC1 pairs of VC2 short circuit. In the 2 unit configuration, VC1 and VC2 are short -circuited to VC3.

Looking at the Dog input (WDI)

When determining the overload and short -circuit delay cycle, you need to use WDI input as a delayed time -time basis and use part of the system monitor.

Initially, the start of the dog monitoring host oscillator was launched; if there was no response from the host in the 700 ms of its minimum operating voltage at the BQ29312A, the BQ29312A closed CHG, DSG and ZVCHG FET.

In this wake -up cycle, once the door was launched, it monitored whether the host had an oscillating state. This state was defined as a cycle of 100 microseconds (typical values), and did not receive in this cycle. Enter the clock. If the oscillator stops, the door dogs close CHG, DSG and ZVCHG FET. When the host clock oscillates, WDF is released, but the sign is locked until the LTCLR is switched.

DSG and CHG FET driver control

BQ29312A driver DSG, CHG and ZVCHG fet off, if the OL or SC security threshold violates the current direction. Only under BQ29312A integrated protection control permit can the host be forced to open or close any FET. DSG and CHG FET driving grid to drain voltage are cut to 15 V (typical values).

When PMS GND, the default state of the CHG and DSG FET drives is closed. The host can control the FET driver by programming the CTL (B3 ... B1). The B1 is used to control the discharge FET, the B2 is used to control the charge FET, and the B3 is used to control the ZVCHG FET. These controls are only effective when they are not initialized. The CHG drive field effect tube can be powered by the component, and the DSG field effect tube can be powered by BAT.

Principles of pre-charging and 0-V charging work

BQ29312A supports both chargers with a pre-charging mode and a charger without a pre-charging mode. Even if the battery voltage drops to 0 volts, BQ29312A supports charging. For details, see the application part.

Sleep control input (Sleep)

Sleep input is pulled inside to REG. When sleep is pulled to REG, BQ29312A enters the sleep mode. The dormant mode will disable all FET outputs, and at the same time, OL, SC and door dog failure will also be disabled. RAM configuration is still effective when exiting sleep mode. The host can also enter the sleep mode through the register control.

Power mode

BQ29312A has three power modes: normal, sleep and shipping. The following table outlines the operation functions in these power modes.

Communication

I2C compatible serial communication provides reading and writing access to the BQ29312A data area. Data pipes timing through separate data and clocks (SCLK). BQ29312A is used as a device and does not produce clock pulse. Provide from the GPIO pin or I2C support port of the host system controller to BQ29312A's communication. The slave address of BQ29312A is 7 digits, with a value of 0100 000 (0x20).

BQ29312A is not compatible with the following functions that are compatible with I2C.

BQ29312A is always considered a machine.

BQ29312A NACK with an invalid register address without returning.

BQ29312A does not support the universal code of the I2C specification, so it will not return ACK.

BQ29312A does not support the increased address automatically, allowing continuous reading and writing.

BQ29312A allows writing data to the same location without sending the position address without sending the position address.

The register mapping

BQ29312A has nine addressable registers. These registers provide status, control and configuration information for the battery protection system.

Status register provides information about the current status of BQ29312A. The read status register will remove the Xalert foot.

Status B0 (SCDSG): This bit indicates a short circuit in the discharge direction.

0 The current is lower than the short -circuit threshold (default value) in the direction of discharge.

1 The short -circuit threshold of the current greater than or equal to the direction of discharge.

Status B1 (SCCHG): This bit indicates a short circuit in the charging direction.

0 The current in the charging direction is lower than the short -circuit threshold (default value).

1 The short -circuit threshold of the current greater than or equal to the charging direction.

Status B2 (OL): This bit means overload.

0 The current is less than or equal to the overload threshold (default value). 1 The current is greater than the overload threshold.

Status B3 (WDF): This bit indicates that the dog failure occurs.

0 32 kHz oscillation is normal (default).

1 32 kHz oscillation stops or has not been started, and the door dog has goneout.

Status B4 (Sleepdet): This bit indicates that BQ29312A is in sleep mode.

0 bq29312a is not in the sleep mode (default). 1 bq29312a is in the sleep mode.

Status B5 (ZVCLMP): This bit means that the ZVCHG output is restrained.

0 ZVCHG pin without clamping (default). 1 zvchg pin is clamped.

The output CTL register controls the output of BQ29312A, which can be used to remove certain states.

Output control B0 (LTCLR): When the current limit failure or the timer fault of the door dog is locked, when switch from 0 to 1 and return to 0 (default value 0), the release fault is released locking.

0 (default) 0- gt; 1- gt; 0 Clear the fault lock

Output control B1 (DSG): This bit controls external discharge FET.

0 discharge FET closed, controlled by the system host (default).

1 discharge FET open, BQ29312A is in normal working mode.

Output control B2 (CHG): This bit controls the external charge field effect tube.

PMS ground

0 The effect of the charge field effect tube is turned off, and the system host is controlled (default).

1 charge field effect tube open, BQ29312A is in normal working mode.

PMS Packaging

0 The effect tube of the charging field is turned off, which is controlled by the system host.

1 Charging FET open, BQ29312A is in normal working mode (default).

Output control B3 (XZVCHG): This bit controls the external ZVCHG field effect tube.

0 ZVCHG FET open, controlled by the system host (default).

1 ZVCHG FET closed, BQ29312A is in normal working mode.

Output control B4 (OD): This bit enables or disables OD output.

0 OD is high impedance (default value). 1 OD output activation (GND).

Status control register control the state of BQ29312A.

Status control B0 (Sleep): This bit is used to enter the sleep power mode.

0 bq29312a exit sleep mode (default). 1 bq29312a enter the sleep mode.

Status control B1 (SHIP): This bit is used to enter the SHIP power mode when the power set voltage is not applied.

0 bq29312a is in normal mode (default).

1 BQ29312A Enter the transport mode when the battery pack voltage is canceled.

Status control B2 (WDDIS): This bit is used to enable or disable the scheduler timer function.

0 Enable clock monitoring (default).

1 Disable clock surveillance.

Note: Be careful when setting WDDIS.For example, when the 32 kHz input fails, overload and short -circuit delay timer will no longer work because they use the same WDI input. If the WDI input clock stops, these currents cannot be protected. WDF should be enabled at any time to obtain the greatest security. If the door dog function is disabled, CHG and DSG FET should be closed.

The function of the function CTL register is enabled and disabled by BQ29312A.

Function CTL B0 (VMEN): This bit is enabled or disabled by battery and battery voltage monitoring functions. 0 Disable voltage monitoring (default). The unit output is pulled down to the GND level. 1 Enable voltage monitoring.

Function CTL B1 (Packout): When VMEN 1, this bit is used to convert Pack into a cell PIN. The battery pack is removed by 25, which is displayed on the battery, which has nothing to do with the battery selection register settings. 0 Disable packaging (default). 1 Enable packaging.

Function CTL B2 (XOL): This bit enables or disabled the current detection function.

0 Enable overload detection (default). 1 Disable overload detection.

Function CTL B3 (XSCC): The short -circuit current detection function enabled or disabled charging.

0 short -circuit current detection in the charging direction (default). 1 Disable short -circuit current detection in charging direction.

Function CTL B4 (XSCD): The short -circuit current detection function enabled or disabled by this bit.

0 short -circuit current detection in the direction of discharge (default). 1 Disable short -circuit current detection in the direction of discharge.

Function CTL B5 (TOUT): The power supply controls the thermistor.

0 Thermistor is turned off (default). 1 The power supply of thermal resistance is opened.

The register determines the unit selection of the operation mode of voltage measurement and conversion, unit balance, and unit voltage monitoring.

Cell_sel B0–b1 (Cell0 – Cell1): These two digits are selected to connect units for voltage measurement conversion.

Cell_sel B2–b3 (CAL1, CAL0): These bit determine the mode of the voltage monitor block.

Cell_sel B4 – B7 (CB0 – CB3): These 4 are selected in series communities that are selected for balanced bypass paths in the community.

Unit selects B4 (CB0): This bit enables or disables the bottom series of the union to balance the charged bypass path.

0 Disable the bottom series of battery flatHealth charging bypass path (default). 1 Enable the bottom series battery to balance the charging bypass path.

Cell Sel B5 (CB1): The CELL BALANCE charge by the second minimum series is enabled or disabled.

0 Disable the balanced charging bypass path (default). 1 Enable the charging pathway to balance the battery.

Select B6 (CB2) in the community: This bit enables or disables the balanced charging pathway path of the second high community.

0 Disable the balanced charging bypass path (default). 1 Enable the charging pathway to balance the battery.

Select B7 (CB3) in the community: This bit enables or disables the upper and high -level districts to balance the charged bypass path.

0 Disable the balanced charging bypass path (default).

1 Enable the charging bypassing the charging by series.

Application information

Principles of pre-charging and 0-V charging work

In order to charge, the charging field effect transistor (CHG -Fet) to generate a current path. When V (BAT) is 0 V and CHG-FET ON, V (battery pack) is as low as the battery voltage. In this case, the power supply voltage of the device is too low and cannot work. This function has three possible configurations, and BQ29312A can be easily configured according to application needs. These three modes are 0-V charge field effect tube mode, public field effect tube mode and pre-charging field effect tube mode.

1.0-V charging FET mode-Use additional FET (ZVCHG-FET) provides a pre-charging current path to maintain the battery pack+voltage level. The host charger should provide a pre -charging function.

2. Public field effect tube mode-not using special pre-charging field effect tube. The charging field effect of the crystal (CHG-FET) is determined to be set to the default opening state. The charger should provide a pre -charging function.

3. Pre-charging FET mode-Use additional leakage (OD) foot driving FET (PCHG-FET) FET provides a pre-charged current path to maintain the battery pack+voltage level. The charger does not provide any pre -charging function.

0-V charge field effect tube mode

In this mode, a special pre-charging current path diameter of ZVCHG-FET needs to be used to maintain appropriate packaging+voltage Level. In this mode, the charger should provide a pre -charging function. Among them, the pre -charging current level is suitable for battery charging below the set level, usually lower than each battery 3V. When the minimum battery voltage rises to this level, the charger will provide a fast charging current.

The circuit diagram of this method is shown in Figure 7, which showsThe additional field effect tube is added parallel with the charge field effect tube (CHG-FET).

In order to pass the 0V or pre-charged current, the ZVCHG-FET must be applied to the proper grid source V (GS). Here, V (PACK) can be represented by v (gs) as follows:

v (package) V (zvchg)+v (gs) (zvchg-ft grid voltage)

[ 123]

In BQ29312A, the initial state is CHG-FET OFF and ZVCHG-FET ON, and the initial V (ZVCHG) is restrained to 3.5V. The charger then applied a constant current and raised the V (PACK) to a pre -charged current that is sufficient to pass through point A. For example, if V (GS) is 2V at this time, V (PACK) is 3.5V+2V 5.5V. At the same time, ZVCHG-FET is used in the MOS saturation area at this time, so that V (DS) is as follows:

V (PACK) V (BAT)+V F+VDS (ZVCHG-FET), of which V (F) 0.7V is the positive voltage of the di-ft back diode, usually 0.7V.

The following procedure is exported: VDS 4.8 伏-伏 (battery)

When the battery is charged, the V (BAT) increases, and the V (ds) voltage decreases to reach its linear range. For example: if the linear area is 0.2V, the state will continue to V (BAT) 4.6V (4.8V-0.2V).

With the further increase of V (BAT), V (PACK) and V (GS) voltage increased. But because ZVCHG-FET is driven by point B in MOS linear zone, VDS remains at 0.2V.

V (PACK) VF+0.2V+V (BAT), where VF 0.7V is the positive voltage of the DSG-FET back diode, usually 0.7V, and the purpose of R (zvchg) is dividing The heat dissipation of ZVCHG-FET and resistors.

ZVCHG pin behavior is shown in Figure 9, where V (ZVCHG) is set to 0V at the beginning.

When V (PACK) exceeds 7V, V (ZVCHG) V (PACK)/2. However, V (ZVCHG) is maintained to limit the voltage between components and ZVCHG to maximum 8V (typical values). This restriction is designed to avoid overvoltage between the gate and the ZVCHG-FET source.

The signal timing is shown in Figure 10. When the pre -charging starts, (v (bat) 0 v) v (pack) is cut to 3.5 V and maintains the power supply voltage operated by the BQ29312A. When V (BAT) When a sufficiently high voltage is reached for BQ29312A, CHG-FET and DSG-FET are connected, and ZVCHG-FET is disconnected.

Although the current path has changed, the same pre -charging current is still applied. When V (BAT) reaches a fast charging voltage (each battery is usually 3 V), the charger will be switched to the fast charging mode.

Ordinary field effect tube

This mode does not require a dedicated pre-charging field effect tube (ZVCHG-FET). When PMS V (package), the charging (CHG-FET) is turned on when the BQ29312A is initialized, allowing 0 V or pre-charging current to flow. The application circuit is shown in Figure 11. In this mode, the charger should provide a pre -charging function. Among them, the pre -charging current level provided by the charger is suitable for charging at a battery below the set level, usually lower than each battery 3 V. When the lowest battery voltage rises above this level, a fast charging current will be generated.

When the charger is connected, the voltage at PMS rises. Once more than 0.7V, CHG output is driven to GND, and GND opens CHG-FET. The charging current flows through the back diode of CHG-FET and DSG-FET. The battery pack voltage is represented by the following square.

Among them, VF 0.7V is the positive voltage of the DSG-FET back diode, usually 0.7V.

When V (PACK) remains above 0.7V, the pre -charged current remains unchanged. When V (battery pack) and V (battery pack) are lower than the BQ29312A power supply voltage, the BQ29312A regulator is in a non -active state, and the host controller does not work. Therefore, during this period, any protection function in the chipset does not work. This state continues to the minimum power supply voltage of V (group) higher than BQ29312A.

When V (BAT) rises and V (PACK) reaches the minimum power supply voltage of BQ29312A, REG outputs activation and provides a 3.3 V (typical) power supply to the host. When the electricity is reached, the CHG pin is changed from GND to a BQ29312A register. In this state, the CHG output level is driven by a clamp circuit to change its voltage level from 0V to 1V. In addition, the main controller is activated and can open DSG-FET.

The disadvantage is that the BQ29312A does not work during the 0-V charging process. The device does not protect the battery or updates the battery information to the computer (now is charging 0 volts).

This configuration has two advantages:

1. The voltage between batteries and battery packs is low. Because the heat loss in the field effect tube is small, it allows higher pre -charged currents, and does not require externalresistance.

2. The charging FET is opened during the pre -charging process. The pre -charged current can be completely controlled by the charger.

The signal of the public field effect tube mode is timed as shown in Figure 12. When the charger is connected, CHG-FET is turned on. When V (BAT) rises and V (PACK) reaches the minimum power supply voltage of BQ29312A, REG output activation, and host controllers begin to work.

When V (Pack) is high enough, the main controller opens DSG-FET. When V (BAT) reaches the level of fast charging, the charger enters the fast chargin