Features

Stable, no output capacitance or any value, TPS736XX series low loss (LDO) linear

or capacitive voltage regulator using a new topology: nmos [123 [123 ]

20V [ 123] Fixed output to 4.3V -1.20V to 5.5V's adjustable output

- Provide customized output

Figure Figure

Fixed voltage type

available voltage

Tube foot allocation

Input the output capacitor with the LDO regulator of NMOS through the transistor of NMOS

Input output capacitors to achieve ultra-low dropout performance. The reverse current-although inserting the capacitor without input-disconnecting the blocked Simulation design practice constraints. These characteristics, plus 0.1 μF to 1 μF low ESR capacitor from low noise input terminals and enable input, making TPS736XX a power supply near the regulator. This will offset REAC-portable application. This regulator homeThe family provides active input sources, improves the transient response, and is widely selected for the fixed output voltage version and noise suppression and ripple suppression. Higher value can be transmitted and published. All versions have calories. If the increase time is large and fast, the capacitor and overcurrent protection may be required, including folding current-expected load transient, or low-rent-restrictions.

A few inches from the power supply.

The figure shows that the TPS736XX does not require the output capacitor fixed voltage model. The figure gives the connection for stability, and the maximum phase margin is used for adjustable output publications (TPS73601). R1 and capacitors. It is the type and value of all the capacitors that can be used. The formula in the figure in the application. The public output voltage of the sample resistance value vin -vout lt; 0.5V and multiple low ESR capacitors is shown in Figure 2. For the same time, when the optimal accuracy is the best accuracy, the parallel combination of R1 and the total ESR is lower than 50NΩF. The total ESR and R2 are about 19kΩ.

Including all parasitic resistors, including capacitor ESR and circuit boards, sockets, and welders.

In most applications, the sum of the capacitor ESR and tracking resistance will meet this requirement.

Output noise

A precise band gap benchmark is used to generate internal reference voltage VREF. This benchmark is the main noise source in TPS736XX, which generates about 32 μVRMS (10Hz to 100kHz) at the benchmark output (NR). The regulator control circuit increases the reference noise with the same gain as the reference voltage, thereby making the noise diagram. The voltage of a fixed voltage typical application circuit regulator is about:

When the external noise reduction capacitor CNR is grounded from NR, the internal internal internal with the noise reduction (NR) is connected in series (NR) The 27kΩ resistor forms a low -pass filter for voltage reference. For CNR 10NF, 10Hz to 100kHz total noise adjustable voltage version five values

This noise reduction effect is displayed as a balanced root noise voltage pair in the typical feature part CNR.

TPS73601 adjustable version has no noise reduction. However, connecting the feedback capacitor CFB from the output end to the FB pin will reduce the output noise and improve the load transient performance.

TPS736XX uses an internal charge pump to generate an internal power supply voltage, which is sufficient to drive a gate with NMOS -powered components higher than VOUT. The charge pump generates a ~ 250 μV switch noise at 4MHz; however, the contribution of the charge pump noise at the regulator output terminal can be ignored for most values of iOut and COUT.

Circuit layout suggestions to improve PSRR and noise performance

In order to improve communication performance, such as PSRR, output noise and transient response, it is recommended to set up circuit boardsThe separate VIN and VOUT ground planes are calculated, and each ground plane is only connected to the GND pins of the device. In addition, the grounding connection of bypass containers should be directly connected to the ground pins of the device.

Internal current limit

TPS736XX internal current limit helps protect the regulator under failure conditions. When the output voltage drops below 0.5V, the folding restrictions can help protect the regulator from being damaged under short -circuit conditions. For the relationship diagram of the output voltage and output voltage, see Figure 11 of the typical feature part.

Turn off

The enable pipe is to be high-level, which is compatible with standard TTL-CMOS levels. When the voltage is lower than 0.5V (maximum value), turn off the regulator and drop the ground pins to about 10NA. When the function is not needed, the pin can be connected to the vehicle recognition number. When using a pull -up resistor and need to work below 1.8V, use a pull -up resistor value below 50KΩ.

Lotal voltage

TPS736XX uses NMOS generals crystal to achieve large -scale changes in load current. TPS736XX needs to drop from VIN to VOUT to avoid reducing transient response. The boundary of this transient leakage area is about twice the DC leakage. Value values higher than this line ensure normal transient response.

The work in the transient leakage area will lead to increased recovery time. The time required to recover from the load is a function of changing the load current rate, the change rate of the load current, and the available clean air (vehicle recognition number to the voltage drop). In the worst case, [VIN-VOUT) is close to the level of DC voltage drop], TPS736XX may require hundreds of microseconds to return to the prescribed adjustment accuracy.

Inspector response

In the voltage follower configuration, the low -opening output impedance provided by NMOS through the component allows the output capacitor operation without using the output capacitor in many applications. Like any regulator, an increase in capacitors (nominal value 1μF) from output pins to grounding will be reduced, but the duration will be increased. In the adjustable version, adding a capacitor CFB, from the output end to the adjustment tube foot, will also improve the transient response.

When the output over -voltage, TPS736XX did not drop off. This allows a higher voltage source (such as spare power supply) to the output application. When the capacitor is connected to the output end, if the load current drops to zero quickly, it will also cause the output to be over -adjusted percent. By increasing the load resistance, the duration of the overrun can be reduced. The rate decays at a rate determined by the output capacitor COUT and the internal and external load resistance. The attenuation rate is given from the following formula:

Inverse flow

NMOS power -power component of TPS736XXWhen being pulled down, it provides inherent protection to prevent the current from flowing from the output of the regulator to input. In order to ensure that all the charge is removed from the grid of the power -powered element, it must be driven by the pins before removing the input voltage. If you don't do this, PASS elements may keep opening due to the charge stored on the gate.

When the enable tube foot is driven low, no bias voltage is required to block the current on any tube foot. Note that reverse current refers to the current flowing from the input pins due to the voltage applied to the output pins. Because the 80kΩ internal resistor division is grounded, an additional current flows into the output pins (see Figure 1 and Figure 2).

For TPS73601, when VFB is higher than the vehicle recognition number 1.0V, the reverse current may flow.

Hot Protection

When the knot temperature rises to about 160 ° C, the heat protection will disable the output to cool the equipment. When the temperature drops to about 140 ° C, the output circuit is enabled again. Depending on the power consumption, thermal resistance, and the environmental temperature, the thermal protection circuit can be opened and closed in circulation. This limits the loss of the regulator to prevent damage due to overheating.

It is expected to have an environmental temperature and the worst case.

The internal protection circuit design of TPS736XX is used to prevent overload. It is not to replace proper heat dissipation. Running TPS736XX continuously to the heat shutdown state will reduce reliability.

Power consumption

For each packaging type, the ability to remove calories from the mold is different, and different considerations are presented in the PCB layout. The PCB area without other components around the device shifted heat from the device to the environmental air. The performance data of JEDEC low K -board and high K board are displayed in the rated value table. Using heavier copper will improve the efficiency of equipment heat dissipation. Adding plating holes in the heat dissipation layer will also improve the heat dissipation effect.

Power consumption depends on the input voltage and load conditions. Power consumption is equal to the output current multiplication of the voltage drop through the output (from VIN to VOUT):

PD (vehicle identification number) output (6) Low input voltage can minimize power consumption.

Packaging Installation