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2022-09-21 17:24:28
ADN2850 is a non -easy loss memory, dual 1024 digital resistor
Features
dual channel, 1024 position resolution; 25 kΩ, 250 kΩ nominal resistor; maximum ± 8%nominal resistor difference error; low temperature coefficient: 35ppm/℃; 2.7 V to 5 v single single single order The power supply or ± 2.5 V dual power supply; the current monitoring can configure the SPI compatible serial interface; the non -easy loss memory storage wiper setting is set with EEMEM settings to refresh the power; permanent memory writing protection; resistance to the storage in EEMEM; user definition The 26 bytes of the information are additional non -loss -loss memory; 1M programming cycle; 100 years of typical data retention.
Application
SONET, SDH, ATM, Gigabit Ethernet, DWDM laser diode driver, light monitoring system; mechanical resistor replacement instrument gain adjustment; programmable filter, delay, time constant; Sensor calibration.
General instructions
ADN2850 is a dual channel, non -easy memory memory, digital control resistance 1024 step resolution, providing maximum low resistance error guarantee to ± 8% Essence This device has the same electronic adjustment function as a mechanical resistor, and has a higher low -temperature coefficient performance with higher resolution, solid reliability and superiority. ADN2850 performs multi -functional programming through serial interface compatible with SPI, allowing 16 operations and adjustment modes, including draft programming, memory storage and recovery, incremental/reduction, ± 6dB/step log adjustment, wiper settings recovery And additional EEMEM, for user -defined information, such as memory data, finding tables or system identification information of other components.
In the scratchpad programming mode, the specific settings can be directly programmed to the RDAC register, which sets the resistor between the terminal W and the terminal B. The settings can be stored in EEMEM and automatically recovered to the RDAC register during the system.
EEMEM content can be dynamically recovered, or EEMEM content can also be protected through external PR flushing and WP functions. In order to simplify programming, you can use an independent or at the same time to move the RDAC wiper upper and lower to move the RDAC wiper, step by step. For the number ± 6 db change in the wiper settings, the left or right displacement command can double or minimize the RDAC wiper settings.
ADN2850 graphics resistance is stored in EEMEM. Therefore, in the recovery mode, the host processor can know the actual full standard resistance. The host can perform appropriate resistance steps by simplifying the opening application and accuracy calibration and tolerance matching applications.
ADN2850 can be used for 5 mm × 5 mm 16 lead frame chip chip -level LFCSP and thin 16 drawing TSSOP. This device guarantees the extended industrial temperature range 40 ° C to+Run at 85 ° C.
In this data table, the term non -loss -loss memory and EEMEM are used, and the term digital resistor and RDAC are used.
Function box diagram
Typical performance features
123]
Test circuit
Operation theory 
It takes about 15 milliseconds to store data to the EEMEM register, and it takes about 2 mAh. During this period, the displacement register is locked to prevent any changes. RDY's foot pulse is low, indicating that the EEMEM memory has been completed. There are 13 addresses, each user -defined data has two bytes, which can be stored from address 2 to EEMEM registers with address 14.
The following description helps to meet the user's programming needs (see Table 8 for details):
0. Do nothing.
1. Restore EEMEM content as RDAC.
2. Set the RDAC settings to EEMEM.
3. Set the RDAC settings or user data to EEMEM.
4. Reduce 6 decibels.
5. All reduced 6 decibels.
6. Step by subtraction.
7. Step by decrease.
8. Reset the EEMEM content to RDAC.
9. Read EEMEM content from SDO.
10. Read the RDAC wiper setting from SDO.
11. Write the data into RDAC.
12. Add 6 decibels.
13. All 6 decibels are added.
14. Increased step.
15.Essence
Table 14 to Table 20 provides a programming example of some of the commands.
Scratchpad and EEMEM programming
The RDAC register of the draft line directly controls the position of the digital resistance wiper. For example, when the draft register loads all 0, the wiper is connected to the terminal B of the variable resistor. The ScratchPad register is a standard logic register that does not limit the number of changes allowable, but the EEMEM register has a programming/writing cycle limit.
Basic operation
Set the basic mode of the position of the variable resistance wiper position (programming the draft register) is to load the string of data loading string by using instructions 11 (0xb), address 0, and the position data of the needed wiper position. The line data input register is completed. When determining the correct wiper position, the user can use instruction 2 (0x2) to load serial data input register, which stores the wiper position data in the EEMEM register. After 15 milliseconds, the wiper position is permanently stored in non -easy -to -loss memory.
Table 6 provides a programming example that lists the order of serial data input (SDI). The serial data output appears on the SDO pin in the SCO format.
When the system is powered on, the ScratchPad register will automatically refresh the value that was previously stored in the corresponding EEMEM register. The preset EEMEM value of the factory is medium scale. ScratchPad registers can also be refreshed in three different ways in three different ways. First, execute instructions 1 (0x1) to restore the corresponding EEMEM value. Secondly, execute instructions 8 (0x8) to reset the EEMEM value of two channels. Finally, the pulse public relations refresh the two EEMEM settings. Operating hardware control PR function requires a complete pulse signal. When the PR becomes lower, the internal logic sets the wiper to medium scale. It was not until PR returned to high before loading the EEMEM value. 
Writing protection (WP) foot prohibits any changes to the contents of the draft register. Except for EEMEM settings, the settings can still use instructions 1. Directive 8 and PR pulse recovery. Therefore, WP can be used to provide hardware EEMEM protection characteristics.
Digital input and output configuration
All digital inputs have ESD protection, high input impedance, and can be driven directly from most digital sources. Activate when logic is low. If PR and WP are not used, they must be bound to VDD. There is no internal pull -up resistor on any digital input pin. In order to avoid floating numbers' feet in the noise environment, it may cause error triggers, and the pull -pulling resistance is added. This is applicable when the device is separated from the driver source when programming.
SDO and RDY tube feet are leaking digital outputIf you use these functions, you only need to pull the resistor. To optimize the speed and power balance, use 2.2 kΩ to pull the resistor.
Equivalent serial data input and output logic are shown in Figure 25. When the chip selection (CS) is in a logical high -electricity, the SDO of the leakage output is disabled. The ESD protection of the digital input is shown in Figure 26 and Figure 27.
ADN2850 contains a 4 -line SPI compatible digital interface (SDI, SDO, CS and, and CLK). MSB must be loaded with 24 -bit serial data first. The format of the word is shown in Table 7. The command position (C0 to C3) controls the operation of the digital resistor according to the command shown in Table 8. A0 to A3 is the address position. A0 is used to handle RDAC1 or RDAC2. Users can access address 2 to address 14 to get additional EEMEM. Address 15 Keep it to the factory. Table 10 provides an address chart of the EEMEM position. D0 to D9 is the value of the RDAC register. D0 to D15 is the value of the EEMEM register.
ADN2850 has an internal counter, which counts the multiple of the 24 -bit (one frame) to ensure normal work. For example, ADN2850 can work with 24 -bit or 48 -bit words, but cannot work normally with 23 or 25 characters. In order to prevent data error lock (for example, due to noise), when CS becomes high, if the count is not a multiple of 4, the counter is reset, but if the count is a multiple of 4, the counter is still retained in the register. In addition, the ADN2850 also has a delicate feature, that is, if CS pulses without CLK and SDI, the component will repeat the previous command (except for the power period). Therefore, we must pay attention to ensure that there is no excessive noise in the CLK or CS row that may change the validity digital mode.
The SPI interface can be used for two types: CPHA 1, CPOL 1 and CPHA 0, CPOL 0. CPHA and CPOL refers to the timing control of SPI in the following micro converters and microprocessors: ADUC812, ADUC824, M68HC11, MC68HC16R1, and MC68HC916R1.
The operation of the chrysanthemum chain
The serial data output pin (SDO) has two purposes. It can be used to use instruction 10 and instruction 9 to read the wiper settings and EEMEM values. The remaining instructions (instructions 0 to instruction 8, instruction 11 to instruction 15) are valid for the chrysanthemum chain of multiple devices at the same time. The chrysanthemum chain minimizes the number of port feet required by IC (see Figure 28). The SDO pin contains a leakage N-CH FET. If this function is used, a pull-up resistor is required. As shown in Figure 28, users need to put a bag SDOPIN is bound to the SDI PIN of the next package. Users may need to increase the clock cycle because the pull -up resistance and capacitance load at the SDO to the SDI interface may need to be delayed between subsequent devices.
When the two ADN2850 devices are connected to the chrysanthemum chain, 48 -bit data is needed. The first 24 -bit (formatted 4 -bit command, 4 -bit address, and 16 -bit data) is transferred to U2, and the latter 24 -bit uses the same format to U1. Keep CS low until all 48 bits enter their respective serial registers. Then pull the CS to raise the operation.
Terminal voltage operating range
The positive V and negative V power supply of ADN2850 define the boundary conditions for the normal operation of the 2 -terminal digital resistor. The power signal that appears on the wiring end B and the wiring end W is restrained by the internal positive bias diode (see Figure 29).
The GND pin of ADN2850 is mainly used for digital grounding reference. In order to minimize digital ground bounces, the ADN2850 grounded terminal should be remotely connected to public ground (see Figure 30). The digital input control signal of ADN2850 must refer to the device ground pins (GND), and must meet the logic level defined in the specification chapter. The internal level shift circuit ensures that the co -mode voltage range of the three terminals extends from V to V, regardless of the digital input level.
The order of power -on
Since the voltage compliance at the diode restricted terminal B and terminal W (see Figure 29), before applying any voltage to the terminal B and terminal W, it must be necessary to apply any voltage, it must be necessary to apply any voltage, it must be necessary to apply any voltage. Power on V and V first. Otherwise, the diode is positive bias, which makes V and V inadvertently power. For example, before V, a 5 V voltage on the terminal W and terminal B will cause the V terminal to appear 4.3 V.
But it may affect other parts of the user system. The ideal sequence of electricity is GND, V and V, digital input, V and V. As long as V, V, and V, the power sequence of V, V and digital input is not important.
Regardless of the power supply sequence and slope rate of the power supply, when V and V are powered on, the preset activation is activated, and the EEMEM value is restored to the RDAC register.
Layout and power bypass
The tight and minimum layout design is a good practice. The wire of the input terminal should be as direct as possible, and the wire length should be the smallest. The grounding path should have low resistance and low inductance.
Similarly, in order to obtain the best stability, it is best to use high -quality capacitors to bypass the power. The bypass power supply device with 0.01 μF to 0.1 μF disk or chip ceramic capacitor. In addition, low ESR, 1 μF to 10 μF 钽 or electrolytic capacitors are used at the power supply to minimize any transient interference (see Figure 30).
In Table 7, the command position is C0 to C3, the address bit is A0 to A3, the data bit D0 to D9 is suitable for RDAC, D0 to D15 is suitable for EEMEM.
command instruction code see Table 8.
1. SDO output shifted the last 24 -bit data to the serial register for the chrysanthemum chain operation. Abnormal: For any instructions after instruction 9 or instruction 10, the selected internal register data appears in data byte 0 and data byte 1. The instructions after instruction 9 and instruction 10 must also be a complete 24 -bit data word, with the content of the serial register of the full clock output. 2. The RDAC register is a easily lost draft register, which is refreshed from the corresponding non -easy -to -sex EEMEM register during power.
3. When CS selects the Loguer to return the logic high -electricity, these operations are performed.
4. Instruction 3 Write two data bytes (16 -bit data) into EEMEM. In the case of address 0 and address 1, only the last 10 bits are valid for the wiper position.
5. Increased, decreasing, and shift instructions ignore the contents of the displacement register, data byte 0 and data byte 1.
Advanced control mode
ADN2850 digital resistors include a set of user programming functions to solve the widespread application of these general -purpose adjustment devices. Main programming functions include:
Draft program programming to any expectation value
EEMEM registers in the draft RDAC register value of the RDAC register value
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[123] RDAC wiper registers increasing and decreasing instructions
RDAC wiper register left and right displacement to achieve the level of ± 6 dB
# 8226; 26 users with additional bytes can address non -easy -to -loss memory
Linear increasing and decreasing instructions
Instructions increase and decrease in instructions (instructions 14, instruction 15, instruction 6 and instruction 7 ) It is very useful for linear step adjustment applications. These commands simplify the software encoding of microcontroller by allowing the controller to only send an incremental or reduction command to the device. Adjustment can be separate, or a combination of resistance device, and the position of the two wiper is changed at the same time.
For an incremental command, execution instructions 14 will automatically move the wiper to the next resistance section. The main increase command, instruction 15, move all the resistance waterwater in one position up.
Adjust the digital taper mode
Four programming instructions through a separate resistor or two water scraping positions at the same time to generate the position control of the water scratcher position control at the same timeIncrease and reduce the number of cones. 6DB increments are activated by instruction 12 and instruction 13, 6DB reduction is activated by instruction 4 and instruction 5. For example, starting with a wiper connected to terminal B, the 11 -year increase instructions (command instruction 12) Move the wiper from 0%of the R (terminal B) position of the ADN2850 10 -bit resistor at the R (terminal B) position of the ADN2850 100%. When the wiper position is close to the maximum settings, the last 6DB incremental instructions make the wiper to the full marked 1023 code position. When each incremental instruction is added with another 6 decibels, the wiper position will not exceed its full scale (see Table 9).
6DB step incremental and 6DB step increments are implemented through the inside or right to right, respectively. The following information explains the non -ideal ± 6DB adjustment adjustment under certain conditions. Table 9 shows the operation of the shift function of the RDAC register data bit. Each table shows a continuous displacement operation. Note that the left shift 12 and 13 instructions are modified, so that if the data in the RDAC register is equal to zero and the data is shifted, the RDAC register is set to code 1. Similarly, if the data in the RDAC register is greater than or equal to the medium scale, and the data is moved left, the data in the RDAC register will automatically set to a full scale. This allows the left -move function to be used as a pair adjustment as much as possible.
Only when the LSB is 0 (the ideal pair no error), the right shift 4 instructions and the right shift 5 instructions are ideal. If LSB is 1, the right shift function generates a linear semi -LSB error, which is converted into a number of numbers related to bit, as shown in Figure 31. FIG. 31 shows the odd digit number of ADN2850.
For each right shift 4 command and right shift 5 command execution, the actual consistency of the data content between the RDAC register and the position of the wiper position is only the actual consistency of the digital curve is only the only curve. Error containing strange digital positions. The even digit is ideal. FIG. 31 shows the log error (20 × log10 (error/code)) of ADN2850. For example, code3 log error 20 × log10 (0.5/3) -15.56 dB, which is the worst situation. The log error chart is more important at lower code (see Figure 31).
Another subtle feature of the previous command
ADN2850 is that the subsequent CS selection, without clocks and data, repeat the previous previous previous, repeat the previous previous previous previous The command.
Using additional internal non -loss EEMEM
ADN2850 contains additional user EEMEM registers to store any 16 -bit data, such as memory data, finding tables or system logo information of other components, such as other components. Essence Table 10 provides the address chart of the internal storage register shown in the function box (see Figure 1), that is, EEMEM1, EEMEM2 and user EEMEM's 26 bytes (13 addresses × 2 bytes of each address). 
1. RDAC data stored in the EEMEM position is transmitted to the corresponding power -on or instructions or instructions 1. Directive 8 and PR are executed.
2. Userx is an internal non -loss EEMEM register, which can be used to store and use instructions 3 and instruction 9, respectively.
3. Read only.
Calculate the actual end -to -end resistance
The resistance tolerance is stored in the EEMEM register during the factory test. Therefore, the actual end -to -end resistance can be calculated, which is valuable for calibration, tolerance matching and precision applications. Note that this value is read only. The R AT full marker match at the full label, usually 0.1%.
The percentage of the resistance tolerance is included in the last 16 -bit data of EEMEM register 15. The format is a dual -proof format of the symbol size, where the MSB specifies the symbol (0 negative number, 1 positive number), the next 7 MSB specifies an integer, and 8 LSB specifies the decimal number (see Table 12). 
For example, if R 250 kΩ, and the data in SDO is displayed as xxxx xxxx 1001 110000 0000 1111, you can calculate the RAT full marker as follows: [123 123 ]
the highest effective position: 1 ZhengNext 7 lsb: 001 1100 28
8 LSB: 0000 1111 15 × 2 0.06%tolerance 28.06%-8 #61623;
Therefore, the full standard R 320.15 kΩ
RDAC structure
RDAC contains multiple string more Equal resistance sections with a set of simulation switches for wiper connections. The number of positions is the resolution of the device. The ADN2850 has 1024 connection points, which can provide more than 0.1%settings resolution. Figure 32 shows the equivalent structure between the three RDAC terminals. SW is always open, and each time the SW (0) to the SW (2-1) switch is turned on, it depends on the resistance position of the data bit decoding. Because the switch is not ideal, there is a 30Ω wiper resistor, R. The wiper resistor is a function of the power supply voltage and temperature. The lower the power supply voltage or the higher the temperature, the higher the wiper resistance generated. If the output resistance is required, the user should understand the wiper resistance dynamic.
Variable resistance programming
The nominal resistor terminal B, RWB of the terminal W and the terminal B, RWB, with 25 kΩ and 250 kΩ has 1024 positions (10 -bit resolution). The last digits of the part number determine the nominal resistance value, for example, 25 kΩ 24.4Ω; 250 kΩ 244Ω.
Decoding the 10 -bit data words in the RDAC memory to select one of the 1024 possible settings. The following description provides calculation of the resistance RWB under different code of 25 kΩ components. The first connection of the wiper starts with the terminal B with data 0x000. Due to the wiper resistor, RWB (0) is 30Ω and has nothing to do with the nominal resistor. The second connection is the first tap point, and the RWB (1) of the data 0x001 becomes 24.4Ω+30Ω 54.4Ω. The third connection is the next tap point, indicating that the RWB (2) of the data 0x002 48.8Ω+30Ω 78.8Ω, which is pushed according to this. Every time a LSB data value is added, the wiper will move up the resistance ladder until RWB (1023) 25006Ω to reach the last part of the connection point. The simplified picture of the equivalent RDAC circuit is shown in Figure 32.
The general formula for determining the programming output resistance between the terminal BX and the terminal WX is:
where: D is the The decimal equivalent of data contained in RDAC.
RWB_NOM is the nominal resistance value
RW is a wiper resistor.
Note that under zero -scale conditions, a limited wiper resistor with 30Ω exists. It should be noted that the current between W and B in this state is limited to no more than 20 mAh to avoid internal switching degradation or possible damage. In the same packaging, the typical distribution of RWB-NOM in different channels is ± 0.2%. The matching of the device to the device depends on the worst situation of the change of ± 30%. However, RWB has a temperature coefficient of 35 ppm/℃ with the temperature changes at full standard.
Programming Example
The programming example below demonstrates the typical event sequence of various characteristics of ADN2850. See Table 8 in the description and data font format. The instruction numbers, addresses and data appearing at the foot of SDI and SDO tube adopt the hexadecimal format.
The EEMEM value of RDAC can be recovered by power -on, tapped PR pins or two commands shown in Table 16.
Analog devices, inc. Provide a user-friendly Eval. -ADN2850SDZ evaluation tool package, PC can be combined with control and digital signal processor platform. The driver is self -contained; no need toProgramming language or skills.
Application information
gain control compensation
Digital resistors are usually used for gain control, as shown in Figure 34.
Depending on the different GBP of the computing amplifier, reducing the feedback resistance may extend the frequency of zero to the degree that is sufficient to overcome the problem. A better way is to compensate the capacitor C2 to eliminate the effects of C1. When R1 × C1 R2 × C2, the best compensation occurs. This is not an option, because R2 changes. Therefore, the previous relationship and proportion C2 can be used, just like R2 is at its maximum value. When R2 is set to a low value, this may be excessive compensation and damage performance.
Or, it can avoid bells or oscillation in the worst case. For key applications, find C2 according to experience to adapt to oscillation. Generally speaking, C2 is usually enough to compensate within the range of a few pickups to a few -tenths of pickups.
Similarly, W and A -end capacitors are connected to the output terminal (not shown); they have a small impact on the node and can avoid compensation in most cases.
Programmable low -pass filter
In the modulus conversion (ADC), it usually includes anti -hybrid filter to restrict the frequency band of the sampling signal. Therefore, dual -channel ADN2850 can be used to construct a second -order Sallen key low -pass filter, as shown in Figure 35.
First, users should choose a convenient value for capacitors. In order to obtain the maximum flat bandwidth, the Q 0.707 is twice the size of the C2 of the C2, so that the R1 is equal to R2. As a result, users can adjust R1 and R2 simultaneously to the same settings to obtain the required bandwidth.
Programmable oscillator
In the classic Wien Bridge oscillator, Wien Network (R | C, R #39; C #39;) provides positive feedback, while R1 and R2 Provide negative feedback (see Figure 36).
At the resonant frequency FO, the total phase movement is zero, and the positive feedback makes the circuit oscillation. When R R #39;, C C #39;, R2 R2A/(R2B+RDIODE), the oscillating frequency is:
where R is equal to RWA, where R Wa is equal to RWA, where RWA is equal to RWA, and RWA is equal to RWA, where RWA is equal to RWA. Therefore: 
When resonance, set R2/R1 2 balanced bridge. In fact, R2/R1 should be set to slightly greater than 2 to ensure that the oscillating can be started. On the other hand, the alternation of diode D1 and D2 ensures that R2/R1 is less than 2, and instantly oscillates stable. 
VO, ID, and VD are mutually dependent variables. By choosing the R2B appropriately, the balance of VO convergence is achieved. R2B can connect with discrete resistance in series to increase the amplitude, but the total resistance cannot be saturated. 
Use ADN2841 to calibrate the optical transmitter
ADN2850 and the multi -rate 2.7Gbps laser diode driver ADN2841 to form an optical monitoring system. In this system, dual digital resistors can be used to set up laser average light Power and anti -light ratio (see Figure 37). The ADN2850 has the characteristics of high resolution and high temperature coefficient, which is especially