BYD6456_AFN4924WS8RG Introduction

The above is the specification of the power mos tube NCE80H12. The power mos tube NCE80H12 used in our electric vehicle controller is actually different from the low-power mos structure in the usual cmos integrated circuit.

The power mos used on electric vehicles is a three-dimensional structure. The mos tube we have seen is actually composed of thousands of small mos tubes in parallel. You may think that one or a few bad moss should easily appear in thousands of small mos. In fact, it is not that easy. , the current manufacturing process basically guarantees the high consistency of various parameters of these small units. Low-power mos is a planar structure.

BYD6456_AFN4924WS8RG

APM9926AKC-TRL

BYP31538 BYP31510 BYP31575 BYH31574 BYD31523A BYH31532 BYM31580 BYH31519 BYS31535 BYM31545 .

NCE30H11K NCE3402B NCE30H10AK NCE2304 NCE3404.

There are three parasitic capacitance parameters in the MOS tube specification, namely: input capacitance Ciss, output capacitance Coss, and reverse transfer capacitance Crss. What do the three capacitance parameters represent in the body of the tube? How did it form? .

. The conductive channel of the MOS tube can be formed during the production process or by turning on an external power supply. When the gate voltage is equal to zero, there is a channel (that is, formed during production), which is called depletion mode. When an external voltage is applied The one that forms the channel later is called the enhancement type.

BYD6456_AFN4924WS8RG

DMN4034SSD

The parasitic capacitance structure of the MOS tube is as follows. Among them, the width of polysilicon, the width of the channel and the trench, the thickness of the G oxide layer, and the doping profile of the PN junction are all factors that affect the parasitic capacitance. .

BYM8615 BYH8638 BYN8610A BYM8628 BYN8222 BYM31020 BYS31010 BYJ3104 BYH3105 BYP3109.

NCE3020K NCE3025Q NCE3035K NCE3025G NCE3030K.

The N-channel enhancement mode MOS transistor uses a low-doped P-type semiconductor as the substrate, and forms two heavily doped N+ regions on the substrate by a dispersed method, and then generates a very thin one on the P-type semiconductor. A silicon dioxide insulating layer, and then photolithography is used to etch away the silicon dioxide layer on the upper end of the two heavily doped N+ regions, exposing the N+ regions, and finally on the outer surface of the two N+ regions and the two between them. The surface of silicon oxide is sprayed with a layer of metal film by evaporation or sputtering. These three metal films constitute the three electrodes of the MOS tube, which are called source (S), gate (G) and drain (D) respectively. .

BYD6456_AFN4924WS8RG

NCE25TD120WT NCE25TD120VT NCE15TD120LT NCE25TD120LT NCE40TD135LT.

NCE2302C NCE8205t NCE2004Y NCE2006Y NCE2007NS.

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