Features

Low -power consumption octa -in -making modulus converter; four 16 -bit DAC; four 12 -bit DAC; 14 guide/16 guide TSSOP; 1.25 V/2.5 V, 5 ppm/℃ benchmark benchmark. ; At 5 volts, the power supply dropped to 400 mAh, and at 3 volts, the power supply dropped to 200 mA; 2.7 V to 5.5 V power supply; the design guarantee monotonicity and reset to zero scale; 3 power -off function; hardware LDAC; And LDAC super control function; CLR function to programmable code; rail -to -track running.

Application

process control; data collection system; portable battery power supply instrument; digital gain and offset adjustment; programmable voltage current source; programmable attenuation.

General description

AD5678 is a low -power, octagonal, buffer voltage output DAC. There are four 12 -bit DACs and four 16 -bit in a single package. DAC. All equipment runs under a single 2.7 V to 5.5 V power supply, and it is monotonous by design.

AD5678 has an internal internal benchmark with internal gain of 2.

The reference voltage of AD5678-1 is 1.25 V 5 ppm/℃, and the full scale output is 2.5 V; the reference voltage of AD5678-2 is 2.5 V 5 PPM/℃, and the full scale output is 5 V. The car reference voltage is turned off when power is powered, allowing external reference voltage. Internal reference is enabled by software.

This section includes a power -on reset circuit to ensure that the DAC output power is as high as 0V and keeps power on the level until it is effectively written. This part contains a power -off function that reduces the current consumption of the device to 400NA at 5V, and provides a software selected output load channel when any or all DAC is in the power off mode.

You can use the LDAC function to update the output of all DACs at the same time, and add the function of the DAC channel to select the DAC channel to update simultaneously. There is also an asynchronous CLR that removes all DACs as a software -opted code -0 V, medium or full scale.

AD5678 uses multi -functional 3 -line serial interface, which can work at a clock frequency of 50 MHz, and compatible with standard SPI and QSPI Signal processor interface standard. The precision output amplifier on the film realizes rail pairing output amplitude.

Product Highlights

1. Octobic digital module converter (four 12 -bit digital modulus converters and four 16 -digit module converters).

2. 1.25 V/2.5 V on the film, 5 ppm/℃ benchmark.

3. Provide 14 -guide/16 -guide TSSOP.

4. Reset off at 0 V.

5. Power off power. During power off, DAC usually consumes 200 mAh at 3 volts and consumes 400 mAh at 5 volts.

timing characteristics

All input signals are specified in TR TF 1 ns/v (10%to 90%V), and (v v The voltage level of +v)/2 starts time. See Figure 2. V 2.7 V to 5.5 V. Unless otherwise explained, all specifications T to T.

Typical performance features

]

The term

Relators

For DAC, relative accuracy or integral non -linearity (INL) is Measure the maximum deviation of the straight line of the end point through the DAC through the DAC. Figures 5, Figure 7, and 9 show the relationship diagram of typical INL and code.

Differential non -linearity

Differential non -linear (DNL) is the difference between the measurement changes of any two adjacent codes and the ideal 1LSB change. The maximum specified value is ± 1 LSB, and the differential non -linearity ensures monotonicity. The design guarantees the monotonicity of the DAC. Figure 6, Figure 8, and 10 show the relationship diagram of typical DNL and code.

The offset error

The offset error is the difference between the measurement of the actual voltage and the ideal voltage, and it is represented by the millivoltory in the linear area of the transmission function. Measure the offset error on the AD5678 and load the code 512 into the DAC register. It can be negative or positive, indicated in the hecy.

Zero Code Error

Zero code error is to load zero code (0x0000) to the DAC register to output error. Ideally, the output should be 0 V. Since the output of DAC cannot be lower than 0 V, the zero -code error in AD5678 is always positive. This is caused by the combination of offset errors in DAC and output amplifier. Zero code is represented by the millivck.

FIG. 18 shows a typical zero code error VS.

Temperature.

gain error

The gain error is a measuring the DAC span error. It is the slope deviation between the DAC transmission characteristics and the ideal value, indicating the percentage of the full marking range.

Zero -code error drift

Zero -yard error drift is a way to measure zero -code error with temperature changes. It is represented by μV/℃.

gain error drift

IncreaseError error drift is a method of changing the amount of gain error with temperature. Represented by (full range of PPM)/℃.

Full marking error

The full marking error is the measuring error of the output error when the full marking code (0xffff) is loaded to the DAC register. Ideally, the output should be V-1 LSB. The full marking error is expressed as a percentage of the full marking range. FIG. 17 shows a diagram of a typical full standard error and temperature.

Digital mold fault pulse

Digital mold fault pulse is to inject the pulse of analog output when the input code in the DAC register is changed. It is usually specified as a faulty area in NV-S, and the digital input code is measured when the digital input code is changed by 1LSB when the primary advancement conversion (0x7fff to 0x8000) is measured. See Figure 34.

DC power suppression ratio (PSRR)

PSRR indicates how the output of DAC is affected by the change of power voltage. PSRR is the ratio of V changes to V changes to V of DAC's full marking. It is based on decibels. V is kept at 2V and V changes ± 10%.

DC string disturbance

DC disturbance is a DC change that occurs with changes in the output of another DAC. It is measured by the full standard output of one DAC (or the soft power supply), while monitoring another DAC. It is expressed by slightly.

DC disturbance caused by changes in load current is a method that measures the effect of changing load current on one DAC on another DAC that keeps at medium -scale DAC. It is expressed by slightly perh.

Reference Five

Reference feed refers to the signal amplitude amplitude of the DAC output place when the DAC output is not updated (that is, LDAC high). It is expressed in decibels.

Channel isolation

The ratio of the output signal of the channel to the channel is the amplitude of the output signal of one DAC to the reference of another DAC. It is based on decibels.

Digital feedback

Digital feedback is the pulse measurement of the DAC simulation output from the digital input pins of the device, but measured when DAC was not written (synchronized at a high level). It is specified in NV-S and measured through the full marker changes on the digital input pins, that is, from 0 to 1 or from 0 to 1.

Digital string disturbance

Digital string disturbance is the full standard code change in the input register in the other DAC DAC output fault pulse. It measures in independent mode and is represented by NV-S.

Analog string disturbance

The simulation string is transferred to the output of a DAC output due to the output change of another DACFailure pulses. It is measured by loading a full -scale input register. With the LDAC, code changes (all 0s to all 1s, vice versa), then the pulse LDAC is low, and monitor its digital code that has not changed DAC DAC Output. NV-S is represented by NV-S.

DAC to DAC string disturbance

DAC-to-DAC string disturbance was transferred to the fault pulse of the output of the DAC due to the change of the digital code change of one DAC and the subsequent output change of the other DAC. This includes numbers and simulation string disturbances. It is a low LDAC and monitoring the output of another DAC by loading one of the DACs for a full -size code change (all 0s to all 1s or opposite). Failure energy is represented by NV-S.

Double bandwidth

The amplifier in DAC has limited bandwidth. The double -increase bandwidth is a measure of measurement. In the output, a sine wave (load the full marking code to DAC) will appear in the output. The frequency bandwidth is the frequency of the output amplitude below the input of 3DB.

Total harmonic distortion (THD)

Total harmonic distortion is really the difference between the ideal sine wave and the attenuation of sine waves using DAC. The sine wave is used as a reference of DAC. THD is the measurement of DAC output harmonic. It is based on decibels.

Operation theory

D/A Section

AD5678 DAC is made of CMOS process. This structure consists of a series of DAC and an output buffer. These components include internal 1.25 V/2.5 V, 5 ppm/℃ benchmark, and the internal gain is 2. Figure 45 shows the frame diagram of the DAC architecture.

Because the input coding of DAC is direct binary, the ideal output voltage during external reference is:

] The ideal output voltage of the internal base is:

where: d load to the DAC register.

AD5678 DAC C, D, E, F (12 digits) is 0 to 4095.

AD5678 DAC A, B, G, H (16 -bit) is 0 to 65535.

n DAC resolution.

resistance string

The resistance string section is shown in Figure 46. It is just a resistor, each resistance value is R. The code loaded to the DAC register determines which node tap of the voltage from the string into the output amplifier. By turning off a switch to connect to the amplifier to cut the voltage. Because it is a string of resistors, it is guaranteed to be monotonous.

Internal reference

AD5678 has the internal internal benchmark with an internal gain of 2. The reference voltage of AD5678-1 is 1.25 V 5 PPM/℃, and the output of the full margin is 2.5 V. The reference voltage of AD5678-2 is 2.5 V 5 PPM/℃, and the output of the full margin is 5 V. The reference voltage of the vehicle is turned off when power is powered, allowing an external reference voltage. Internal references are enabled by writing control registers. See Table 7.

The internal reference associated with each part is available in V sales. If the output is used to drive the external load, the buffer needs to be needed. When using internal benchmarks, it is recommended to place a 100 NF capacitor between the benchmark output and GND to maintain the benchmark stability. When re -cutting and using internal references, a single channel is not supported.

Output amplifier

The output buffer amplifier can generate rail voltage at the output end, and its output range is 0 V to V. The amplifier can drive a 2 kΩ load and connect with 1000 PF to GND. The source and exchange capacity of the output amplifier is shown in Figure 24 and Figure 25. The rotation rate is 1.5V/μs, the stability time of the range is 10 μs, and the range is 1/4 to 3/4.

Serial interface

AD5678 has a 3 -line serial interface (synchronous, SCLK and SPI, QSPI and Microwire interface standards, as well 2.

Low the synchronization line at the beginning of the sequence. The data from the data cable is recorded in the 32 -bit displacement register on the bottom of the SCLK. High -speed DSP compatibility. On the edge of the 32 -decrease clock, the last data bit is timely and performs programming functions, that is, changes in the content of the DAC register and/or mode changes. At this stage, the synchronization line can be kept at a low or high. In these two cases, it is necessary to raise it at least 15 ns before the next writing sequence, so that the next -to -be -written sequence can be activated. Compared with V 0.8V, SYNC should be in a low -altitude and leisure state in a low -power part of the sequence. Improve synchronization.

Input displacement register

The input shift register is 32 bits. The first four are not important. The next four are the command position C3 to C0 (see Table 7), followed by 4 digit DAC address bits A3 to A0 (see Table 8), and finally 16/12 digit datawords. The dataword consists of 16/12 bits of input code, followed by 4 digits of 4 digits, respectively Or 8 -bit, and AD5678 DAC A, B, G, H and AD5678 DAC C, D, E, F is not related (see Figures 47 and Figure 48). These data bits are transmitted to the DAC register on the 32nd decrease of SCLK.

Synchronous interrupt

In the normal writing sequence, the synchronization line is kept low in the 32 decrease edges of SCLK, and the DAC is updated on the 32 decrease edge and rising edge of the synchronous. However, if the 32nd decline will be raised before, this will act as the interruption of the sequence. The displacement register is reset and the writing sequence is considered invalid. The update and operation mode of the DAC register content have not occurred, as shown in Figure 49.

Internal reference register

By default, the car reference is closed when booting. This allows external references when the application needs. By setting the level DB0 high or low (see Table 9), the user's internal reference register can open/close the car reference. The command 1000 retains the command to set the internal REF (see Table 7). Table 11 shows the state of the bit in the input shift register corresponds to the operating mode of the device.

Powering reset

AD5678 contains the power -on reset circuit and control the output voltage during the power -on period. The AD5678 output power is as high as 0V, and the output remains at the level before the DAC is effectively written into the sequence. This is very useful in the application, because it is very important to understand the state of its output in the DAC power -power process.

There is also a software executable reset function for resetting the DAC of the power -on reset code. See Table 7 if the 0111 command is retained. Any event on LDAC or CLR during the period of power -on reset is ignored.

Power off mode

AD5678 contains four independent operating modes. Command 0100 is retained for the power -off function. See Table 7. These modes are programmed by setting up two bits DB9 and DB8 in the control register.

Table 11 shows how the status of the bit corresponds to the operation mode of the device. By setting the corresponding 8 -bit (DB7 to DB0) to 1, any or all DAC (DAC H to DAC A) can be disconnected to the selected mode. See the content of the input shift register when the power failure/power failure is shown in Table 12-uplink operation. When using internal reference, only the power supply of all channels is supported to the selected mode.

When both bits are set to 0, the component works normally when 5 V, and its normal power consumption is 1.3 mAh. However, for the three types of power -off mode, the power supply is reduced to 400 mAh at 5 V (200 mAh at 3 V). Not only the power supply decreases, but also the output stage also switches from the output of the amplifier to the known resistance network. This advantage is that when the part is in the power off mode, the output impedance of the part is known. There are threeMove different options. The output is connected to the GND through the 1kΩ or 100kΩ resistor, or keeps the road (three -state). The output level is shown in Figure 50.

When the power shutdown mode is activated, the bias generator, output amplifier, resistance strings and other related linear circuits selected by the selected DAC are closed. However, the content of the DAC register is not affected during power off. For V 5V and V 3V, the time to exit power is usually 5 μs, as shown in Figure 33.

By setting PD1 and PD0 to 0 (normal operation), you can power on any combination of DAC. The value of the output to the input register (low LDAC) or the value (LDAC high) in the DAC register before the electrociation is.

Clear code register

AD5678 has an asynchronous hardware CLR pins to clear the input. The CLR input is sensitive to the decline. Bring the data of the CLR low -clearing input register and the DAC register to the data contained in the CLR register that can be configured by the user, and set the analog output accordingly. This function can be used for system calibration and loads zero scale, medium scale or full scale to all channels. These removal code values are in the CLR control registers by setting up two digits (bit DB1 and position) programmable DB0. See Table 13. Set the 0 V output by default. The command 0101 is retained to load the clear code register, see Table 7. Write this part next. If the CLR is activated during the writing sequence, the writing will be suspended.

When the output starts, the CLR pulse activation time of the decrease of the CLR is usually 280ns. However, if the value is online, 520ns is usually executed by the CLR to start changing the output. See Figure 43.

During the operation of the removal code register, the contents of the input shift register are shown in Table 14.

LDAC function

The output of all DACs can be updated with the hardware LDAC pin.

Synchronous LDAC: After reading new data, the DAC register is updated on the alongs of the 32 SCLK pulse. As shown in Figure 2, LDAC can be permanent low or pulse.

Asynchronous LDAC: The time to update the input register when the output is different. When the LDAC becomes low, the DAC register will update the contents of the input register. Alternatively, you can use the software LDAC function to update all DAC output register N and update all DAC registers at the same time by writing inputs. Command 0011 is retained for this software LDAC function.

The LDAC register provides users with additional flexibility and control of the hardware LDAC foot. This register allows users to choose a channel combination to perform hardware LDAC pins at the same time. Will LC channel LThe DAC position setting to 0 means that the update of the channel is controlled by the LDAC foot. If the bit is set to 1, the channel will be updated simultaneously; that is, the DAC register will be updated and reads the new data, regardless of the status of the LDAC pin. It effectively fix the LDAC pin to low. (Regarding the operation mode of the LDAC register, see Table 15.) This flexibility is very useful in the application of users who want to update the SELECT channel at the same time and other channels are being updated simultaneously.

Use command 010 to write DAC to load 8 -bit LDAC registers (DB7 to DB0). The default value of each channel is 0; that is, the LDAC pin is normal. Setting the bit to 1 means that no matter what the LDAC status, the DAC channel will be updated. The contents of the input shift register are shown in Table 16 during the loading LDAC register operation mode.

Power bypass and ground

When accuracy is important in the circuit, it is helpful to carefully consider the power and ground circuit layout on the circuit board. The printing circuit board containing AD5678 should have a separate simulation and digital part. If AD5678 needs to be connected only when other devices need to be connected to DGND. The location should be as close to AD5678 as possible.

10 μF and 0.1 μF capacitors should be used to bypass the AD5678 power supply. The physical location of the capacitor should be as close to the device as much as possible. Ideally, the 0.1 μF capacitor should be facing the device. 10 μF capacitors are beads. It is important that the 0.1 μF capacitor has low -effective series resistance (ESR) and low -effective series inductors (ESI), which is a typical feature of common ceramic capacitors. The 0.1 μF capacitor provides a low impedance grounding path caused by the high -frequency current caused by the internal logical switch.

The power cord should have as large trajectories as possible to provide a low impedance path and reduce the failure effect on the power cord. Clocks and other fast switching digital signals shall be isolated from other parts of the circuit board through digital grounding. Avoid the cross -digital and analog signals as much as possible. When the trajectory crosses the relative side of the board, ensure that they run in a right -angle to reduce the feeding effect through the board. The best circuit board layout technology is micro -band technology, where the component side of the circuit board is only used for ground plane, and the signal traces are placed on the welded side. However, this is not always possible to be with the 2 -layer board.

The size of the shape

[1] The temperature range is -40 ° C to+105 ° C , Usually 25 ° C.

[2] Use AD5678 12 -bit DAC (code 32 to code 4064) and AD5678 16 -bit DAC (code 512 to code 65024). The output has been uninstalled.

[3] It is guaranteed by design and characteristics;

[4] The interface is not activated.All DAC activation.DAC output has been uninstalled.

[5] Eight DACs were powered off.

[6] It is guaranteed by design and characteristics; [7] See the term part. [8] The temperature range is -40 ° C to+105 ° C, and is usually 25 ° C. [9] Z Lead -free part.