Feature

User programming soft start

Active low stop

User's programmable maximum load

cycle

] The approachable 5V reference voltage

IOU lock

Run to 1MHz

0.4a source /0.8a exchange field effector drive

Low 100 100 Wei'an startup current

Economic first -sided controller

Instructions

UCC3809 series BCDMOS low -power integrated circuit contains offline and isolation houses All control and drive circuits DC-DC fixed frequency current mode switch the number of external parts with the least external parts. The internal implementation circuits include the lack of voltage lock, the start -up current is less than 100 Weire, and the user communication can accept the voltage benchmark to ensure the logic of the lock operation, the pulse width modulation, and the totem output level to the receiver or source peak current. This output level is suitable for driving the N -channel MOSFET, which is very low when closed.

The frequency of oscillator and maximum duty occupy ratio are resistors and capacitors. The UCC3809 series also has a full loop soft start.

The family has the UVLO threshold and lagging horizontal line and DC-DC system, as shown in the left table.

UCC3809 and UCC2809 provided (n), TSSOP (PW), and MSOP (P) packets in 8 stitches (D), PDIP. Small TSSOP and MSOP software packets make the device very suitable for circuit board space and height.

Typical Application Figure

Absolutely maximum rated value*

VDD, VDD, VDD, VDD, VDD, VDD, VDD, VDD , VDD, VDD, VDD, VDD, VDD. 19 volts

IVDD. Essence Essence 25 mAh

IOUT (TPW LT; 1 milliseconds, occupy a duty cycle lt; 10%). Essence Essence 0.4A to 0.8A

RT1, RT2, stainless steel. Essence Essence Essence Essence Essence 0.3V to reference voltage+0.3V

Iref. Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence Essence -15 mia

Storage temperature. Essence Essence -65-C to+150-C

knot temperature. Essence Essence Essence Essence Essence -55 degrees Celsius to 150 degrees Celsius

Lead temperature (welding, 10 seconds). Essence Essence +300 degrees Celsius

The value of damage may occur.

Unless otherwise explained, all voltageAll related to ground.

The current is a positive inflow, and the negative flow produces the specified heat -2. For the heat restrictions and precautions of packaging, see the packaging part of the data manual.

Tube Foot Instructions

FB: This pin is a recipient feedback, voltage induction feedback (passed optocoupler) and slope compensation for current detection. Export slope compensation compensation from the upper -time capacitor from an external small signal NPN crystal tube buffer.

The capacitance of the external high -frequency filter. The discharge from the node to the GND is from the resistance of the resistance NMOS FET within the vein width modulation of the pulse width and provides the effective front edge of the RC time setting current feedback resistor. Constant FB input resistance and high -frequency filter capacitor. GND: All reference ground and power grounding function.

Output: This pin is the output of a large current power drive. A recommended minimum segment pole resistance is 3.9 to limit the grid drive current voltage when running at high bias.

Reference: Internal 5V reference output. This reference is a buffer that can be used on the reference pin. Ref should be bypassed 0.47 F ceramic capacitors.

RT1: The pin is connected to the timing resistor RT1 and the positive slope time (TR 0.74 (CT+27PF) RT1) of the internal oscillator. The internal oscillator of the positive threshold to sensor RT2 through non -active timing of time, connect to the pin RT2 and the timing capacitor CT.

RT2: The pin is connected to the timing resistor RT2 and the negative slope time of the internal oscillator (TF 0.74 (CT+27PF) RT2). The negative threshold is connected to the pin RT1 and the timing capacitor CT through non -active timing sensing internal oscillator RT1.

This needle has two functions. Softening the regular -timed capacitor is connected to SS and from the internal micro -safe current source. When the normal soft start is the discharge to at least 0.4V, and then transition to the positive voltage to 1V During this time, the output drive remains low. As a SS from 1V to 2V, the charging soft start is increased by the increased output duty. If the SS is less than 0.5V, the output drive is suppressed and maintained at a low level. The 5V voltage benchmark that the user can approach will also become low and IVDD

VDD: The power input connection of this device. This pins are adjusted in parallel to the rated voltage of the DMOS output drive level below 17.5V. The video display should use 1 F ceramic capacitor bypass.

Application information

The typical application diagram shows

Use UCC3809's anti -gratitude converter.

CRF and CVDDs are local decoupled capacitors for reference voltage and IC input voltage, respectively. Both capacitors should be low eSR and ESL ceramics are placed in the position near the IC pin as much as possible, and then returned to the ground pins that are directly connected to the chip to obtain the best stability. Ref provides many internal deviations of many IC functions. CREF should be at least 0.47 μF to prevent REF from sagging from the lower sag.

The basic premise of the FB pin UCC3809 is that the sensor feedback signal comes from the optocoupler on the second side. This signal and current influenza signal and FB pin are compared with the 1V threshold, such as typical application diagrams. More than 1V threshold heavy vein width modulates the lock memory and modulates the output drive to the real -time nature of UC3842. Without the FB signal, the output will follow the maximum opening time of OS Cillator. When compensation is compensated, the AC coupling of small capacitors and oscillators waveforms before seeking this signal with the FB pin. Correctly select the transmitting resistance of the optocoupler, and the voltage detection signal can force the FB node to exceed the 1V threshold that is compared when the output is compared. This will drive the UCC3809 duty ratio to zero. Oscillator

The frequency of oscillator is set in the following formulas:

f CT-PF-RT-RT [] (...) osc + +-0 74 27 1 2 1.

D RT CT PF F maximum OS C ++ 0 74 1 27. ()

When Q1 is turned on, CT is charged through Q1's RDS (on)

Part 1. During the charging process, the voltage of CT is induced by RT2. The s (OSC) of the oscillator locks is the level sensitive, so the Q output (CLK signal is set to 2/3VRef or 3.33V (typical 5.0V reference voltage)) ) Lock. The high CLK signal causes turning off Q1 and opening Q2. CT is now RDS (open) in RT2 and the second quarter. CT discharge from 3.33V to the lower threshold (for the typical 5.0V, set to 1/3 VREF or 1.67V reference), through the RT1 induction. The R (OSC) R input of the OSCIL LATOR locks R (OSC) is also sensitive, and the CLK signal is low when the CT exceeds 1.67V threshold. Turn off Q2 and open Q1 to start another charging cycle.

The figure shows waveforms related to the oscillator lock and pulse width modulation lock (as shown in the typical application diagram). The high CLK signal not only starts the discharge cycle of the CT, but it also opens the FET on the internal NMOSFB tube foot that any external capacitor is used to connect to the front edge of this pinrse to be unloaded to the ground. By discharging any external capacitors, the externally grounded switch is turned off. The anti -noise resistance of the converter is enhanced, allowing users to design anterior edge in a smaller RC component. High CThe LK signal also sets up the level sensitive S input of the PWM memory, S (pulse width modulation), high, resulting in high output, Q (pulse width modulation), as shown in the figure. This Q (pulse width modulation) signal will keep high electricity level until receiving the reset signal R (pulse width modulation). High R (pulse width modulation) signal comes from the FB signal through the 1V threshold, or during the soft start, or if the SS pin is disabled.

Assume that the UVLO threshold is satisfied, as long as Q (PWM) is high and S (PWM), also known as CLK, which is low. As long as the FB is low when the CLK is low, the signal trigger the 1V threshold. If the FBCLK is low, the signal does not exceed the 1V threshold, and the output signal will be controlled by the maximum duty cycle to be programmed by the user. The diagram illustrates 70%of the various waveforms designed by the maximum value.

Application information (continued)

The recommended value of CT is 1NF, the frequency is 100 kHz or smaller Scope and smaller CT to get higher frequencies. RT1's minimum recommendation value RT2 is 10kΩ and 4.32kΩ, respectively. The ratio of at least 20: 1 is maintained between the use of these values internal FET and external timing resistance RDS (on), making the frequency of temperature change to the smallest. Because the oscillator couples against the capacitor, the RT1-RT2-CT node commonly viewed on the circuit is the opposite of the pins 3 and the opposite of the pin 4. For good noise resistance, RT1 and RT2 should be placed as pins 3 and 4 near IC as possible. CT should be directly returned to the ground pins o

Application information (continued)

Synchronous

As shown The internal oscillator of UCC3809 can be successfully implemented. Both schemes allow the time to access slope compensation to the maximum effect on the maximum of programming.

In the absence of synchronization pulses, the PWM controller will scan with RT1, RT2 and computer faults. This free operation frequency must be about 15%to 20%lower than the synchronous pulse frequency to ensure that the free -run oscillator does not pass the threshold before the synchronization pulse required for the comparator.

Option I use the synchronous pulse to pull the pin 3, trigger the internal 1.67V comparator reset the RS lock and start the charging cycle. When the valley voltage uses this synchronization, the CT waveform is more configured to reduce the slope charging and discharge double, thereby increasing the working frequency; on the other hand, the overall shape of the CT voltage waveform does not change.

Options II uses synchronization voltage on the peak of CT waveforms with synchronous pulses. This trigger internal 3.33V comparator, starts the discharge cycle. The synchronous pulse and free pulse run the oscillator waveform at the CT node, resulting in the peak of the CT peak voltage.

ucc3802And UCC3809 First side pulse width control controller