XC6SLX16-2FTG256C

Embedded - FPGA (Field Programmable Gate Array)

category

Integrated Circuit (IC)

Embedded - FPGA (Field Programmable Gate Array)

manufacturer

Xilinx Inc.

series

Spartan?-6 LX

Package

tray

Part status

in stock

Number of LAB/CLB

1139

Number of logic elements/units

14579

Total RAM bits

589824

I/O count

186

Voltage - Powered

1.14V ~ 1.26V

installation type

Surface Mount Type

Operating temperature

0°C ~ 85°C (TJ)

Package/Enclosure

256-LBGA

Supplier Device Packaging

256-FTBGA (17x17)

Basic product number

XC6SLX16

The series provides leading system integration capabilities to meet the needs of high volume applications at the lowest total cost. This

The 13-member family offers expanded densities from 3840 to 147443 logic cells with half the power consumption

Spartan series, and faster, more comprehensive connections. Built on mature 45nm low-power copper process technology,

Offering the best balance between cost, power and performance, the Spartan-6 family provides a new, more efficient dual-register 6-input look-up table (LUT) logic with a rich set of built-in system-level modules for you choose. This includes second-generation 18 Kb (2 x 9 Kb) block RAM

DSP48A1 slice, SDRAM memory controller, enhanced mixed-mode clock management module, SelectiO™ technology, power-optimized high-speed serial transceiver module, PCIExpress™ compatible endpoint module, advanced system-level power management

mode, auto-detect configuration options, and enhanced IP security with AES and device DNA protection. These features provide a low-cost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGA provides the best solution for the following products

High-volume logic designs, consumer-facing DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are

Programmable silicon foundation for target-oriented design platforms that provide integrated software and hardware components to enable

Designers focus on innovation as soon as the development cycle begins.

Spartan-6 FPGA Feature Summary

?Spartan-6 family:

?Spartan-6 LX FPGA: Logic Optimization

?Spartan-6 LXT FPGA: High-speed serial connection

?Designed for low cost

?Multiple efficient manifolds

?Optimized I/O standard selection

? Staggered pads

? High-volume plastic wire-bond packages

?Low static and dynamic power consumption

? 45nm process optimized for cost and low power consumption

? Sleep power-down mode, zero power consumption

? Suspend mode maintains state and configuration by

Multi-pin wake-up with enhanced control

?Low power 1.0V core voltage (LX FPGA only, -1L)

? High performance 1.2V core voltage (LX and LXT

FPGA -2, -3 and -3N speed grades)

?Multi-voltage, multi-standard SelectIO? interface library

? Up to 1,080 Mb/s data transfer rate per differential I/O

? Optional output driver, 24 mA max per pin

?3.3V to 1.2VI/O standards and protocols

?Low-cost HSTL and SSTL memory interface

?Compliant with hot swap

? Adjustable I/O slew rate for improved signal integrity

? High-speed GTP serial transceivers in LXT FPGAs

?Up to 3.2 Gb/s

?High-speed interfaces, including: Serial ATA, Aurora,

1G Ethernet, PCI Express, OBSAI, CPRI, EPON,

GPON, displayPort and XAUI

?Integrated Endpoint Block for PCI Express Designs (LXT)

?Low-cost PCI?Technical support and

33 MHz, 32-bit and 64-bit specifications.

? Efficient DSP48A1 slice

?High-performance arithmetic and signal processing

? Fast 18 x 18 multiplier and 48-bit accumulator

?Pipelining and cascading capabilities

? Pre-adder to assist filter application

?Integrated memory controller module

?DDR, ddr2, ddr3 and LPDDR support

? Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)

?Multiport bus structure with independent FIFO reduces

Design Timing Issues

?Abundant logic resources and increased logic capacity

? Optional shift register or distributed RAM support

? Efficient 6-input LUT improves performance and

minimize power

? LUT with dual flip-flop for pipeline-centric applications

? Block RAM with wide granularity

?Fast block RAM with byte write enable

? 18 Kb block, which can optionally be programmed into two

Independent 9 Kb Block RAM

? Clock Management Tile (CMT) for enhanced performance

?Low noise, flexible clock

? Digital Clock Manager (DCM) eliminates clock skew

and duty cycle distortion

? Phase Locked Loop (PLL) for low jitter clocks

?Frequency synthesis, simultaneous multiplication,

Division and Phase Shift

? 16 low-skew global clock networks

? Simplified configuration, supporting low-cost standards

?2-pin auto-detection configuration

? Extensive 3rd party SPI (up to x4) and NOR flash support

? Feature-rich xilinx platform flash memory with JTAG

?MultiBoot supports multiple remote upgrades

Bitstream, using watchdog protection

?Enhanced security by design protection

? Unique device DNA identifier for design authentication

? AES bitstream encryption in large devices

?Faster embedded processing, enhanced low cost

microBlaze™ soft processor