General description

ZILOG's Z86E04 /E08 microcontroller (MCU) is ZILOG's single -chip Z8 Microcontroller family one -time programming (OTP) Members, allowing simple software development, debugging, prototype production and small production operations, but the use of the shielding ROM version is not economical.

For applications that require strong I/O functions, the special input and output cable of Z86E04/E08 is divided into three ports. It can be configured under software control to provide timing, status signals or parallel I/O. Essence

Two counters/timers on the two films have a large number of user -available modes, which reduces the system burden of management real -time tasks (such as counting/time and I/O data communication).

Two programmable 8 -bit countmakers/timers, each 6 -digit programmable preliminary frequency frequency frequency frequency power, POR) acceptable XTAL, ceramic film oscillator resonance, LC, RC or or Outer clock WDT WDT resetting low power consumption (typical 50 MW) fast instruction pointer (1 microsecond@12 MM)

Note: All signals of the front slash are low levels of activity at low levels , For example: B // W (the word is low level);/b/w (byte only low level).

Function box diagram

General description

EPROM programming mode box diagram

Pipe instructions

18 -needle EPROM mode configuration. 18 -needle DIP/SOIC mode configuration

Table 1. Dipping needle recognition Table 2. 18 -pin DIP/SoIC pin recognition

Standard test conditions

The following features are applicable to the standard test conditions described. All voltage refers to grounding. Positive current inflow reference pin

Test load chart

Note:

1. Only port 2 and port 0

[

[ 123] 2. VSS 0V GND

3. The device works to VLV with a specified frequency. The minimum working voltage CC depends on the voltage VLV value at the ambient temperature. VLV increases with the decrease in temperature.

4. VCC 4.5V to 5.5V, the typical value measured during VCC 5.0V

5. Standard mode (non -low EMI mode)

6 . Only Z86E08

7. All outputs have been uninstalled, and all inputs are at VCC or VSS levels.

8. If you select an analog comparator, the comparator input must be at VCC level.

AC electrical characteristics

AC electrical timing graph

pin function

OTP programming mode

[

123] D7-D0 data bus. The data can be read or written from EPROM through this data bus.

Five Kocos Islands Power. It is usually 5V in the EPROM reading mode, and 6.4V under other mode (program, program verification, etc.).

/Chief Executive chip enabled (low activation). This pin is activated during the EPROM reading mode, program mode and program verification mode.

/Operation Experience Output Enabilities (effective low). This pin drives data bus direction. When the pin is low, the output data bus. High -electricity usually enter the data bus.

EPROM program mode. This pin controls different EPROM program modes by applying different voltages.

Wusuylene program voltage. The pins provide program voltage.

Clear removal (high activation). This PIN resets the internal address counter to a high level.

Clock address clock. This pin is clock input. The internal address counter is added in one clock cycle.

/PGM company program mode (low activation). The low level of the pin is programmed to EPROM through the data bus.

Precautions for use

If there is too large noise waves above VCC on the XTAL1 pin, the production test mode environment may be used unexpectedly during normal operation.

In addition, when the microcontroller is in the standard mode, the processor operation of the Z8 OTP device may be affected by the surging noise waves on the foot of VPP,/CE,/EPM,/OE tube.

Suggestions that suppress voltage surge in testing and OTP mode include:

Use VCC to clamp the diode.

Add a capacitor to the affected pin.

Note: Programming the Eprom/Test Mode Disable option will prevent accidents from entering the EPROM mode or test mode.

pin function (continued)

XTAL1, XTAL2 crystal input, crystal output (input and output based on time). These pins connect parallel resonance crystals, LC or external single -phase clocks (8MHz or 12MHz) to the clock on the filmOscillator and buffer.

Port 0, P02-P00. Port 0 is a 3 -bit two -bit Schmidt triggering CMOS compatible I/O port. These three I/O cables can be configured to input or output the global control under software control

automatic locking. The automatic locks put the effective CMOS level at all non -external -drive CMOS inputs (except P33, P32, P31). A valid CMOS level, not a floating node, can reduce excessive power current in the input buffer. After turning on the power and resetting, the automatic lock will set the port to 0 or 1 to set. The default condition is to enable automatic locking.

Port 0 Configuration port 2, P27-P20. Port 2 is an 8 -bit, bit -can, dual control input or output, independent. BITS Prodirectional, Schmitt trigger CMOS compatible I/O ports. Programming is the overall programming, because these eight I/O cables can be configured under push -pull or leakage software

Port 2 configuration

pin function (Continued)

Port 3, P33-P31. Port 3 is a 3-digit CMOS compatible port. These three input cables are also used as interruptions of three fixed input cables (P33-P31). These three input sources IRQ0-IRQ3, as the timer input signal Tin

configure the line to digital Smallist trigger input or simulate under software control.

Function description

Z86E04/E08 device integrates the following special functions to enhance the standard Z8 core architecture and provide users with higher design flexibility.

Reset. This function is completed by power -on resetting or looking at the scheduler timer. After the power is powered, the power -to -reset circuit is waiting for TPORMS, plus the 18 clock cycle, and then start the program at 000C (hexadecimal). Z86E04/E08 controls the reset value of the register as shown in Table 3

at the output edge or comparator 1 of the comparator 2 The output drops the edge of the border. The comparator output is used to interrupt generate, port 3 data input or Tin through P31. Alternatively, the comparator can be disabled, and the reference input (P33) can be released for IRQ1 and/or P33 input.

Powering and reset (POR). A timer circuit clock is used by a dedicated car RC oscillator for a POR timer function. POR time allows VCC and oscillator circuits to stabilize before the execution of the instruction. The Por timer circuit is a one -time timer triggered by one of the following four situations:

Poor power to electricityGood source

Stop mode recovery

WDT timeout

WDH timeout

Looking at the scheduler timer reset. WDT is a disposable disposable timer. If it reaches its terminal count, it will reset the Z8. WDT was initially enabled by executing the WDT instruction, and re -triggered when the WDT instruction was executed. The timer circuit is driven by the RC oscillator.

Program memory. Z86E04/E08 can address internal program memory with up to 1k/2KB (pictured). The first 12 bytes of the program memory are retained for interrupt vectors. These positions include 6 16 -position vectors, corresponding to 6 available interruptions. Byte 0-1024/2048 is a one-time programmable ROM.

Z86E04/E08 instruction can directly access the register through the 8 -bit address field. This allows the use of the register pointer to address a short 4 -bit register.

In 4 digits, the register file is divided into 8 working register groups, and each working register group occupies 16 continuous positions. The starting position of the register pointer (picture) processing activity register group.

Stack pointer. Z86E04/E08 has an 8 -bit stack pointer (R255), which is used for the internal stack of 124 general registers.

General Register (GPR). These registers are not defined after the device is powered. As long as the reset occurs within the scope of working specified by the VCC voltage, the register maintains its final value after any reset. Note:

In this figure, the extension register group is selected by the bit D3 to D0 in the register R253 (RP) as 0 " processing (0).

The register pointer

The register R254 is specified as a general register