ISL6530 The dual DC-DC converter DDRAM memory application optimized for high performance. Its design purpose is to reduce the N -channel MOSFET in the speed synchronization of the speed and rectification buck of the 2.5V VDDQ topology DDRAM memory for the 2.5V VDDQ, for VREF for DDRAM differential signals, and VTT for signal termination. ISL6530 integrates control, output adjustment, monitoring and protection functions into a single package. The VDDQ output of the converter is kept at 2.5V through integrated precision voltage benchmarks. VREF output accurately adjust to 1/2 of the storage power, with a maximum temperature tolerance of ± 1%and changes in line voltage. VTT accurately track VREF. In the V2_SD sleep mode, VTT output is adjusted by a low -power car window. ISL6530 provides simple, solid feedback circuit, voltage mode control and fast transient response. Including two locks 300kHz triangle wave oscillator replaced 90 degrees, with a minimized interference pulse width adjustment regulator. The regulator has an error amplifier 15MHz gain bandwidth and 6V/microsecond conversion rate to fast transient high converter bandwidth meter. The existing pulse width regulation is 0%to 100%. ISL6530 is modulated by inhibiting pulse width. ISL6530监控电流在VDDQ调节器中，使用上部的rDS（ON无需电流传感的MOSFET电阻器。

特征

为单通道和The dual-channel DDRAM memory system provides VDDQ, VREF, and VTT voltage

Excellent voltage adjustment -VDDQ 2.5V ± 2%full range-VREF (VDDQ ÷ 2) ± 1%exceeds the full working range-vtt VREF ± 30mv

Support S3 " sleep mode Ligue ratio

Input operation from+5V input operation

Over current fault monitor on VDD-no additional current sensing element-using MOSFET RDS (open)