Features

1.8V power operation; low power consumption: 110 MW per channel, 125 millisecond/second, scalable power options; signal -to -noise ratio 74 decibels (to Naquist); SFDR; SFDR; 90 dbc (to Naquist); DNL ± 0.75 LSB (typical); INL ± 2.0 LSB (typical); serial LVDS (ANSI-644, default value) and low power, low signal options (similar to it to similar to to IEEE1596.3); 650 MMS full power simulation bandwidth; 2V P-P input voltage range; serial port control; full chip and single-channel power disconnection mode; flexible drill positioning; built-in and custom digital test mode generation; multi-chip synchronization and and Clock distribution; programming output clock and data calibration; programming output resolution; standby mode.

Application

Medical ultrasound; high -speed imaging; orthogonal radio receiver; diversity radio receiver testing equipment.

General description

AD9253 is a four -bit, 14 -bit, 80MSPS/105MSPS/125MSPS modulus converter (ADC), which has a low cost, low work The sampling maintenance circuit designed by consumption, small size and easy -to -use. The product runs at a conversion rate of up to 125 MSPS and is optimized for excellent dynamic performance and low power consumption in small encapsulated applications.

ADC requires a 1.8V power supply and LVPECL-/CMOS-/LVDS compatible sampling rate clock to achieve full performance work. Many applications do not require external references or drivers.

ADC automatically uses the sampling rate to multiply at an appropriate LVDS serial data rate. Provides data clock output (DCO) for data on the output and frame clock output (FCO) for new output bytes for signaling. Support a single channel power off. When all channels are disabled, the power consumption is usually less than 2 mW. ADC contains some characteristics of maximizing flexibility and minimizing system costs, such as as a programmable output clock and data calibration and digital test graph. The available digital test mode includes the built -in certainty and pseudo -random mode, and the test mode defined by the custom user definition through the serial port interface (SPI).

AD9253 uses 48 lead LFCSP that meets the ROHS standard. This product is -40 ° C to+85 ° C within the industrial temperature range. The product is protected by the US patent.

Product Highlights

1. The area is small. Four ADCs are included in a small space saving.

2. Low -power 110 MW/channel, 125 millisecond/second, scalable power options.

3. Compatible with AD9633 12 -bit ADCPin.

4. Easy to use. Data clock output (DCO) works at a frequency of up to 500 MHz and supports dual data rate (DDR) operation.

5. User flexibility. SPI control provides a series of flexible functions to meet specific system needs.

Sequence diagram

For SPI register settings, see the memory mapping register description part.

Typical performance features

Equivalence circuit [ 123] Operation theory

AD9253 is a multi -level assembly line ADC. Each stage provides sufficient overlap to correct the flash memory errors in the previous stage. In digital correction logic, the quantitative output from each level is combined into the final 14 -bit result. The serialization program transmits data after transmission conversion in 16 -bit output. The assembly line architecture allows the first stage to use a new input sample operation, while the rest of the sample operation is used in the rest of the stage. The sampling occurs at the rising edge of the clock.

Each level of the pipeline (excluding the last level) is composed of low -resolution Flash ADC connected to the switch capacitor DAC and the remaining amplifier (eg, multiplication digital modulus (MDAC)). The differences between the DAC output of the remaining amplifier and the Flash input in the next stages of the next level. Each stage is used to use a digital correction for flash memory errors. The last level consists of a Flash ADC. Output temporarily deposit block data, correct errors, and pass the data to the output buffer. The data is then serialized and aligned with the frame and the data clock.

Precautions for analog input

The analog input of AD9253 is a differential switch capacitor circuit that designs the differential switching of the differential input signal. While maintaining good performance, the circuit can also support a wider -mode range. By using an intermediate power supply that enters the co -mode voltage, the user can minimize the error related to the signal to achieve the best performance.