Feature

-12 bit resolution

-65-MSPS maximum sampling rate

-2-vpp differential input range

-3.3- V single power operation

-1.8-V to 3.3-V output power supply

-400 MW total power consumption

-two supplementary yards output formats

[

[ 123] -The regulating circuit on the S/H to occupy ratio on the film

-In internal or external reference

-An 48-pin TQFP packaging with a power board (7 mm x 7mm body size) [) [7 mm x 7mm body size) [ 123]

-65 MSPS and 190 MHz Input 64.5-DBFS signal-to-noise ratio and 72 DBC SFDR

-Cathe ] -1-GHZ 3-DB Input Bandwidth

Application

-The high school frequency sampling receiver

-The portable instrument

Explanation

ADS5413

is a low power consumption, 12-bit, 65-MSPS, CMOS assembly line module digital converter (ADC), which can be a single 3.3 volt power supply. In the work, it also provides digital output level selection from 1.8 to 3.3 volts. Low noise, high -line, and low clock jitter make ADCs very suitable for high input frequency sampling applications. The cycle -to -adjustment circuit on the film allows the use of non -50%duty cycle. This can be ignored for applications that require low jitter or asynchronous sampling. The device can also use a single -ended or different clock to timing without changing performance. Internal reference can bypass the use of external reference to meet the accuracy and low drift requirements of the application.

The device specifies the entire temperature range (-40 ° C to+85 ° C).

Function box diagram

Sequence diagram

Typical features

[123 ]

Equivalence circuit Application Program information Inverter operation ADS5413 is a 12 -bit assembly line ADC. Its low power consumption (400 MW) is achieved by the most advanced switch capacitor flow line structure established with advanced low -voltage CMOS processes in 65 milliseconds/second and high sampling rate. ADS5413 simulation core is powered by 3.3V power, consumed most of the electricitysource. In order to increase the flexibility of the interface, the digital output power supply (OVDD) can be set to 1.6V to 3.6V. The core of ADC consists of 10 streamlined lines and a Flash ADC. Each stage is 1.5 -bit. Utilize the samples of the pipeline through the pipeline of the rising and declining clock edges, a total of six clock cycles.

Analog input

The analog input of ADS5413 consists of a differential tracking of the use switch capacitance technology, as shown in Figure 27. This differential input topology, plus a close matching capacitor, generate high -level AC performance until high sampling and input frequency.

ADS5413 requires each simulation input (VINP and VINM) on the co -mode level of the internal circuit (CML, pin 6).

For a full-scale differential input, each differential line (pin 3 and 4) of the input signal is symmetrically swinging between CML+(VREFT+VREFB)/2 and CML- (VREFT+VREFB)/2. The maximum swing is determined by the difference between the above reference voltage (REFT) and the lower reference voltage (REFB). The total difference in input is 2 (VREFT-VREFB). For adjustments to the full label, please refer to the reference circuit part.

Although the input can be driven in a single -end configuration, when the analog input is driven by the differential, ADS5413 gets the best performance. The circuit in Figure 30 shows a possible configuration. Single -end signal is sent to the main power radio frequency transformer. Since the input signal must be biased towards the co -mode voltage of the internal circuit, the co -mode (CML) reference from the ADS5413 is connected to the central tap of the secondary circuit. In order to ensure a stable low noise CML benchmark, the best performance is obtained when the CML output is grounded through 0.1-μF and 0.01-μF low-induced capacitor.

If you need to buffer or apply the input analog signal, you can combine single -end amplifiers and radio frequency transformers, as shown in Figure 31. Texas Instruments offers a variety of computing amplifiers, such as THS3001/2, OPA847 or OPA695, which can be selected according to the application. You can place R and C to input the source from the switch of the ADC and achieve a low -pass RC filter to limit the input noise in ADC. Although it is not needed, it is recommended to arrange circuits for these three components so that the prototype is fine -tuned when necessary. However, any loss between the input differential lines will lead to a decline in performance at high input frequency, and its main feature is the increase in the occurrence of the occasional harmonic. In this case, special attention should be paid to maintaining as much electrical symmetry as possible between the two inputs. This includes short R and let Cin University leave.

Another possibility is to makeUse differential input/output amplifiers to simplify the driver circuit that needs input-DC coupling applications. This amplifier structure is flexible (see Figure 32), which can be used for single -end -to -differential conversion, signal amplification, and filtering before ADC.

Reference circuit

In the design, ADS5413 has its own internal reference signal generator, which saves external circuits. In order to obtain the best performance, it is best to connect VREFB and VREFT with ground, and connect a 1 μF and a 0.1 μF descoupable capacitor between the two feet, and a 0.1 μF capacitor (see Figure 33). The bandwap voltage output is not used for an external voltage source outside ADS5413. However, 1-μF and 0.01-μF should be separated from ground containers.

In order to be greater design flexibility, internal reference can be disabled using tube foot 48. By default, the pin is connected to the ground with the 70-KΩ drop-down resistor to ground to enable internal reference circuits. Connecting this pin with AVDD can make the internal reference generator power off, allowing users to provide external voltage for VREFT (pin 9) and VREFB (pin 8). In addition to the reduction of power consumption (usually 56MW) transmitted to the external circuit, it also allows accurate setting input range. In order to further eliminate any changes in external factors (such as temperature or power supply voltage), users can directly access the internal resistor division without any intermediate buffer. The equivalent circuit of the input pin is shown in Figure 26. The core of ADC is designed for the 1V difference between the reference pins. However, users can use these pipes to set different input range. Figure 11 shows the changes in the SNR and SFDR of different VREFT-VREFB voltage settings of 65 MHz and 80 MHz single-sound input.

Clock input

ADS5413 clock input can use a differential clock signal or single -end clock input drive. The performance difference between single -end and differential input configuration is very different. Small or there is no difference (see Figure 17). The common mode of the clock input is set to AVDD/2 with a 5-kΩ resistor inside (see Figure 28).

When using a single-end clock input driver, it is best to use a 0.01-μF capacitor to enter the CLKC input ground (see Figure 34), and CLK and 0.01 μF communicate coupled to the clock source.

ADS5413 clock input can also be driven. In this case, it is best to use the 0.01-μF capacitor to connect the two clocks to the differential input clock signal (see Figure 35). Differential input swing can change between 1V and 6V, and the performance has almost no decrease (see Figure 17).

Although it is recommended to use AC couplingThe configuration to set the clock co -mode, but for the situation where the communication configuration cannot be used, you can use different co -mode to operate the ADS5413. Figure 18 shows the performance of the public mode of ADS5413 for different clocks.

ADS5413 can be driven by sine waves or square waves. The internal ADC core uses the two edges of the clock to transform. This means that in an ideal circumstances, a 50%duty occupation ratio should be provided. However, the ADC includes a vehicle duty cycle regulator (DCA), which may not be a 50%duty cycle ratio for 50%of the input clock duty cycle for internal use. By default, the circuit is enabled internally (the pull -up resistance is 70 kΩ) to relax the design specifications of the external clock. FIG. 16 shows the relationship between the ADC performance of the 65 MHz clock and the 14 MHz input signal in the case of enabled and disabled DCA. However, in some cases, users may be more willing to disable DCA. For asynchronous clocks, this circuit should be disabled when the sampling cycle is deliberately not constant. Another situation is high input frequency sampling. For high input frequency, a low shake clock should be provided. In this sense, we recommend the source of the filter to provide a sine clock duty cycle to 50%. In this case, it is not good to use DCA. It will increase noise, increase jitter, and reduce performance to the internal clock. Figure 19 shows the relationship between the performance of different clock schemes and the input frequency. Finally, adding DCA to the delay between the input clock and the output data, and more importantly, the delay is slightly larger with the changes in external conditions (such as temperature). To disable DCA, users should ground it.

Power off

When the power loss (pin 16) connects to AVDD, the device reduces its power consumption to a typical value of 23MW. Connect the pin to GND or keep it unable to connect (providing an internal 70-KΩ drop-down resistor) to make the equipment work.

Digital output

ADS5413 output format is 2S supplementary code. By setting the OVDD voltage between 1.6V and 3.6V, the voltage level of the output can be adjusted to allow direct interfaces with multiple digital series. In order to get better performance, customers should choose the smaller output swing required in the application. In order to improve the performance, it is mainly in the higher output voltage swing configuration. It is recommended to add a series resistance to the output end to limit the peak current. The maximum value of this resistor is limited by the maximum data rate of the application. The usual value is between 0Ω and 200Ω. In addition, the length of restricting external traces is also a good approach.

All data maps are obtained in the worst case, of which OVDD is 3.3V. The external series resistance is 150Ω, and the load is 74AVC16244 buffer, as used in the assessment board. In this configuration, the rising edge of the ADC output is 5NS, which allows a window to capture 10.4NS data (excluding other factors).

The definition of specifications

Simulation bandwidth

The analog bandwidth is an analog input frequency. At this frequency, the spectrum power of the base frequency (determined by FFT analysis) is relative to low at low at low at low at low to low at low at low at low. The value of the measurement frequency is reduced by 3DB.

Pore diameter delay

The delay between 50%point and analog input sampling time of the clk command.

Pore diameter uncertainty (jitter)

The sampling-sampling change of the aperture diameter.

Fortune non -linearity

An average deviation of any single LSB conversion and analog input processing of digital output places 1 LSB step.

Integral non -linearity

The transmission function and the bias of the reference line measured by the best straight line determined by the minimum two -multiplied curve fixing with the minimum two -multiplied curve.

Clock pulse width/duty cycle ratio

High pulse width is CLK pulse maintenance logic 1 state to achieve the minimum amount of rated performance; low pulse width is the minimum period when CLK pulse keeps low state. quantity. At the given clock rate, these specifications define the acceptable clock duty ratio.

Maximum conversion rate

The clock frequency of parameter testing.

Power suppression ratio

The ratio of input offset voltage changes to the change of power supply voltage.

Signalive ratio and distortion (Sinad)

All other spectrum components (including harmonics, but excluding DC electricity), the equalized square root signal amplitude (set to the full scale below 1 decibel below be decibel below ) The ratio of the basis root value.

The ratio of valid value signal amplitude (123]

The effective value of the valid value (at the full marked 1DB settings) and all other spectrum components are not included Five harmonics and DC.

The dynamic range of no mixed dynamic

The ratio of the average root signal amplitude amplitude of the peak mixed spectrum component to the average root value. The peak mixed components can be harmonic or harmonic, and report in DBC.

Dual -sound interoperability distortion inhibitory

The ratio of the average root value of the input tone and the worst third -order interoperability product reported in DBC.