Features

Single channel, 256-/1024 position resolution; 20 kΩ, 50 kΩ, and 100 kΩ nominal resistors; maximum ± 1%nominal resistor difference error (resistance performance mode); 20 times times; 20 times times more Programmable wiper memory; temperature coefficient of the barrier mode: 35 PPM/℃; the temperature coefficient of the sterilizer: 5ppm/℃; +9 V to+33 V single power operation; Serial interface; Receive the wiper settings; refresh the power from the 20-TP memory.

Application

Replacement of mechanical potential; Instrument: gain and offset adjustment; programmable voltage current conversion; programmable filter, delay and time constant; programmable power supply; low resolution; low resolution; low resolution; DAC replacement; sensor calibration.

General description

AD5291 and AD5292 is a single channel, 256-/1024 digital digital potentiometer, which will lead the industry's leading variable resistor performance Tightly combined with non -eroded memory (NVM). These devices can work within the width voltage range, support dual power operations at ± 10.5 V to ± 16.5 V and single power operations at +21 V to +33 V. And provide 20-time programmable (20-TP) memory.

Ensure that the industry's leading low resistance tolerance error characteristics simplify the opening of the ring and the accurate calibration and the tolerance matching application.

AD5291 and AD5292 device wiper settings can be controlled through the SPI digital interface. Before programming the resistance value to the 20-TP memory, an unlimited adjustment is allowed. AD5291 and AD5292 do not require any external voltage power supply to promote fuse melting, with 20 opportunities for permanent programming. During the 20-TP activation, the permanent fuse commands to freeze the wiper position (similar to placing epoxy resin on a mechanical prunter).

AD5291 and AD5292 are encapsulated with compact 14 -guide TSSOP. This component is guaranteed to work within the extended industrial temperature range (from -40 ° C to+105 ° C).

Sequence diagram

ta 25 ° C, unless another separate other There are explanations.

1. The maximum terminal current processing, the maximum power consumption of the packaging, and the two terminals in the A, B and W terminals under the given resistance. The maximum external voltage limited.

2. Maximum continuous current.

3. Pulse occupation ratio.

4, including OProgramming of TP memory.

The stress greater than or equal to the absolute maximum rated value may cause permanent damage to the product. This is just a stress level; it does not imply that the product operates the conditions described in the operation part of this specification or the above conditions. Long -term operation that exceeds the maximum operation may affect the reliability of the product.

Thermal resistance

θJa is defined by JEDEC specification JESD-51, which depends on the test board and the test environment.

Typical performance features

]

Test circuit

Figure 58 to FIG Test conditions.

Operation theory

AD5291 and AD5292 digital potentiometer is designed as a real variable resistor that can be used as an analog signal. The analog signal is maintained in VSS LT; Vterm lt; VDD terminal voltage range. Getting the ± 1%resistance of patent tolerance helps to minimize the total RDAC resistance error, thereby reducing the overall system error by providing better absolutely absolute matching and improved opening performance. Digital potential wiper position is determined by the contents of the RDAC register. The RDAC register is used as a draft draft register, allowing multiple values to change according to needs to place the potential wiper in the correct position. The RDAC register can be programmed with a standard SPI interface by loading 16 -bit data words. Once you find the required position, the value can be stored in the 20-TP memory register. Since then, the wiper position has always returned to this position for subsequent power. The storage of 20-TP data requires about 6 ms; during this period, the displacement register is locked to prevent any changes. RDY tube foot logo the completion of this 20-TP storage.

Serial data interface

AD5291 and AD5292 include a serial interface (SYNC, SCLK, DIN and SDO), which are compatible with SPI interface standards and most DSP compatibility. This section allows the data to write the data into each register through a serial interface.

Showing register

AD5291 and AD5292 displacement register width is 16 bits (see Figure 2). The 16 -bit input word consists of two zero, and then consists of 4 control bit and 10 RDAC data bits. For AD5291, the lower RDAC data bit does not care whether the RDAC register is read or write. Data first load MSB(DB15). The four control bit determine the function of the software command (see Table 11). Figure 3 shows the timing diagram of typical AD5291 and AD5292.

The synchronization line is lowered at the beginning of the sequence. This synchronous tube foot must be kept low until the complete dataword is loaded from the DIN tube. When SYNC returns high, the serial data is decoded according to the command in Table 11. Instruction position (CX) controls the operation of the digital potentiometer. The data bit (DX) is the value loaded to the decoder register. AD5291 and AD5292 have an internal counter, which count the number of 16 -bit (one frame) multiple to ensure normal work. For example, AD5291 and AD5292 can handle 32 -bit characters, but 31 or 33 characters cannot be processed correctly. When synchronization is high, AD5291 and AD5292 do not need continuous SCLK. All serial interface pipes should be operated at the position near the VLOGIC power rail to minimize the power consumption in the digital input buffer.

RDAC register

The RDAC register directly controls the position of the digital potential wiper. For example, when the RDAC register loads all zero, the wiper is connected to the terminal B of the variable resistor. The RDAC register is a standard logic register; there is no limit on allowable changes.

20-TP memory

Once you find the ideal wiper position RDAC register, you can save it in the 20-TP memory register (see Table 12). Since then, the wiper position has always been set at this position so that any sequence of disrupting is performed in the future. AD5291 and AD5292 have 20 disposable programming (OTP) memory register array. When the required words are programmed to 20-TP memory, the device automatically verify whether the programming command is successful. The verification process includes margin testing. You can inquire about the bit C3 of the register to verify whether the Fuse Program command is successful. Putting data to 20-TP memory requires about 25 mAh 550 micrists, and it takes about 8 milliseconds to complete. During this period, the displacement register is locked to prevent any changes. The RDY pin can be used to monitor the completion and verification of the 20-TP memory program. Programming 20-TP memory does not need to change the power supply voltage. However, 1 μF capacitors need to be installed on the outer sales (see Figure 68). Before the activation of 20-TP, AD5291 and AD5292 preset the medium scale when power-on.

Write protection

When power is powered on, the RDAC register and the shift register of the 20-TP memory register are banned. The RDAC writing protection level C1 default settings of the RDAC writing of the register (see Table 13 and Table 14) are set to 0. This will ban any changes to the content of the RDAC register, instead of considering the software command, except that it can be usedSoftware reset command (command 4) from 20-TP memory or refresh the RDAC register through the hardware through the restraint. To enable the programming (programming RDAC register) of the position of the variable resistor wiper, we must first program the control position C1 of the register. This is achieved by loading the shift register with command 6 (see Table 11). To enable the programming of the 20-TP memory block, the C0 (default setting to 0) of the register must be set to 1 first.

Basic operation

Set the basic mode of the position of the variable resistor wiper (programming the RDAC register) is to use command 1 (see Table 11) and The required wiper position data loaded the shift register to complete. When the required wiper position is determined, the user can use the command 3 (see Table 11) to load the shift register, which stores the wiper position data in the 20-TP memory register. After 6 millimt, the position of the water scraper is permanently stored in the 20-TP memory. The RDY pin can be used to monitor the completion of the 20-TP program. Table 12 provides a programming example that lists the sequence of serial data input (DIN). The serial data output appears at the SDO tube foot in the SDO pipe.

20-TP read and spare memory status

You can use command 5 to read the content of any 20-TP memory register via SDO (see Table 11). 5 LSB bits (D0 to D4) of the data bytes are selected (see Table 16) to read (see Table 16). During the next SPI operation, the data from the selected memory position from the SDO pipe is poured in, of which the last 10 points include the content of the specified memory location.

You can also read the only memory address 0x14 and memory address 0x15 by reading the command 5. The data bytes read back from the memory address 0x014 and the memory address 0x015 are the thermometer coding version of the last programming memory position address.

For examples listed in Table 15, the address of the final programming position is calculated as follows:

If there is no programming of the memory location, the generated address will be generated. For -1.

Shipping mode

Turn off the command by executing the software, command 8 (see Table 11), and set LSB, D0 to 1. This function puts RDAC in a special state. In this state, terminal A opens the road and the wiper W is connected to terminal B. By entering the shutdown mode, the content of the RDAC register remains unchanged. However, all commands listed in Table 11 are supported in the closure mode. Execute command 8 (see Table 11), and set LSB D0 to 0 to exit the shutdown mode.

Resistance performance mode

This mode activates a new, patented1%end -to -end resistance publicity to ensure that the resistance of each code is ± 1%, that is, the code half scale, and the R 10 kΩ ± 100Ω. See Table 2 (AD5291) or Table 5 (AD5292) to check which code to reach ± 1%of the resistance tolerance. The resistor performance mode is activated by the programming position C2 of the control register (see Table 13 and Table 14). The typical settlement time is shown in Figure 50.

Reset

Hardware reset pins from low to high conversion loaded RDAC registers containing the recent programming 20-TP memory location content. AD5291 and AD5292 can also be reset through software by executing commands 4 (see Table 11). If you do not program the 20-TP memory position, the RDAC register loads the medium scale during reset. Control the register with the default bit; see Table 14.

SDO pin and chrysanthemum chain operation

The serial data output pin (SDO) has two uses: using commands 2. command 5, and command 7 (see Table 11) to read Wiper settings, 50-TP values and control registers, or SDO pins can be used in chrysanthemum chain mode. Data is planned in the SDO rising edge of SCLK. The SDO pin contains a leaking N channel FET. If the pin is used, a pull -up resistor is required. To put the tube foot in high impedance and minimize the power consumption when using the tube foot, send 0x8001 data words to the part, and then follow the command 0. Table 17 provides examples of serial data input (DIN) sequence. The chrysanthemum chain minimizes the number of port pins required by IC. As shown in Figure 64, users need to bind a bag of SDO tube to the DIN tube of the next package. Users may need to increase the clock cycle because the pull-up resistance and capacitance load at the SDO-TODIN interface may require additional time delays between follow-up devices.

When two AD5291 and AD5292 devices are connected to the chrysanthemum chain, 32 -bit data is required. The first 16 -bit enters U2, and then the second 16 -bit enters U1. Keep the synchronous pipe foot at a low position until all 32 bits are recorded in their respective shift registers. Then pull the synchronous tube foot to complete the operation.

Keep the synchronous pipe foot at a low position until all 32 bits enter their respective serial registers. Then pull the synchronous tube foot to complete the operation.

RDAC architecture

In order to obtain the best performance, the simulated device has applied for the RDAC segmented structure patent for all digital potentiometers. In particular, AD5291 and AD5292 adopt a three -stage division method, as shown in Figure 65. The AD5291 and AD5292 wiper switch adopts the grid CMOS topology structure, and the grid voltage is exported by VDD and VSS.

Variable resistor program

Voltizer operation -1%resistance tolerance

When only two terminals are used as a variable resistor, AD5291 and AD5292 are in the transformer mode in the transformer mode Work. Unused terminals can be kept floating or binding to W terminals, as shown in Figure 66.

terminal A and terminal B, the nominal resistors between R are 20 kΩ, 50 kΩ, and 100 kΩ, and 256 or 1024 connected by the wiper terminal Tap point. The 8/10 data in the RDAC memory is decoded to select one of the possible wiper settings of 256/1024. AD5291 and AD5292 include a internal ± 1%resistance performance mode, which can be prohibited or enabled by programming the C2 bits of the control register (this is enabled by default) (see Table 13 and Table 14). The digital programming output resistance between the W terminal and the A terminal R and the W terminal and the B terminal R pass internal calibration, and the maximum absolute resistance error in the wide code range is ± 1%. Therefore, the general equation used to determine the digital programming output resistance between the W terminal and the B terminal is:

where: D is loaded in the 8/10 RDAC register Timinal equivalent values of binary code.

RAB is the resistance from the end to the end.

Similar to the mechanical potentiometer, the RDAC resistance between the W terminal and the A terminal also generates a digital control complementary resistance. R.RIS is also calibrated with a maximum absolute resistance error of 1%. R starts from the maximum resistance value, and decreases as the data loaded to the memory. The general equation of this operation is:

Among them: D is the decimal value of the binary code loaded in the 8/10 RDAC register.

RAB is the resistance from the end to the end.

Under the condition of zero standard, there is a limited total scraper resistance of 120Ω. Regardless of where the components work in, pay attention to restricting the current between the terminal A and the terminal B, the terminal W and the terminal A, and the terminal W and the terminal B. Pulse current. Otherwise, the internal resistor may degenerate or damage.

Programming the potential scorer

Voltage output operation

Digital potentiometer is easy The input voltage is a proportional pressure division, as shown in FIG. 67. Unlike the polarity of V to GND (must be positive), the voltage between A to B, W to A and W to B can be arbitrary polarity.

If the impact of the scrape resistance is ignored for simplicity, connect the A terminal to 30 V, BThe terminal is connected to the ground, and the output voltage of 0 V to 1 LSB of less than 30 V to 1 LSB is generated at the wiper W to the B terminal. The voltage of each LSB is equal to the voltage applied to the A terminal and B terminals, except for the 256/1024 position of the potentiometer. For any effective input voltage on the terminal A and terminal B, the general equation defined by the V -output voltage relative to the ground is:

If in the steriler mode Using AD5291 and AD5292, as shown in FIG. 67, when matching with discrete resistance, the ± 1%resistance public difference calibration function can reduce errors. However, it is recommended to disable the internal ± 1%resistance public deviation function through programming control registers (see Table 13 and Table 14) to optimize the position update rate of the wiper position. In this configuration, RDAC is measured by ratio, and the resistance error error will not affect performance.

The operation of the digital potentiometer in the steriler mode can make the operation when the temperature is too high. Unlike the resistor mode, the output voltage mainly depends on the ratio of internal resistance R and R, not an absolute value. Therefore, temperature drift is reduced to 5ppm/℃.

Forex container

During the entire operation of AD5291 and AD5292, 1 μF capacitors must be grounded to the outer foot (see Figure 68) when power -on (see Figure 68).

Terminal voltage operating range

AD5291 and AD5292 positive V and negative V power supply define the boundary conditions for the normal operation of the 3 -terminal digital potentiometer. The power signal that appears on the terminal A, terminal B and terminal W is restrained by the internal positive bias diode (see Figure 69).

The ground pins of AD5291 and AD5292 devices are mainly used for digital grounding reference. In order to minimize the digital ground bounce, AD5291 and AD5292 grounded terminals should be remotely connected to public ground. The digital input control signals of AD5291 and AD5292 must refer to the device ground pins (GND), and meet the logic level defined in the specification part.

Powering order

In order to ensure that AD5291 and AD5292 are correct, 1 μF capacitors must be connected to the outer cover. Because the diode restricted terminal A, terminal B, and terminal W (see Figure 69), before applying any voltage to terminal A, terminal B and terminal W, you must first power V and V. Otherwise, the diode will be pressed forward, causing V and V to be electricly electric. The ideal sequence of power is GND, V, V and V, digital input, and then V, V and V. As long as V, V and V are powered on, the power sequence of V, V and digital input is not important.

Regardless of the power supply sequence and slope rate, after the V is power, the power is powered onLet activation, restore the 20-TP memory value to the RDAC register.

Application information

High -voltage DAC

AD5292 can be configured to high voltage DAC, and the output voltage is as high as 33V. The circuit is shown in Figure 70. The output is:

Among them, D is a decimal code between 0 and 1023.

The programmable voltage source with a boost output

For applications that require large current adjustment, such as laser diode or adjustable laser, you can consider using liter Plumbers; see Figure 71.

In this circuit, the reverse input of the computing amplifier forced VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then transmitted by the power supply through the N -channel FET (U3). N channel FET power processing must be sufficient to dissipate (VIN-Vout) × IL power. The circuit can be powered by 33 volt power, with a maximum current of 100 mAh.

High -precision digital modulus converter

By optimizing the resolution of the device within a specific reduction range, AD5292 can be configured to high -precision DAC. This is achieved by placing external resistors on any side of RDAC, as shown in Figure 72. The improved ± 1%R public tolerance specification greatly reduced errors related to discrete resistance.

The variable gain instrument amplifier

As shown in Figure 73, AD8221 and AD5291, AD5292 and ADG1207 together constitute an excellent instrument for data collection systems A amplifier. The data acquisition system has the characteristics of low distortion and low noise, which can regulate the signal before various modulus converters.

The gain can be calculated in formula 9.

Audio volume control

Excellent THD performance and high voltage performance make AD5291 and AD5292 become an ideal choice for digital volume control such as audio decayer or gain amplifier. Essence A typical problem in these systems is that a large -scale jump change at any time can cause a sudden interruption of audio signals, resulting in a zipper noise that can be heard. To prevent this, the zero window detector can be inserted into the synchronous line to update the delay device until the audio signal passes through the window. Because the input signal can work at any DC level rather than the absolute zero level, in this case, the zero means that the signal is coupled, and the DC offset level is the zero reference point of the signal.

The configuration of reducing zipper noise is shown in Figure 74. The results of this configuration are shown in Figure 75. Enter the AC coupling from C1The merger is attenuated before entering a window comparator formed by U2, U3 and U4B. U6 is used to establish zero reference signal. The upper limit of the comparator is set on its offset. Therefore, in this example, the output pulse is high when entering between 2.502 V and 2.497 V (or 0.005 V window). This output is the synchronous signal to update the AD5291 and AD5292 when the signal passes through the window. Avoid constant updated devices, synchronous signals should be programmed as two pulses, not one.

In FIG. 75, a lower record display shows that when the signal changes near the zero window, the volume level changes from a quarter of the scale to a full scale.

The size of the shape

[1] The maximum current processing and the maximum power consumption of the maximum current of the switch And at the maximum outer voltage limit of any two in the A, B and W terminals under the given resistance. 2 Maximum continuous current 3 pulse duty ratio.

[2] Including programming of OTP memory.

[3] x Don't care.

[4] In AD5291, this is irrelevant.

[5] The wiper position was frozen to the value of the previous programming in 20-TP memory. If the 20-TP memory is not programmed, the wiper is frozen to the medium scale.

[6] Allow users to calculate the remaining free memory location.