Features

AD5253 : Four -digit 64 -bit resolution; AD5254 : Four 256 position resolution; 1,000 euros, 10,000 euros, 50,000 thousand thousand, 50,000 thousand thousand Europe, 100,000 Euros; non -easy loss memory [1] storage bands to write protective wiper settings; pass to the EEMEM settings of 300 microseconds; EEMEM rewriting time 540 microsecond (typical value); stored in non -Easy Easy Easy The resistance tolerance in the sex memory; the 12 extra bytes in EEMEM are used for information defined by the user; Linear incremental/reduction command; pre-defined ± 6 decibel grades jumping command; synchronous or asynchronous four-channel update; wiper settings back; 4MHz bandwidth -1kΩ version; single power supply 2.7 V to 5.5 V; dual power supply ± 2.25 2.25 V to ± 2.75 V; 2 operations of the two devices from the address decoding bit; the typical data of 100 years is saved, TA 55 ° C; working temperature: -40 ° C to+85 ° C.

Application

Replacement of mechanical potential; low resolution DAC replacement; RGB LED backlight control; white LED brightness adjustment; bias control of the power amplifier of the radio frequency base station; programmable gain and offset control ; Programmable attenuator; programmable voltage current conversion; programmable power; programmable filter; sensor calibration.

General description

AD5253/AD5254 is four channels, ICs, non -vulnerable memory, 64/256 digital digital control potentiometers. These equipment executes the same electronic adjustment function as mechanical potential, fine -tuning, and variable resistors.

AD5253/AD5254's multifunctional programming can allow multiple operating modes, including reading/writing access in RDAC and EEMEM registers, incremental/reduction of resistance, resistance in the range of ± 6 db Change, the recovery of wiper settings, and additional EEMEM for storing user definition information (such as other components), find tables or system identification information.

AD5253/AD5254 allows the host IC controller to write 64/256 wiper settings in the RDAC register and store it in EEMEM. Once these settings are stored, they will automatically return to the RDAC register when the system is turned on; these settings can also be dynamically restored.

AD5253/AD5254 provides additional incremental, reduced,+6 decibel jump and -6 decibels in the synchronous or asynchronous channel update mode. Increment and reduction function allows gradual linear adjustment, while the order change of ± 6 decibels is equivalent to double or halving the RDAC wiper settings. These functions can be used for non -linear adjustment applications of steep slopes, such as whiteLED brightness and audio volume control.

AD5253/AD5254 has a patented resistance capacity limit storage function, allowing users to access EEMEM and obtain an absolute end -to -end resistance value of RDAC to be used for precision applications.

AD5253/AD5254 has 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options of TSSOP-20 packaging. All components are guaranteed to work within the extended industrial temperature range of -40 ° C to+85 ° C.

Typical performance features

] I2C interface

I2C interface general description

s starting conditions.

p Stop conditions.

A confirmation (low SDA).

A Uncertain (SDA high).

r/w high reading and enabled;

I2C interface detailed description

s starting conditions.

p Stop conditions.

A confirmation (low SDA).

A Uncertain (SDA high).

AD1, AD0 IC device address bit. It must be matched with the logical state at the pin AD1 and AD0. R/W Reading Power Bit, High Logic/Writing Enable Bit, Low Logic.

CMD/R command enable bit, logic high/register access bit, low logic.

EE/RDAC EEMEM register, high logic high/RDAC register, low logic. A4, A3, A2, A1, A0 RDAC/EEMEM register address.

RDAC/EEMEM Write

Setting the wiper position requires RDAC writing operation. The single writing operation is shown in Figure 27, and the continuous writing operation is shown in Figure 28. In continuous writing operation, if you choose RDAC and the address starts from 0, the first data byte to RDAC0, the second data byte to RDAC1, the third data byte to RDAC2, the fourth one The data byte is turned to RDAC3. This operation can continue to eight addresses with four unused addresses; then cycle back to RDAC0. If the address starts from any of the 8 valid address n, the data is first transferred to RDAC_N, RDAC_N+1, and push it according to this;RDAC0. The RDAC address is shown in Table 6.

Although the RDAC wiper setting is controlled by a specific RDAC register, each RDAC register corresponds to a specific EEMEM memory position, which provides non -easy -to -lose -loss wiper storage functions. The address is shown in Table 7. Single and continuous writing operations are also applicable to EEMEM writing operations.

There are 12 non -easy -to -sex memory positions, EEMEM4 to EEMEM15, users can store 12 bytes of information in them, such as as other components, finding tables or system memory data identity information. In the writing operation of the EEMEM register, the IC interface is disabled during the internal writing cycle. Confirmation of rotation (discussion in the data table later) is necessary to determine the completion of the writing cycle.

RDAC/EEMEM read AD5253/AD5254 offers two different RDAC or EEMEM reading operations. For example, FIG. 29 shows the method of reading RDAC0 to RDAC3 content without specifying the address. Assuming that the address RDAC0 has been selected from the previous operation. If you previously select RDAC_N other than the address 0, read back from the address n, and then N+1, which is pushed according to this.

FIG. 30 illustrates the reading operation of random RDAC or EEMEM. This operation allows users to specify which RDAC or EEMEM register to read. The method is to first issue a false writing command to change the RDAC address pointer, and then continue to perform RDAC reading operations at the new address position.

s Starter condition;

p Stop stop Conditions;

a confirmation (SDA low);

a uncertainty (SDA high);

AD1, AD0 IC device address bit. It must be matched with the logical state at the pin AD1 and AD0.

R/W Reading Power, High Logic/Writing Power Pitch, Low logic CMD/Reg Direction Bit, Logic High/Register Access Position, Low logic C3, C2, C1, C0 Command bit A2, A1, A0 RDAC/EEMEM register address.

RDAC/EEMEM fast command

AD5253/AD5254 has 12 fast commands, which is convenient for operating RDAC wiper settings and provided storage and recovery from RDAC to EEMEM Function. The command format is shown in Figure 31, and the command description is shown in Table 9.

When using a quick command, there is no need to issue a third byte, but the third byte is allowed. Quickly command to reset RDAC and store it to EEMEM needs to confirm the rotation inquiry to determine whether the command has been completed.

RAB tolerance stored in only read storage

AD5253/AD5254 stored patent RAB tolerance in non -easy -to -sex memory. The tolerance of each channel is stored in the memory during the production process, and users can read it at any time. The knowledge of storage tolerance, that is, the average value of the overall code of R (Figure 29), allows users to accurately predict RAB. This characteristic is very valuable for accuracy, resistor mode or opening ring application. In these applications, the knowledge of absolute resistance is essential.

The stored tolerance is located in only read memory and expressed at percentage. The tolerance is dual -encoded in the size of the symbol, 16 -bit, and stored in the two memory positions (see Table 10). The data format of the tolerance is a dual -proof format of the symbol; the for example is shown in Figure 32. In the first memory position of the eight data bits, MSB is specified as a symbol (0 +and 1 -), and 7 LSB is specified as an integer part of the tolerance. In the second memory position, all eight data bits are specified as a decimal part of the tolerance. As shown in Table 8 and Figure 32, for example, if the rated R 10 kΩ, the data read from the address 11000 shows 0001 1100 and the address 11001 shows 0000 1111, then the RDAC0 tolerance can be calculated as:

]

EEMEM write confirmation rotation

After each writing operation of the EEMEM register, a internal writing cycle starts. The IC interface of the device is disabled. In order to determine whether the internal writing cycle is completed and whether the IC interface is enabled, the interface can be executed. The IC interface rotation can be performed by sending a starting condition, and then the position of the machine address+writing. If the IC interface is responded with ACK, the writing cycle is completed, and the interface is ready to continue performing further operation. Otherwise, you can repeat the IC interface rotation until successful. Command 2 and 7 also need to confirm the rotation.

EEMEM writing protection

After EEMEM programming, set WP PIN to a low logic that protects the memory and RDAC register is not affected by future writing operations. In this mode, EEMEM and RDAC read the operation normally. When the writing protection is enabled, the command 1 (from EEMEM to RDAC) and command 7 (reset) work normally, allowing RDAC to set it from EEMEM to RDAC registers.

I2C compatible 2 -line serial bus

The first byte of AD5253/AD5254 is from address bytes (see Figure 24 and Figure 25) Essence It has a 7 -bit address and a R/W bit. From the 5 mSB of the machine address to 01011, the following 2 LSB from AD1 and AThe state of the D0 foot is determined. AD1 and AD0 allow users to place up to four AD5253/AD5254 on one bus. 2 Line IC serial bus protocol operation is as follows:

AD5253/AD5254 can be controlled by the serial bus compatible with ICs and used as a serial bus compatible with ICs and used as a serial bus compatible with ICs and used as a serial bus compatible with ICs and used as a serial bus compatible with IC, and used as a serial bus compatible with IC Connect from the device to the bus. 2 Line IC serial bus protocol is as follows (see Figure 33 and Figure 34):

1. The host starts the data transmission by establishing a startup condition. To. The following bytes are composed of 5 MSBs that are defined as 01011 from 01011. The next two are AD1 and AD0, the IC device address position. According to its AD1 and AD0 -bit state, it can be in the same bus 2. The last LSB (R/W bit) determines whether the data is read from the device or the device.

The address corresponds to the SDA cable lowering the SDA cable (this is called the confirmation bit) through the machine that sends the address during the ninth bell pulse period. At this stage, all other devices on the bus remain free, and the selected device waits for the data to write or read its serial register.

2. In the writing mode (except when the EEMEM is restored to the RDAC register), there is a instruction byte from behind the address byte. MSB command/registration marked by the instruction byte. MSB 1 Enlightenment command instruction byte; MSB 0 enables conventional registers to write.

The third MSB of the instruction byte to win the bid to EE/RDAC is True only when MSB 0 or in a regular writing mode. EE enables EEMEM registers and RDAC registers are enabled. 5 LSB, A4 to A0, designed the address of EEMEM and RDAC registers; see Figure 27 and Figure 28. When MSB 1 or is in the command mode, the four bits behind MSB are C3 to C1, corresponding to 12 pre -defined EEMEM controls and quick commands; there are four factors retained commands. 3 LSB-A2, A1, and A0 are 4-channel RDAC addresses (see Figure 31). After confirming instruction bytes, the last byte in the writing mode is data byte. The data is transmitted through serial bus with the order of 9 clock pulse (after 8 data bit). The conversion of the SDA line must occur at the low period of the SCL and maintain stability at the high period of SCL (Figure 33).

3. In the current reading mode, the RDAC0 data byte follows the confirmation of the bytes of the machine. After confirming, RDAC1 follows, and then RDAC2, which is pushed according to this (there is a little difference in the WRITE mode, the last

eight representative of the data position of the data of RDAC3 follows a no response position). Similarly, the transition on the SDA line must occur at the low period of the SCL and maintain stability at the high period of SCL (see Figure 34)Essence Another reading method, random reading method, as shown in Figure 30.

4. When all the data bit has been read or writes, the host will establish a stop condition. The stop condition is defined as a conversion from low to high on the SDA line when SCL is high. In the writing mode, the host pulls the SDA cable to high during the 10 clock pulse to establish a stop condition (Figure 33). In the reading mode, the main control is not recognized to the ninth hour pulse, that is, the SDA line remains high. Then, the main device makes the SDA cable lower before the 10 clock pulse, which will become higher to establish a stop condition (Figure 34).

Operation theory

AD5253/AD5254 is a four -channel digital potentiometer with 1 kΩ, 10 kΩ, 50 kΩ or 100 kΩ, and allows 64/256 to linear resistance levels. AD5253/AD5254 uses a dual -door CMOSEEPROM technology to allow storage resistance settings and user -defined data in EEMEM registers. EEMEM is non -prone, so settings remain unchanged during power off. The RDAC wiper is set up from a non -easy -to -sex memory settings during the device power period, and can also be recovered at any time during operation.

AD5253/AD5254 resistor wiper position is determined by the RDAC register content. The role of the RDAC register is similar to that of the notebook register, allowing infinite changes in the resistance settings. You can use the serial IC interface of the device to change the RDAC register content. Discuss the format of the data word and the command of the programming RDAC register in the IC interface.

The four RDAC registers have the corresponding EEMEM memory position and provide non -easy -to -sex storage settings set by the position settings of the resistance wiper. AD5253/AD5254 provides commands to store RDAC register content to their respective EEMEM memory positions. In the subsequent power sequence, the RDAC register will automatically load the stored value.

Whenever EEMEM is written into operation, the device activates the internal charge pump and increases the bias voltage of the EEMEM unit gate to a higher level; this will actually erase the current content in the EEMEM register And allow new content to be stored later. Save data to the EEMEM register will consume a current of about 35ma and last about 26ms. Due to the charge pump operation, all RDAC channels may experience noise coupling during EEMEM.

The EEMEM recovery time during power -on or operation is about 300 microseconds. Please note that the refresh time of the power -to -power EEMEM depends on the speed of V's final value. Therefore, any power supply voltage decouple capacitor limits the recovery time of EEMEM during the power period. Figure 20 shows the power -based configuration file, where V, without any decoupling electric container connected to it, is a digital signal application. Before restoring EEMEM content, the device will initially take RDAC reset to MIDSCALE.

In addition, the user should immediately emit the NOP command 0 after the EEMEM is restored to the RDAC to minimize the power current loss. Reading user data directly from EEMEM does not require similar NOP commands.

In addition to moving data between RDAC registers and EEMEM memory, AD5253/AD5254 also provides other fast commands to facilitate user programming needs, as shown in Table 11.

Linear increasing and decreasing command

Increase and reduction command (#10,#11,#5,#6) Application is very useful. These commands simplify the micro -controller software coding by allowing the controller to only increase or decrease the command to the AD5253/AD5254 or decreased command. Adjustment can point to a single RDAC or all four RDACs.

± 6 decibel adjustment (double/minus semi -scraper settings)

AD5253/AD5254 to move the contents of the register to the left/to the right to increase the operation/decrease, adjust the position of the RDAC wiper position ± 6 dB. Commands 3, 4, 8, and 9 can be used in synchronization or asynchronous to increasing or decreased wiper positions with 6DB steps.

Increasing the position of the wiper+6DB is actually twice the value of the RDAC register, and reducing -6DB is half of the register content. Internally, the AD5253/AD5254 uses the shift register to move left and right shift to achieve an increase or decrease of ± 6 decibels. The maximum adjustment times starting from the increase of zero scale and the reduction of the full scale is 9 steps and 8 steps, respectively. These functions are very useful for various audio/video level adjustments, especially the white LED brightness settings. In this setting, human visual response is more sensitive.

Digital input/output configuration

SDA is a digital input/output, with a way to open the MOSFET, which requires a pull -up resistor to perform correct communication. On the other hand, SCL and WP are digital input with pull -up resistance. When the driver signal is lower than V.SCL, it is recommended to minimize the cross -conduction of MOSFET and the WP with ESD protection diode, as shown in Figure 35 and Figure 36 Essence

If the protection function is not used. If WP keeps floating, the internal current source will be pulled down to enable and write protection. In the application where the device is not often programmed, this allowed component to be written by default after any disposable factory programming or on -site calibration, without using a plate -loading resistor. Because all these inputs have protected diodes, their signal levels must not be greater than V to prevent the positive bias of the diode.

There are multiple devices on a bus

AD5253/AD5254 with two addressing pin AD1 and AD0, allowing up to four AD5253/AD5254 on one IC bus. To achieve this, to first define the status of AD1 and AD0 on each device. For example, as shown in Table 12 and Figure 37. In IC programming, each device is issued different from the machine address 01011 (AD1) (AD0) to complete the addressing.

In the wireless base station intelligent antenna system that requires the digital potentiometer array to biased power amplifier, additional decoders, switches and I/O bus can be used to address A large amount of AD5253/AD5254, as shown in Figure 38. For example, to communicate with a total of 16 devices, 4 decoders and 16 set switches are required (4 groups shown in Figure 36). Two I/O bus as a public input of four 2 × 4 decoders, and select four sets of output in each combination. Since the output of the four groups of switching is unique, as shown in Figure 38, the specific device is designed by the proper IC programming address, and is defined from the machine address to 01011 (AD1) (AD0). This operation allows one of the 16 devices to be addressing, provided that the input of the two decoders does not change. Once the operation of the device is specified, the input of the decoder can be changed.

Terminal voltage operating range

AD5253/AD5254 is protected by internal ESD diode; these diode also set up the boundary of the terminal work voltage. The positive signal that appears on the terminal A, B, or W is restrained by the positive bias diode. Similarly, the negative signal that is more negative than V on the terminal A, B or W is also restrained (see Figure 39). In practice, users should not operate the voltage between V, V and V higher than V to V, but V, V and V have no polarity limit.

Powering and power -off order

Because ESD protects the diode in the ESD, the voltage compliance at the terminal A, B and W (Figure 39), so Before applying any voltage to the terminal A, B and W, it is important to power V/V. Otherwise, the diode will have positive bias, which makes V/V unintentionally power -on and may affect the rest of the user's circuit. Similarly, V/V should be finally closed. The ideal power sequence is as follows: GND, V, V, digital input and V/V/V. As long as the order of power after V/V, the order of V, V, V and digital input is not important.

Layout and power supply bias

The layout design with compact and minimum lead length is always a good approach. The wire of the input terminal should be as direct as possible, and the wire length should be the smallest. The grounding path should have low resistance and low inductance.

Similarly, using high -quality capacitors bypass power is also a good approach. Low ESR should be used at the power supply (Equivalent series resistance) 1 μF to 10 μF 钽 or electrolytic capacitors to minimize any transient interference and filter low -frequency ripples. Figure 40 illustrates the basic power sources of AD5253/AD5254.

The ground pins of AD5253/AD5254 are mainly used for digital grounding reference. In order to minimize the digital ground bounce, the AD5253/AD5254 grounded terminal should be remotely connected to public ground (see Figure 40).

Digital potentiometer operation

The structural design of RDAC is used to simulate the performance of the mechanical potentiometer. RDAC contains a set of resistance segments, a set of simulated switch as a wiper connection as a resistance array. Points are the resolution of the device. For example, the AD5253/AD5254 simulation 64/256 connection points with resistance R with 64/256 allow it to provide it with settings more than 1.5%/0.4%. FIG. 41 provides an equivalent diagram between the connection between three terminals that forms a channel of RDAC. Switch SW A and SWB are always open, and the switch SW (0) to SW (2) is opened one by one, depending on the settings of the data bit decoding. Because the switch is not ideal, there is a 75Ω wiper resistor R. The wiper resistor is a function of the power supply voltage and temperature; the lower power supply voltage and higher temperature will cause higher wiper resistors.

The programmable resistor operation

If the W-to-B or W-TO-A terminal is used as a variable resistor, the unused terminal You can open a road or short circuit; this operation is called a resistor mode (see Figure 42). The resistance tolerance can be within the range of ± 20%.

The nominal resistor of AD5253/AD5254 has 64/256 contacts, connected through the wiper terminal and B terminal contacts. The 6/8 -bit datawords in the RDAC register are decoded to select one of the 64/256 settings. The first connection of the wiper starts with the B terminal of the data 0x00. The tentacle resistance R connected to this B terminal is 75Ω, which has nothing to do with the nominal resistor. The second connection (AD5253 10 kΩ part) is the first tap point of the data 0x01, where R 231Ω [r r/64+r 156Ω+75Ω], which is pushed by this. Every time a LSB data value is added, the wiper will move up the resistance ladder until the last tap reaches R 9893Ω. The simplified picture of the equivalent RDAC circuit is shown in Figure 41.

The general equation of determining that the digital programming output resistance between W and B is:

Among them, D is the decimal equivalent effect contained in the RDAC lock memory. Data, R is the nominal end -to -end resistance.

ExampleFor example, the R value shown in Table 13 can be found on the AD5253 10 KΩ parts.

Note that under the condition of zero scale, 75Ω limited wiper resistance exists. In this state, you should pay attention to restricting the current instrument between W and B to restrict the continuous continuity of no more than ± 5 mA, and the total resistance is 1 kΩ or ± 20 mm of the pulse to avoid degeneration or possible damage to the internal switch contact.

Similar to the mechanical potentiometer, the RDAC resistance between the wiper W and the terminal A also generates a digital control complementary resistor R. When using these terminals, the B terminal can be opened. Set the resistance value of R starts with the maximum value of the resistance, and decreases as the data value loaded in the lock memory (see Figure 41). The general equation of this operation is:

In a given device, the typical distribution of R in each channel is about ± about ± ± 0.15%. On the other hand, the matching of equipment and equipment depends on the process batch, and the tolerance is ± 20%.

The programmable potentiometer operation

If all three terminals are used, the operation is called the potential mode, and the most common configuration is the operation (see Figure 44).

If the wiper resistance is ignored, the transmission function is:

A more accurate calculation, including the wiper resistance effect , Generate:

Among them, 2 are steps. Unlike the operation with a high tolerance in the variable -resistor mode, the operation in the potentiometer mode is almost a D/2 ratio function, and the error caused by the R item is relatively small. As a result, the tolerance effect is almost canceled. Similarly, the ratio adjustment also reduces the temperature coefficient effect to 50 ppm/℃, except in the low -value code dominated by R.

The potentiometer mode operation includes other applications, such as the op amp input, the feedback resistance network, and other electrical compressed applications. If | V |, | V | and | V | No more than V-TO-V, then A, W and B terminals can actually be input or output terminals.

Application

RGB LED LCD backlit controller

high power ( gt; 1W) RGB LED has significantly improved efficiency and cost, it is expected to be in the near future. In the future, CCFLS (cold cathode fluorescent lamp) will become a backlight for high -end LCD panels. Unlike the traditional LED, high -power LED has a forward voltage of 2V to 4V, and consumes more than 350mA under maximum brightness. LED brightness is a linear function of the conduction current instead of forward voltage. In order to increase the brightness of the given color, multiple LEDs can be connected in series instead of parallel to achieve uniform brightness. For example, three in series configurationA red LED requires an average voltage balance of 6 V to 12 V, but the circuit operation requires current control. As a result, FIG. 45 shows the implementation of the high -power RGB LED controller of the digital potentiometer AD5254, boost regulator, operational amplifier and power MOSFET.

ADP1610 (U2 in Figure 45) is a adjustable supercharged regulator, which is adjusted by RDAC3 of AD5254. Such outputs should be set enough to work normally, but it is low enough to save electricity. The 1.2V band band benchmark of ADP1610 is buffered to provide the benchmark level of the voltage distributor set by RDAC0 to RDAC2 and resistor R2 to R4 from AD5254. For example, by adjusting the RDAC0 of AD5254, the required voltage appears on the sensor. The output settings of R and U2 are correct. The op amp and power MOSFET N1 will do anything necessary to adjust the current of the ring. Therefore, the current of the sensor and the red LED is:

requires R8 to prevent oscillation.

In addition to level 256 adjustable current/brightness, users can also apply PWM signals on U3's SD pins to obtain higher brightness resolution or higher power efficiency.

The size of the shape