AS1106 and AS110...

  • 2022-09-21 17:24:28

AS1106 and AS1107 are 8 -bit LED display drives

Main features

★ ★ 10MHz SPI-, QSPI-, micro-line compatible serial I/O

★ A single LED segment control

★ Flash control (can Synchronization across multiple drives)

★ Scripture or BCD code/no code position selection

★ 3 Weian low power turnover current (typical; retain data)

[ 123] ★ Open Ring extremely low working current 0.5mA

★ Digital and simulation brightness control

★ When the power is turned on, it is displayed as a blank

★ Drive the communist cathode LED display [ 123]

★ Low EMI low conversion rate limit segment drive (

AS1107

) ★ Power supply voltage range: 2.7 ~ 5.5V

Software reset

★ Optional outer clock

★ Packaging:

-24 pinching

-24 needle SOIC

Application

]

AS1106

and AS1107 are shape map display, instrument board and instrument, LED matrix display, dot matrix display, set -top box, white goods, professional audio equipment, medical equipment, industrial control and instrument panel. General description

AS1106 and AS1107 are compact display drivers, which can be used for up to 8 -bit digital display. These devices can be programmed through SPI, QSPI and Microw Ire and traditional 4 -line serial interfaces.

These devices include an integrated BCD code B/HEX decoder, multi -road scanning circuit, segment and display drive, and 64 -bit memory. The memory storage LED settings are not required to be re -programmed by continuous device.

Each paragraph can address and update separately. Only an external resistor (RSET) can set the current through the LED display. LED brightness can be controlled by simulation or digital.

These devices can be programmed using internal code -b/hexadecimal decoders to display numbers or directly address each paragraph.

AS1106 and AS1107 have a typical 3 Weian extremely low -level interruption current and working current less than 500 Weian. The number of numbers can be programmed, the device can be reset through software, and also supports external clocks. In addition, the flickering of segments can be synchronized across multiple drives.

There are several test modes that can be used for simple application debugging.

These devices are encapsulated by 24 -shot DIP and 24 -pin SOIC.

Figure 1: Typical Application Figure

Typical operating characteristics

VDD 5V, RSET 9.53kΩ, TAMB 25 ° C (unless there are other regulations).

详细说明

AS1106对AS1107

AS1106和AS1107是相同的,除了两个特点:

The conversion rate of the AS1107 drive is limited to reduce electromagnetic interference (EMI).

AS1107 serial interface is completely compatible with SPI (can be programmed as AS1106).

Serial addressing format

The programming of AS1106/AS1107 is completed by the internal register of the device (see the numbers and control registers on page 8) through the 4 -line serial interface. The programming sequence consists of 16 -bit bags listed in Table 5.

The data rose along with the CLK signal and moved into the internal 16 -bit register. As the Load/CSN signal rises, the data is locked to the digital or control registers. The load/CSN signal must be higher after the edge of the 16th rising clock.

Load/CSN signals can also appear later, but this must occur before the next rising edge of CLK, otherwise the data will be lost. The contents of the internal displacement register are applied to the pipefoot output after the 16.5 clock cycle. Data decreases along the time.

The first 4 digits (D15: D12) are not important. Bit D11: D8 contains register address, bit D7: D0 contains data. The first is D15, the most effective (MSB). The exact time is shown in Figure 11.

Initial power

At the initial power, the AS1106/AS1107 register was reset to its silent value, displayed as blank, and the device entered the shutdown mode. At this time, all registers should be programmed to run normally.

Note: The default settings are allowed to scan only one number; the internal decoder is disabled, and the strength control register (see page 11) is set to minimum value.

The shutdown mode

AS1106/AS1107 device has a shutdown mode and consumes only 10 A (maximum) current. Close mode enter the closing register (see Table 7). For AS1106, at this point, all sections of current sources are pulled to the ground, and all digital drives are connected to VDD, so that all sections are blocked. The behavior of AS1107 is the same, except for the driver is high impedance.

Note: In the shutdown mode, the digital register keeps its data.

The shutdown mode can be used as a way to reduce power consumption, or it can also be used for itGenerate flash display (repeatedly enter and exit the shutdown mode). For the minimum power current in the shutdown mode, the logic input should be GND or VDD (CMOS logic level).

These devices usually take 250 seconds to exit the shutdown mode. In the shutdown mode, AS1106/AS1107 is completely programmable. Only show the test mode (see page 10) to cover the shutdown mode.

When entering or exiting the closure mode, when the 1st register position D7 (page 9) 0 is turned off, the function register is reset to its silent value (all 0).

Note: If the AS1106/AS1107 is used with the external clock, when it is written to close the register, the closing the register position D7 should be set to 1.

Digital and control registers

AS1106/AS1107 device contains 8 -bit registers and 6 control registers, as shown in Table 6. All registers use 4 -bit address characters for selection and communicate through serial interfaces.

The registers of the digital register are implemented with 64 -bit memory on the film. Each number can be directly controlled without reusing the entire register content.

The registers of the control register include decoding mode, display strength, scanning position, shutdown, display testing and function selection registers.

1. When the register position D7 1 is turned off, when entering or off -off mode, the function register remains unchanged.

Shut off the register (0xxc)

The shutter controller controls AS1106/AS1107 shutdown mode (see the shutdown mode of page 8).

Decoding enable register (0xx9)

Decipher enable the register to set the decoding mode. BCD/hexadecimal decoding (BCD code character 0: 9, E, H, L, P, and-or hexadecimal code character 0: 9 and A: F) )choose. Decoding enable register is used to select the decoding mode or not decoding each number. Decoding each bit in the enable register corresponds to its respective display bits (ie, bit D0 corresponds to bit 0, bit D1 corresponds to bit 1, etc.). Table 9 lists some examples of possible settings of the order of the register.

Note: The logic is allowed to decoding, and the logic is completely bypassed the decoder.

When using the decoding mode, the decoder only views the second half (bit D3: D0) of the data in the digital register, and ignores bit D6: D4. The bit D7 is independent of the decimal setting (SEG DP) independent of the decoder, and it is positive logic (bit D7 1 to open the decimal point). Table 9 lists code B fonts; Table 10 lists hexadecimal fonts.

When the decoding mode is not selected, the digital registerData bit D7: D0 corresponds to the segment line of AS1106/AS1107. Table 11 shows the 1: 1 pair of each data bit with the corresponding line segment.

Display test register (0xxf)

AS1106/AS1107 device can work in two modes in two modes : Normal mode and display test mode. In the display test mode, all LEDs are opened in the maximum brightness (the duty ratio is 15/16 (AS1106) or 31/32 (AS1107). 123] Note: Keep all settings of numbers and control registers.

strength control register (0xxa)

The brightness of the display can be controlled by using strength control registers through strength control registers Digital mode and use of RSET simulation methods to control (see page 13 to select RSET resistance values and use external drives).

Display the brightness controlled by the integrated pulse width, which is controlled by the intensive control register by the strength control register. Low half -byte control. The modulator reduces the average segmented current at 162 steps from the maximum value of 31/32 to the peak current set set by RSET (for AS1107 for 15/16 to 1/16). 123]

Scanning restricted register (0x0b)

Scanning restricted register control the number to be displayed. When all 8 digits are displayed, the update frequency is usually 800Hz. If If the number of displaying bits is reduced, the update frequency increases. The frequency can be calculated with 8FOSC/N, where n is the digit. Since the number of displayed digits will affect the brightness, the RSET should be adjusted accordingly. 15 lists less use than less useful use. The maximum current allowed when 4 digits.

Note: In order to avoid the difference in brightness, this register is not used in the blank display part (front guide zero).

Function register (0xxe)

Function register is used to enable various functions, including switching the device to the external clock mode, application external resetting, selecting code B or hexadecimal decoding, enabling or disable flashing, opening, enabling use Or disable the SPI compatibility interface (only AS1106), set the flicker rate and reset the flicker timing.

Note: When power is powered, the function register is initialized to 0.

[ 123] No operating register (0xx0)

When multiple AS1106 or AS1107 device grade supports more than 8 -digit display, the unwanted register. The feet are connected to the next AS1106/AS1107 DIN (see page 15 Figure 13). Load/CSN and CLK signals are connected to all devices.

For example, if the five device grade couplets, in order to perform writing operations for the fifth device, the order must be followed by four non -operating commands. When the Load/CSN signal becomes higher, all the displacement registers are locked. The first four devices will not receive the operation command. Only the fifth device will receive the expected operation command and then update its register.

Typical application

Power bypass and wiring

In order to achieve the best performance, AS1106/AS1107 should be placed in a place very close to the LED display, with minimal electromagnetic electromagnetic electromagnetic The effects of interference and routing inductance.

In addition, it is recommended to connect a 10F electrolytic capacitor between the pin VDD and GND and a 0.1F ceramic capacitor to avoid power ripples (see page 15 Figure 13).

Note: Two ground pins must be grounded.

Selection of RSET resistance values and external drivers

The brightness of the display segment is controlled by RSET. The current flowing between VDD and ISET defines the current flowing through the LED.

The current current is about 200 times the ISET current. Table 18-22 gives a typical RSET value of different sections of current, working voltage, and LED voltage drop (VLED). The maximum current that can be driven by AS1106/AS1107 device is 40 mAh. If a higher current is required, the external drive must be used. In this case, the device is no longer required to drive the high current.

When the device is only driven by a few numbers, Table 15 specifies the maximum current, and RSET must be set accordingly.

Note: The brightness of the display can also be logically controlled (see the strength control register (0xxa) on page 11).

计算功耗

AS1106/AS1107的功耗上限(PD)由以下公式确定:[123 ]

Among them: VDD is the power supply voltage.

The duty occupation ratio is the duty cycle set by the strength register.

n is the number of drivers (the worst is 8) VLED is the positive voltage of LED. ] Therefore, for the pdip package θja +75 ° C/W (from Table 23), the maximum TAMB allowed as follows:

Mercy: Environmental temperature +69.4 ° C.

The TAMB limit of the SO package in the above scattered example is +58.6 ° C.

8x8 LED dot matrix driver

Application examples in FIG. 13 display AS1106 as 8x8 LED dot -matrix drive.

The LED lamp column has a public cathode and connected to the DIG0: 7 output. Line connect to the segment driver. Each of the 64 LEDs can be addressing separately. Select the number selection in Table 6 in Table 6.

Decoding enable register must be set to 00000000, as described in Table 9 8. The single LED in the column can be found in Table 11 in Table 11, where the bit D0 corresponds to paragraph G, and the bit D7 corresponds to segment DP.

Note: For a majority point matrix, multiple AS1106 devices must be connected to the level.

Class Link Driver

FIG. 4 The example of the 4 -line microprocessor interface driver 2 dot matrix numbers. All scanning restrictions should be set to the same value, so that one display will not look brighter than another.

For example, to display a 12 -digit number, please set the two scan restricted registers to display 6 digits so that each number of the two displays has a 1/6 duty ratio. If 11 bits are required, set the two scan restricted registers to display 6 digits and keep an uninterrupted connection. Otherwise, if one driver is set to display 6 digits, and the other driver is set to display 5 digits, one monitor will be displayed lighter because the duty cycle of each number is 1/5, and the other monitor is The duty ratio is 1/6.

Note: For more information, see the operating register (0xx0) on page 12.

Packaging diagram and label

AS1106 and AS1107 have 24 -needle DIP and 24 -pin SOIC packaging.

24 -needle impretion pack

24 -needle SOIC packaging

Order information [ 123]

AS1106 and AS1107 have 24 -needle DIP and 24 -pin SOIC packaging.