Features

Pixels that support maximum 165MHz (including 1080p and wuxga)

compliance with digital video interface (DVI) specifications (1) real color, 24 -bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bit/ bite/ bit/ bit/ bit/ bit/ bite/ bit/ bit/ bit/ bit/ bit/ bitter Pixels, 16.7 million colors, every clock 1 or 2 pixels

Laser trimming internal terminal resistor used for the best fixed impedance matching

can tolerate the deviation of a pixel clock cycle

4 × over -sampling

Reduce power consumption -1.8 V core operation, 3.3 v I/O and power supply (2)

Use time cross -pixel output reduces ground rebound

] Use Ti PowerPad, low noise, high power consumption #8482; packaging

Advanced technologies using Ti 0.18-micron EPIC-5 CMOS process

TFP401A

Have Hsync with hsync Judging Anti -disturbance (3)

(1) Digital visual interface specification (DVI) is an industry standard for digital display high -speed digital connection developed by the digital display working group (DDWG).

TPF401 and TFP401A conform to the DVI specification version. 1.0 points.

(2) TFP401/401A has an internal voltage regulator, which provides a 1.8 V core power supply from the external 3.3 V power supply.

(3) TFP401A uses additional circuits, which introduces

Application

HD TV

HD PC display

Digital Video

HD projector

DVI/HDMI receiver (only HDMI video)

Instructions

Texas instrument TFP401 and TFP401A are Ti Panelbus #8482 ; Tablet display products, end -to -end DVI 1.0 compatible solutions comprehensive series. TFP401/401A is mainly aimed at desktop LCD monitors and digital projectors, and is suitable for any design that requires high -speed digital interfaces.

TFP401 and TFP401A support the display resolution of up to 1080P and Wuxga in the 24 -bit real color pixel format. TFP401/401A provides design flexibility, which can drive one or two pixels per clock, support TFT or DSTN panels, and provide a time staggered pixel output option to reduce the ground rebound.

Werpad's advanced packaging technology brings first -class power consumption, area and ultra -low ground electricitysense.

TFP401 and TFP401 A combine Panelbus circuit innovation and TI's advanced 0.18 micron EPIC-5CMOS process technology, as well as Ti PowerPad packaging technology, realize reliable, low power consumption, low noise, high-speed digital interface solution solutions Essence

needle configuration and function

Overview

TFP401/401A is a TMDS digital receiver compatible with digital visual interface (DVI) compatible. Receive and decoding the RGB pixel data stream of TMDS coding in the digital tablet display system. In the digital display system, the host (usually PC or workstation) contains TMDS compatible transmitters. The transmitter receives 24 -bit pixel data and appropriate control signals, and encodes it into it to transmit it to the display device through the twisted pair line to the display device. High -speed low -voltage differential series. The display device is usually a tablet display. The receiver compatible with TMDS (such as TI TFP401/401A) requires serial streaming to return the same 24 -bit pixel data and control signals from the host. The decoding data then can be directly applied to the tablet drive circuit to generate images on the display. Because the distance between the host and the display can reach or exceed 5 meters, it is best to use the serial transmission of pixel data. In order to support the modern display resolution of the highest UXGA, a high -bandwidth receiver with good jitter and tilt tolerance needs to be needed.

Function box diagram

Feature description

TMDS pixel data and control signal coding

tmds represents the conversion minimization difference points Signal. During the given time, only one of the two pixels of the Pixel Pixel may be transmitted. The transmitter maintains the first 1 and 0 running counts sent before, and sends characters that minimize the number of conversion times to minimize the number of conversion times to balance the DC balance of the transmission line.

Three TMDS channels are used to receive RGB pixel data during the event display time de high. These three channels also receive control signals, Hsync, Vsync, and user -defined control signal CTL [3: 1]. These control signals are received during non -activity display or hidden periods. The hidden time is when de low. Table 1 maps the received input data to the corresponding TMDS input channel in the DVI compatibility system.

TFP401/401A clock and data synchronization

TFP401/401A from DVI transmitter receiving clock reference from the dvi transmitter with a pixel TPIX period. The frequency of this clock is also called pixel rate. Because the TMDS encoding data on the RX [2: 0] contains 10 bits of 8 -bit pixels, the RX [2: 0] serial ratio is 10 times the pixel rate. For example, UXGA points supporting the 60Hz refresh rateThe pixel rate required for the resolution is 165MHz. The TMDS serial ratio is 10 times the pixel rate, that is, 1.65GB/s. Because this high-speed number ratio is transmitted at the independent channel (or twisted line) of three long distances (3-5 meters), the phase synchronization between the data flow and the input clock cannot be guaranteed. In addition, the deviation between the three data channels is also common. TFP401/401A uses a 4 × excessive sampling scheme input data stream to achieve a reliable synchronization with the tilt of the channel with the 1-TPIX channel. Because reflexes and external noise sources accumulated on clocks and data cables are also typical of high -speed serial data transmission; therefore, TFP401/401A design has a high jitter tolerance.

The input clock of TFP401/401A is adjusted by the lock ring (PLL) to eliminate the high frequency jitter of the clock. PLL provides four different phase 10 × clock outputs to locate and synchronize TMDS data streams (4 × over -sampling). During the display period, pixel data was minimized by the transition, and in the blank area, the control data was coded to maximize the transition. The transmitter that meets the DVI standard needs to be launched blank in the shortest time period (128 TPIX) to ensure that there is enough time to synchronize data when the receiver saw the conversion maximum code. When data transmission maximizes, synchronization during the blank period can ensure reliable data bit boundary detection. For each of the three input channels, synchronization with the data stream is unique, and as long as the link remains active, it is kept synchronized.

TFP401/401A TMDS input level and input impedance matching

TFP401/401A receiver TMDS input has a fixed AVDD single -end terminal. TFP401/401A uses a laser fine -tuning process for internal optimization to accurately fix the impedance to 50Ω. The device works normally when or without a resistor on the external pins, so it is compatible with the current socket. Fixed impedance eliminates the needs of external resistance, while providing optimal impedance matching with the standard 50ΩDVI cable.

The concept diagram of the connection of DVI transmitter and TFP401/401A receiver. The transmitter is driven by a current source, which is usually implemented by the leakage output drive. The internal resistor that matches the cable impedance at the TFP401/401A input is provided to the pull -up of AVDD. Of course, when the transmitter is broken and the TFP401/401A DVI input keeps unconnected, the TFP401/401A receiver input is pulled up to AVDD. TFP401/401A is designed to respond to differential signal fluctuations that respond to 150 mv to 1.56 V, and the common mode voltage range is (AVDD -300 MV) to (AVDD -37 MV).

DVI Titanium TFP401/401A

The transmitter receiver

TFP401A has HSYNC jitter resistance

Several DVI transmitters on the market will have a jitter to the transmitted Hsync and Vsync signals during the TMDS encryption process. The Hsync signal can move a pixel position (a clock) from the nominal direction in any direction, resulting in up to two HSYNC mobile cycles. This jitter will be passed to the DVI receiver. If the position of Hsync continues to move, the receiver may lose the time -time tracking of input, which will cause pixel noise on the display. Therefore, DVI compatible receivers with HSYNC jitter resistance are applied to all monitors that may be connected to a host PC with Hsync jitter transmitter.

TFP401A integrates the Hsync regeneration circuit to provide seamless interfaces for these unsatisfactory transmitters. The position of the data enlightenment (DE) signal is always relative to the data fixed, and it has nothing to do with the position of Hsync. TFP401A receiver uses DE and clock signals to rebuild stable vertical and horizontal synchronization signals. The circuit filter the HSYNC output of the receiver, and Hsync is moved to the nearest eighth border to generate a stable output about data, which ensures the accurate data synchronization of the input terminal of the time controller.

This Hsync regeneration circuit is transparent to the monitor, even if

Hsync is stable. For example, the Panelbus cable that complies with the DVI 1.0 standard (such as TFP6422 and TFP420) does not have HSYNC jitter problems. TFP401A can work normally on a compatible or non -compatible launch machine. In contrast, TFP401 is very suitable for customers who control the design and transmission part, such as bundling system manufacturers and internal monitor (DVI connection between monitor and panel modules).

Equipment function mode

TFP401/401A operating mode

tfp401/401A provides configurable options or operations to the system designer by providing system designers that can be configured options or operations to operate to the system designer. Models to support different system architectures, thereby providing the flexibility and value of system design. Table 2 outlines various panel modes that can be supported and appropriate external control pins.

The output drive is broken

(PDO low). Polging PDO will enable all output drives (except CTL1 and SCDT) into high impedance state. The SCDT output indicator link has been disabled or the link is not activated. It can be directly bound to the PDO input to disable the output driver when the link is not activated or the cable is disconnected. The internal pull on the PDO tube feet will default TFP401/401A to the normal non -non -broken power output drive mode (if not connected).

Drive strength

(ST high driving strength is high, ST low -drive strength is low). TFP401/401A allows the selection of output driving strength on data, control and ODCK output. For the value of IOH and IOL current drives in a given ST state, see the DC Power Properties. The high output driving strength provides about twice the driver of the low output driver.

Time staggered pixel output

This option is only applicable to 2 pixel/clock mode (PIXS high). Set stag Low Timestaggggg to output the even and odd pixels to reduce the instantaneous current surge from the power supply. According to the layout and design of the PCB, this helps reduce the ground rebound and power noise of the system. Time is delayed in 2 pixels/clock mode, and the pixels are delayed from 0.25tcip from the lock edge of ODCK. (TCIP is a period of ODCK. When in the 2Pixel/Clock mode, the ODCK cycle is 2tpix).

According to the system limitation of the output load, pixel rate, panel input architecture, and board cost, TFP401/401A driving strength and interlaced pixel options allow the system power noise, ground rebound, and EMI.

Power Management

TFP401/401A provides several system power management functions.

The output drive of the driver (PDO low) is a intermediate mode that provides a variety of uses. In this mode, all output drives except SCDT and CTL1 are driven to high impedance state, while the remaining device circuits remain activated.

TFP401/401A Powerment (PD LOW) is a complete power loss because it offses the digital core, analog circuit and output drive. All output drivers are in HI-Z. Except for PD input, all inputs are disabled. Before the PD was pulled up, TFP401/401A did not respond to any numbers or simulated inputs.

PDO and PD have internal pulling, so if they are not connected, they will default to the normal working mode of TFP401/401A.

Synchronous detection

TFP401/401A provides an output SCDT to indicate the link activity. TFP401/401A monitor the activities on DE to determine whether the link is in a state of activity. When a million (1E6) pixel clock cycle is not transformed on DE, TFP401/401A regards links as non -activated, and SCDT is driven low. When the SCDT is low, if two are detected in the 1600 pixel clock cycle, the link is considered to be in active, and SCDT is pulled up.

SCDT can be used to send signals to the system power management circuit so that the system is considered to start power off when the link is regarded as non -activity. SCDT can also be directly connected to TFP401/401A PDO input to turn off the output drive when the link is not activated. It is not recommended to use the SCDT driver PD input, because once the power is completely disconnected, the simulation input will be ignored, and the SCDT state will not change. It is best to use the external system power management circuit to drive local discharge.

Application information

TFP401 is a DVI (digital visual interface) compatible digital receiver. It is used for the RGB pixel data stream of the digital tablet display system receiving and decoding TMDS encoding. Digital display system host, usually PC or workstation, contains a DVI compatible transmitter. It receives 24 -bit pixel data and appropriate control signals, and encodes them into a high -speed low -pressure differential string that is suitable Xingbi special flow. The display device is usually a tablet display. DVI compatible receivers like TI TFP401 will be decoded to decode serial ratio, so that it returns the same 24 -bit pixel data and control signals from the host. The decoding data then can be directly applied to the tablet drive circuit to generate images on the display. Because the distance between the host and the display can reach or exceed 5 meters, priority is preferred to use the serial transmission of pixel data. TFP401 will support the resolution of Gundam UXGA.

Typical application

Data and control signals

The tracking length of the data and control signal from the receiver's output should be as close as possible. The height of the trace is ~ 5X. Generally speaking, if possible, traces should also be less than 2.8 inches (can accept longer traces). Delay 85 × SQRT ER, where

ER 4.35

The relative dielectric constant of the 50%resin FR-4@1GHz

Delay 177 ps/inch (1 )

The rising edge length TR (picosecond) ÷ delay, of which

tr 3 nano second seconds

3000 PS ÷ 177 ps/inch

] 16.9 inches (2)

The maximum trajectory length of the rising edge ÷ 6 The maximum trajectory length of the concentrated circuit, of which

16.9 ÷ 6 2.8 inches (3)

]

Data and control signal design

Configuration option

TFP401 can be configured to multiple modes according to the required output format, such as 1 byte/clock, 2 bytes 2 bytes /Clock, down/rising clock edge. You can leave a placeholder for future configuration changes

Configuration option design

Power supply decoupled numbers, analog and PLL power must be separated from each other, so as to use it in order Avoid PLL and core electricalNoise

Power decoupling design

Application curve

Sometimes the panel does not support the same format as the graphical processor unit (GPU). In these cases, users must decide how to connect unused bits. Figure 22 and FIG. 23 shows that the 18 -bit GPU and 24 -bit LCD do not match, of which X " and "y " indicate the 2 LSB of the panel.

Power suggestion

Use solid ground plane and connect the ground plane with as many perfunctions as possible. This will provide a ideal return path for the current. Each power supply should be located on a separate separation of the power plane