Performance characteristics

6.25 NS instruction cycle time, up to 160 MIPS continuously perform; ADSP-218X series code compatible; easy-to-use algebraic grammar; single cycle instruction execution; two groups of calculations and memory instructions between the two groups and memory instructions between the two groups and memory instructions Single context switching; instruction cache allows in each instruction cycle; multi-functional instructions; the assembly line architecture supports efficient code execution; compiles C and C ++ architecture enhancement; code efficiency; Support; add registers and peripheral devices; flexible power management that users can choose; power -off and idle mode.

Integrated function

160k byte sheet RAM, configured to be 32K and 24 -bit; memory RAM and 32K 16 -bit memory RAM; double -bit memory for instructions and data storage; Independent Alu, Maketer/Cumulative Incurrency and Barrel; Dual 40 displacement calculation unit; battery; unified memory space allows flexible address allocation to use two independent DAG units; powerful program sequencer provides zero -cost cycle and cycle and Conditional instruction execution; enhanced interrupt controller programmable interruption priority and nested mode; system interface characteristics; host port with DMA function, for 8 or 16 bits of glue without glue; host interface; 16 -bit external memory interface, at most at most Support 16M characters; can address memory space; three full dual -work and multi -channel serial ports; support H.100 and up to 128 TDM channels, and optimize A rhythm and rhythmic pressure expansion for the telecommunications communication system; DMA's SPI compatibility port; UART port supported by DMA; 16 general I/O pins supported by integrated interrupts; three programmable intervals timer Function; any given time for high I/O throughput may be at most 11 DMA channels in the active state; guide ROM for automatic guidance on the outside; 8 or 16 -bit host equipment, SPI ROM or automatic audio detection UART; programmable lock phase loop supports 1 to 32 input frequency; multiplication operations, and can be changed during runtime; IEEE JTAG standard 1149.1 test access port supports films to simulation and system debugging; 2.5 v internal operations and 3.3 v I/O; 144 Lead LQFP and 144 fans BGA package.

General description

ADSP-2191m Digital signal processor is a digital signal processing (DSP) and other high-speed numbers Processing the application and optimized single -chip microcomputer.

ADSP-2191M will be the ADSP-219X series infrastructure (three computing units, two data address generators, and one program sequencer) and three serial ports, two SPI compatible ports, a UART port , A DMA controller, three programmable timers, universal programming signs pins, extensive interrupt functions and chip programs are combined, and data storage space.

ADSP-2191M architecture is compatible with the DSP code of the ADSP-218X series. Although these architectures are compatible, the ADSP-2191M architecture has many enhanced structures than the ADSP-218X architecture. The enhancement of the calculation unit, data address generator and program serial machine makes the ADSP-2191M more flexible and even more programmed.

The indirect addressing option provides the flexibility of addressing -pre -modification and post -modification of the pre -modification of an updated pre -modification, an immediate 8 -bit, two supplementary values, and the base address register Cycle buffer.

ADSP-2191M integrated 64K-character memory, which is 32K (24-bit) program RAM and 32K (16-bit) data RAM. It also provides a power -off circuit to reduce power consumption. ADSP-2191M offers 144 lead LQFP and 144 fans BGA packaging.

Make ADSP-2191M in a high-speed and low power CMOS process to operate at a 6.25ns instruction cycle (160 mIPS). Except for a single instruction, all instructions are executed in a processor.

ADSP-2191M flexible architecture and comprehensive instruction set support multiple parallel operations. For example, in a processor cycle, ADSP-2191M can:

Get an address for the next instruction

123] execute once or two data moves

update one or two data address pointers

These operations continue in the processor:

through two serial ports receiving and transmission data

from the host receiving and/or transmission data

[123 ] through UART receiving or transmission data

through two spi ports receiving or transmission data

access external memory interface

Reduce the timer

DSP core architecture

ADSP-2191M instruction set providing flexible data movement and multi-function (one or two data can be moved at one or two) instructions Essence Each word instruction can be executed within a processor cycle. ADSP-2191M assembly language uses algebraic syntax, which is convenient for coding and readability. A comprehensive development toolSupport program development.

The functional frame diagram of page 1 shows the architecture of the ADSP-219X core. It contains three independent computing units: ALU, Magic/Cumulator (MAC) and displacement. Calculate unit processing 16 -bit data from the register file, and has regulations that support multi -precision calculations. ALU performs a set of standard arithmetic and logical operations; it also supports the primitives. MAC executes single -period multiplication, multiplication/addition and multiplication/subtraction operations. MAC has two 40 cumulators, which helps overflow. The displacement execution logic and arithmetic displacement, standardization, outerization and derived index operations. The displacement can effectively implement digital format control, including multi -words and block floating point representations.

The register's usage rules affect the position of the input and the result in the calculation unit. For most operations, the data register of the calculation unit acts as a data register file, allowing any input or result register to provide inputs for calculation to any unit. For feedback operations, the calculation unit allows the output (result) of any unit to enter any unit in the next cycle. For conditional instructions or multi -functional instructions, the existence of data registers can provide restrictions on input or receiving results from each computing unit. For more information, see the ADSP-219X DSP instruction collection for reference.

The process of controlling instruction execution of a powerful program sequencer control instruction. SEQUENCER supports conditions jump, sub -routine call, and low interrupt overhead. Use the internal cycle counter and cycle stack, ADSP-2191M executes the cycle code with zero overhead; the maintenance cycle does not require an explicit jump instruction.

Two data address generators (DAG) provides addresses to obtain dual operations from data memory and program memory at the same time. Each DAG maintenance and update four 16 -bit address pointers. Whenever the pointer is used to access data (indirect addressing), it is modified in advance or after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -after -afters. The length value can be associated with each pointer to realize the automatic mode address of the circulating buffer. The page register in the DAG allows recycling within the 64K border of 256 memory pages, but these buffers cannot cross the page boundary. The auxiliary register copys all the main registers in the DAG; the switch between the main register and the auxiliary register provides a fast context switch.

Through the use of internal bus, efficient data transmission in the core:

program memory address (PMA) bus

program memory data data (PMD) bus

Data memory address (DMA) bus

data storage data (DMD) bus

DMA address Bus

DMA data bus

Two addressesLine (PMA and DMA) share an external address bus that allows memory to expand outside the film. Two data bus (PMD and DMD) shared an external data bus. Starting memory space and I/O memory space also shared external bus.

Program memory can store instructions and data at the same time, allowing ADSP-2191M to extract two operations in one cycle, one from program memory and one from data memory. DSP's dual memory bus also allows the ADSP-219X kernel to obtain a number of operations from the data memory within a cycle and get the next instruction from the program memory.

DSP外设体系结构

第1页的功能框图显示了DSP的片上外围设备，包括外部存储器接口、主机端口、串行端口、SPI兼容端口、UART端口、 JTAG test and simulation port, timer, logo and interrupt controller. The peripheral devices on these pieces can be connected to the film, as shown in Figure 1.

ADSP-2191M has a 16-bit host port with a DMA function and allows external hosts to access the memory on the film. This 24 -pin combined port consists of a 16 -pin multi -road data/address bus, which provides low -service data moving capabilities. It can be configured to 8 or 16 bits. This port provides a glue -free interface to various 8 -bit and 16 -bit micro -controllers. Two chips are selected to provide access to the host's entire memory mapping. The digital signal processor can start through this port.

ADSP-2191M also has an external memory interface, which is shared by the DSP core, DMA controller and peripheral devices supporting DMA. These peripheral devices include UART, Sport0, Sport1, SPORT2, SPI1, SPI1 and host ports. The external port consists of 16 -bit data bus, 22 -bit address bus and control signal. The data bus can be configured to provide 8 or 16 -bit interfaces to the external memory. Support for word packaging allows DSP to access 16 -bit or 24 -bit characters from external memory, regardless of the width of the external data bus. When the configuration is 8 -bit interface, 8 unused 8 lines provide 8 programmable two -way general -purpose programming logo lines, of which 6 can be mapped to the software status signal.

Memory DMA controller allows ADSP-2191M to move data and instructions between memory space: interior to external, inside to internal and external to external. This controller can also be transmitted with this controller.

ADSP-2191M can respond to up to 17 interruptions at any given time: three internal (stack, simulator kernel and shutdown), two external (simulator and reset), and twelve users Definition (periphery) interrupt. The programmer distributes the peripherals to one of the interruptions defined by 12 user definitions. The priority of each peripheral interrupt service is determined by these allocation.

There are three serial ports on ADSP-2191M, which provides a complete synchronization and full-duplex serial interface. This interface includes optional compression in the hardware, as well as various Opera's frame or frameless data transmission and receiving mode-action. Each serial port can send or receive internal or external programmable serial clocks and frame synchronization. Each serial port supports reinstatement when 128 channels are supported.

ADSP-2191M offers up to 16 general I/O pins, which can be programmed as input or output. Eight of them are dedicated generally programmable signs. The other eight are multifunctional tube feet. When DSP is connected to the 8 -bit external data bus, it acts as the universal I/O tube foot. When DSP is connected to 16 -bit external data bus, it acts as the upper 8 data tube foot. These programmable signs can achieve a sensitive interruption of edge or level, some of which can be used as the basis for execution conditions.

Three programmable interval timers generate cyclical interruption. Each timer can be set to work below one of the following three modes:

pulse waveform generation mode

pulse width count/capture mode

external event surveillance program mode

Each timer has a two -way tube foot and four registers that implement its operation mode: 7 -bit configuration register, 32 -bit count register, 32 -bit cycle cycle The register and 32 -bit pulse width register. One state register supports all three timers. Each timer configuration register is independent of other timers to enable or disable the corresponding timer.

Realm structure

ADSP-2191M digital signal processor provides 64K-word SRAM memory. The memory is divided into 4 16K blocks, on the memory page 0 in the DSP memory mapping. In addition to internal and external memory space, ADSP-2191M can solve two additional and independent chip existence spaces: I/O space and guidance space.

As shown in Figure 2, the two interior memory blocks of DSP fill all the contents of page 0. The entire DSP memory mapping consists of 256 pages (0-255 pages), with 64K characters per page.

The external memory space consists of four memory groups (group 0-3) and supports multiple SRAM memory equipment. Each library can be selected with memory (MS3-0) for selection, and has configured page boundary, waiting status and waiting status pattern.

The 1k word of the ROM on the film is filled at the top 255, and the remaining 254 pages can be addressing outside the film. The difference between I/O memory pages and external memory pages is that the length of the I/O pages is 1K, and the external I/O pages have their own choices (IOM). I/O memory space No. 0-7 is located on the chip and contains a configuration register for peripheral devices. Core peripherals and DMA peripherals can access the entire memory mapping of DSP.

Internal (on the film) memory

The unified program and data storage space of ADSP-2191M consist of 16m position, which can pass two 24-bit address bus through two 24-bit address bus lines. PMA and DMA bus access. Digital signal processor uses different mechanisms to generate 24 -bit addresses for each bus. DSP has three functions, supporting access to complete memory mapping.

DAG generates 24 -bit addresses to obtain data from the entire DSP memory address range. Because the width of the DAG index (address) register is 16 bits and the lower 16 -bit of the address is kept, each DAG has its own 8 -bit page register (DMPGX) to maintain the most effective 8 -bit address. Before DAG generates the address, the program must set the DAG DMPGX register to an appropriate memory page.

program serializer generates the address obtained by instruction. For relative addressing instructions, the program serializer is based on the relative jump, calling and circulating address on the 24 -bit program counter (PC). In direct addressing instructions (dual -word instructions), the instruction provides 24 -bit immediate address value. PC allows a linear address in the 24 -bit address range.

For indirect jump and call using the 16 -bit DAG address register as part of the branch address, the program sequencer depends on the 8 -bit indirect pages (IJPG) register to provide the most effective 8 Address position. Before cross -page jump or call, the program must set the IJPG register of the program serial device to an appropriate memory page.

ADSP-2191M has 1k-character film on the ROM for preserving the guidance program. If the peripheral guidance is selected, the DSP starts to guide the ROM to execute the instruction from the film, and start the guidance process from the selected peripheral. For more information, see the guidance mode " on page 11.

outer (outer) memory

Each ADSP-2191M film exterior memory space has a separate control register