Description

WM9713L is a highly integrated input/output device designed and communicated for mobile computing and communication.

The chip design is used for dual -encoded decoder operation, supports high fidgeted three -dimensional sound -editing decoder function interface by AC link, and supports the function of the voice editing decoder through an PCM type synchronization serial port (SSP) (SSP) Essence The third auxiliary device provides DAC, which can be used to support the supervision sound or ringtone of different samples charging the editor -in -chief decoder.

The device can be directly connected to the 4 or 5 line touch screen, mono or stereo microphone, stereo headphones and stereo speakers to reduce the system. The cover -free connection of the headset can use speakers and headphones to save costs and board areas. In addition, multiple simulation input and output pipes can be seamlessly integrated with the simulation tube.

All device functions are single AC link interfaces that meet AC #39; 97 standards.

24.576MHz main clock can directly input or generate the clock by the car locking ring internally from the 13MHz (or other frequency). PLL supports a wide range of input clocks from 2.048MHz to 78.6MHz.

WM9713L works volt under the power supply voltage of 1.8 to 3.6. Each part of the chip can be controlled by software, saving power. The device is packaged in a small lead 7X7mm QFN, which is very suitable for handheld portable systems.

Features

AC #39; 97 version 2.2 Compatible stereo-editing decoder

-dac signal-to-noise ratio 94db, ThD-85DB

-Steoid control, bass enhancement and 3D enhancement

45MW headset drive

400 MW single or stereo speakers driver on the film

Stereo, monocular or differential microphone input

-Frostomial high control (ALC)

Device description

Introduction

WM9713L is a major PIN compatibility upgrade of WM9712, adding a PCM voice codec decoder. This codec is connected through a PCM -type audio interface, which uses the GPIO tube foot to connect.

It aims to meet the mixed signal requirements of portable and wireless smartphone systems. It includes recording and playback, touch screen digitalization, battery monitoring, auxiliary ADC and GPIO functions, all through a 5 -line AC interface control. In addition, PCM voice supports the function of the codec function

by providing an additional voice DAC and a PCM audio sequence.

Including a PLL to allow unrelated reference clocks to generate the communication link system clock. Usually 13MHz or 2.048MHz reference can be used for reference.

Software support

The basic audio function of WM9713L is a software driver compatible with standard AC #39; 97 equipment. However, in order to better support the touch panel and other additional functions, Wolfson Microelectronics provides custom device drivers for the selected CPU and operating system.

AC #39; 97 compatibility

WM9713L uses AC #39; 97 interface to communicate with microprocessor or controller. This audio and GPIO features are largely in line with AC #39; 97 version 2.2. The following differences

According to AC #39; 97 Standard:

Pin: The functions of some pins have changed to support specific device features. Mobile phones and PCBeep pins have been moved to different positions on the device package.

Packaging: The default packaging of WM9713L is 7 × 7mm lead QFN

package.

Audio mixing: WM9713L can process all the audio functions of smartphones,

includesAudio playback, recording, telephone, telephone recording, ringing sound, and using these functions at the same time. AC #39; 97 mixer structure does not fully support this. Therefore, WM9713L uses improved AC #39; 97 mixer has three independent mixer buildings.

Tone control, bass enhancement, and 3D enhancement: realize these functions in digital domains, so only affect all output signals specified by AC #39; 97 through audio DAC.

Other functions are additional functions of AC #39; 97:

BTL speakers driver used for single -channel or stereo speakers

for ear speakers (for ear speakers ( Telephone receiver) The BTL driver in the film

Auxiliary single -sound DAC for ringtone, system alarm, etc.

touch screen controller

Auxiliary ADC input

2 battery alarm simulation comparators

The characteristics of programming filter that are used for tone control and 3D enhancement

PCM interfaces of additional voice DAC and existing audio ADC

PLL enters from the reference clock from the unrelated reference clock to create an AC #39; 97 system clock

PCM compilation coder

The function of the PCM voice codec that is usually required for mobile phone devices is DAC on the WM9713L. The standard PCM type data interface connection is constructed by the 4 GPIO tube feet on WM9713L. The audio output data comes from one or two audio ADCs can also be output through this PCM interface, allowing a complete voice codec to implement the function. This codec uses standard AC #39; 97 main clock, with WM9713L PCM interface, always acting as the main clock.

Overview of the audio path

The clock produces

WM9713L to support the timing from two independent sources, you can via AC #39; 97; 97; 97 Interface selection:

Enter mcLka

outer clock input MCLKB

In order to run AC #39; 97 interface, the source clock is divided into appropriate frequency interfaces, voice DAC and voice DAC and voice DAC and voice DAC and voice DAC and voice DAC and voice DAC and Voice DAC and Voice DAC and The high -fidelity digital signal processor passes through a programmable segmentation block. The clock rate can be changed through the link of AC #39; 97 to support the replacement mode, such as the power mode when the voice data is transmitted only. The appearance of the PLL increases the typical choice of the flexibility input clock frequency of the selection is 2.048MHz, 4.096MHz or 13MHz.

The default mode when calling is assumed that the clock will appear on the MCLKA when PLL is powered offEssence

This makes the data timing through the link of AC #39; 97 to define the required clock allocation device mode and whether to activate PLL.

Note: The clock can be any available frequency.

When Muxing between MCLKA and MCLKB, two clocks must be switched in a state of activity in at least two clock cycles.

The clock strategy of the clock division

WM9713L. The clock is controlled by CLK_MUX, CLK_SRC and S [6: 0].

CLKAX2, CLKBX2 —— Clock frequency frequency device on the input end MCLKA and MCLKB.

CLK U MUX — Select between MCLKA and MCLKB.

CLK U SRC -Selection between the external or PLL derivative clock reference.

s [3: 0] - Set the voice DAC clock rate and PCM interface clock in the main mode (available segmentation ratio 1 to 16).

s [6: 4] -The set a high-fidelity point rate (available segmentation ratio 1 to 8). The register used to set these switches can be accessing from the register address 44h (see Table 1).

If the pattern changes need to be switched from the external clock to the clock generated by PLL, it is recommended to set the clock segmentation to the clock between clocks between clocks before switching. This option is via two sets of registers SPLL [6: 0] and at 6:30. If you choose PLL (clk_src 0) s [6: 0] spll [6: 0], if you select the external clock (clk_src 1) s [6: 0] sext [6: 0]. Sext [6: 0] is defined in the register address 44h. SPLL [6: 0] In the register 46h (see Table 3), it also contains several independent control functions related to PLL.

Writing the register 44h and 46h can choose PLL output.

Pen mode digital converter

Penadc's clock runs 768kHz nominal nominal, and is exported by BitClk. Except for several clock generators, set up by PENDIV. This allows the Penadc clock frequency to consider the power consumption and conversion rate.

PLL mode

PLL operation is controlled by register 46h (see Table 3), there are two operating modes:

integer n

score n

PLL has optimized the frequency of nominal input clocks (PLL_-in) in the range of 8.192MHz.MHz (low frequency 1).

PLL Can with the input frequency of up to 78.6MHz by using the clock division (DIV × 2/4) is accepted. Enable the input clock division through Divsel (0 level), and set the frequency division of divctl (0 div2, 1 div4)

Integer n mode [123 ] The nominal output frequency of PLL (PLL_-OUT) is 98.304MHz, and the nominal clock with 24.576MHz can be achieved except 4.

Our integer removal (n) is determined by: FPLL_-OUT/FPLL_-in, and is set by n [3: 0], and the range of the integer n operation is 5 to 12 (0101 div multiplication 5, 1100 div multiply 12). Pay attention to setting LF 1 to further divide the input frequency in the range of 2.048MHz – 4.096MHz.

The integer N mode is selected by setting SDM 0.

Score N mode

The score N mode provides a 1/222 division resolution, and is set by K [21: 0] (register 46h, please refer to some PLL register page address mapping). The required partition x and scores divide K [21: 0] and integer except n [3: 0] are:

k () x n 22 2 of them 0 lt; ) Lt; 1, K four houses and five entries are the closest integer.

For example, if the input clock in the locking loop is 13MHz, and the required lock -loop output clock is 98.304MHz, the expected removal X is 7.5618. So n [3: 0] is 7H, K [21: 0] is 23F48H98.304MHz clock.

Data and control interfaces

WM9713L has two interfaces, one is the data and control AC #39; 97 interface, and the other is the PCM interface with only data.

AC #39; 97 interface can be the only control interface through special pins (SDataOut, SData, Sync, BitClk, and Resetb, which can access all the data streams on the device, except that sound. The PCM interface can be obtained and PCMADC through the GPIO pin (PCMCLK, PCMFS, PCMDAC), and provides access to the voice DAC. It can also transmit data ADC from the stereo system. This may be very useful, for example, allows mixing and receiving paths by mixing and receiving paths on an ADC channel, and passing the interface through PCM.

AC97 interface

Interface protocol

WM9713LHA is used for data transmission and controlSingle AC #39; 97 interface. Communication link use 5

wire:

SDatain (pin 8) transmits data from WM9713L to the controller

sdataout (pin 5) from the controller from the controller from the controller Transmit to WM9713L

bitck (pin 6) is a clock, entered and provided to the controller by MCLKA or MCLKB.

SYNC is generated by the controller and passed to

Resetb to reset WM9713L to the default status communication link interface interface interface interface interface interface interface interface (In a typical case, BitCLK is generated by the AC97 codec) Sdata and sdataout signals each carry 13 multiple multi -road reuse data streams (slot 0 to 12). The complete sequence of slot 0 to 12 is called the AC link frame, which contains 256 bits. The frame rate is 48kHz. In this way, you can send and receive multiple data streams (such as audio, touch screens, AUXDAC, control) at the same time, and the sampling rate is as high as 48kHz.

Note:

When resetb is applied, SDATAOUT and SYNC must maintain a low level. These signals must be maintained throughout the entire duration of the reset pulse, especially in

reset B. If it is set to high during resetting, AC #39; 97 device may enter the test mode.

Operation

WM9713L can use a dedicated VXAC to implement the PCM voice codec function, one of which or existing two high -fidelity ADCs. In the PCM codec mode, the VXAC input and ADC output interface via a PCM -style port via GPIO pins.

This interface can support a ADC channel, or a stereo/dual ADC channel (if required) (if required) data is sent to each PCM frame as a back -to -back word).

In pure voice mode, the communication link is only used to control information, not audio data. Therefore, it will usually turn off (PR4 1) unless control data must be sent.

The PCM interface uses 4 GPIO interface pipes for clocks, frames and data input/output. If the PCM codec function is not enabled, the GPIO pin can be used for other functions, such as WM9713L type

interface protocol

WM9713L PCM audio interface is used to input data and output from the three -dimensional sound to the voice DAC ADC data. When enabled, the PCM audio interface uses four GPIO pins:

GPIO1/PCMCLK: bit clock

GPIO3//PCMFS: Frame synchronization

GPIO4/PCMDAC: voice DAC data input

GPIO5/PCMADC: When the stereo ADC data output is not enabled, GPIO can be used for other functions on WM9713L.

PCM interface mode

WM9713L PCM audio interface can be configured to one of the following four modes:

Disable mode: WM9713L disables all PCM interface pins. Any ignoring clock input without transmitting ADC/DAC data.

From machine mode: WM9713L accepts PCMCLK and PCMFS as the external source.

Main mode: WM9713L generates PCMCLK and PCMFS as the output.

Part of the main mode: WM9713L generates PCMCLK as the output and accepts PCMFS as an external input.

Support four different audio data formats:

Digital signal processor mode

] Left alignment

Right alignment

These four modes are MSB first. They are described below. Refer to the characteristic part of electrical timing information.

The PCM interface can be configured as a single track mode, of which only one ADC data channel output. In this mode, the interface should be configured to a digital signal processor mode. Short -frame or long frame synchronization is supported, and the first (Mode B) or the second (mode A) can be used to use MSBVXCLK.

Note that during the operation in stereo mode, the monocular DAC always uses the PCM interface monocular track mode (Mode B, FSP 1) In the digital signal processor mode, the left channel main distribution board is on the power distribution board in the digital signal processor mode in the digital signal processor mode. The edge of PCMCLK (which can be selected by FSP) can be used at the rising edge of PCMFS when the first (mode B) or the second (mode a) is rising. The right channel data follows the left channel. Depending on the length, PCMCLK frequency and sample rate, there may be unused PCMCLK cycle samples between the LSB of the right channel data and the LSB of the next channel data.

Single microphone operation

Single -end configuration can connect up to three microphones. Any of the three of the three can use MPasel [1: 0] to select MICS as the input of MPA (The register is 22h, bit 13:12). Only the microphone on the MIC2B can be selected as MPB. Note that MPABST always sets up MPA input microphone. If MIC2B is a selected input of MPA, it is recommended that MPB has been disabled.

Double microphone operation dual -difference distribution can connect up to two microphones. This is very suitable for the three -dimensional microphone or noise elimination application. MIC1 is connected between MIC2A and MICCM input and MIC2 between MIC2B and MICCM inputs. In addition, MIC1 selected by MUX through MPA can support another microphone. Please note that the microphone can be connected by a single end.

Microphone bias circuit

Microclavic pressure output provides low noise for bias to polar body type Reference voltage microphone and related external resistance bias networks. Refer to the application of the information part of the external component. Micro -biased pressure can be MBVOL in the register 22h. When mbvol 0, micbias 0.9*AVDD, when mbvol 1, Micbias 0.75*AVDD.

Audio mixer

Overview of the mixer

WM9713L has four independent low -power audio mixed, which can meet smartphones, palm computers, and palm -on computers. These mixers are used to drive audio output HPL, HPR, Mono, SPKL, SPKR, OUT3 and OUT4. There are also two inverters to provide complementary output drive signals.

Headphones mixer

There are two headphones mixers, left earphones mixed and right headset mixers (HPMIXL and HPMIXR). These mixer is a stereo output drive source. They are HPL and HPR used to drive stereo sounds. They can also be used to drive SPKL and SPKR output. When they are used with OUT3 and OUT4, they can be configured to support the output of stereo speakers (BTL) stereo speakers through two output inverters. The following signals can be mixed in the headset path:

Monoin (controlled by the register 08h, see Audio input ")

Line L/R (controlled by the register 0AH