Features

● 24-bit-no lack of code

● 19-bit effective resolution up to 20kHz data rate

● Low noise: 1.5ppm

] ● Poor input

● Inl: 15ppm (maximum value)

● External reference (0.5V to 5V)

● Power off mode

● Synchronous mode

● Low power: 8MW at 20KHz; 5MW

Application

● Heart diagnosis, direct thermocouple interface

● Blood analysis

● Infrared high thermometer

● Liquid phase/gas phase chromatography

● Precision process control

ADS1251

It is a DELTASIGMA modulus converter with a high accuracy and a wide range of dynamic range, 24 -bit resolution, single power supply+5V power supply. The Delta-Sigma architecture has a wide range of dynamic scope and 24-bit missileless code performance. Effective resolution 19 digits (1.5ppm uniformly root noise) are the conversion rate as high as 20kHz.

ADS1251 is designed for high -resolution measurement applications in cardiac diagnosis, intelligent transmitter, industrial process control, weight scale, chromatography and portable instruments. The converter includes a flexible 2 -line synchronous serial interface for low -cost isolation.

ADS1251 is a single channel converter, which is packaged with SO-8. It is compatible with faster ADS1252 (41.7kHz data rate).

Typical features

In TA +25 ° C, VDD +5V, CLK 8MHz and VREF 4.096, there are other regulations.

Operation theory ADS1251 is a high -precision, high dynamic range, 24 -bit 24 -bit , Δ-Sigma, A/D converter, can achieve very high-resolution number results at high data rates. The sampling rate of analog input signal is determined by the frequency of the system clock (CLK). The sampling analog input is modulated by the Delta-Sigma A/D modulation, and then the digital filter. Sinc5 Digital low-pass filter processing the output of the Delta-Sigma modulator and writing the result to enter the data output register. DOUT/DRDY pins are low, indicating that external micro -controllers/microprocessors can read new data. As shown in the frame diagram of the previous page, the main function block of ADS1251 is the fourth -order incrementSigma Makers, digital filters, control logic and serial interfaces. Each of these function blocks is described in the following chapters.

Simulation input

ADS1251 contains full differential analog input. In order to provide low system noise, 98DB co -mode inhibition and excellent power suppression, the design topology is based on a full -time switching capacitor architecture. When the reference input voltage is equal to+4.096V, the bipolar input voltage range is -4.096 to+4.096V. The bipolar range is related to -Vin, and has nothing to do with GND.

The differential input impedance of the input input changes with the changes of the clock frequency (CLK) of the ADS1251 system. This relationship is:

Please refer to the application instructions to understand ADS1251, ADS1253 and ADS1254 input circuits (SBAA086), you can download from the TI website.

For the analog input signal, the overall simulation performance of the device is affected by three items. First, input impedance affects accuracy. If the source resistance of the input signal is significant, or if there is a passive filtering before the ADS1251, the significant part of the signal can be lost through the external impedance. The size depends on the required system performance.

Secondly, the current of input or output analog input must be limited. In any case, the current input or output an analog input current should not exceed 10mA.

Third, in order to prevent the input signal from overlapping, the bandwidth of the simulation input signal must be limited; bandwidth is a function of the system clock frequency. When the system clock frequency is 8MHz, the data output rate is 20.8kHz, and the A -3DB frequency is 4.24kHz. -3DB frequency is proportional to the system clock frequency.

In order to ensure the optimal lineivity of ADS1251, and maximize the uniform harmonic noise error, it is recommended to use a full differential signal.

Double -pole input

Each differential input of ADS1251 must be kept between -0.3V and VDD. When the reference voltage is less than half of the VDD, one input can be bound to the reference voltage, and the other input can be from 0V to 2 vREF. By using a three -way transport circuit with a single amplifier and four external resistors, the ADS1251 can be configured to be configured to receive the bipolar input of reference grounding. With the resistance value shown in Figure 1, the traditional ± 2.5V, ± 5V, and ± 10V input range can be connected to ADS1251.

Δ-Siegma Maker

ADS1251 works at the clock frequency of 8MHz. The frequency of the modulation is fixed compared to the system clock frequency. The system clock frequency is divided into 6 to get the modulation frequency (FMOD). Therefore, when the system clock frequency is 8mhWhen Z, the frequency of the modulation is 1.333MHz. In addition, the sampling rate of the modulator is fixed compared to the frequency of the modulation. The sampling rate of the modulator is 64, and when the frequency of the regulator is 1.333MHz, the data rate is 20.8kHz. The slower system clock frequency will cause lower data output rates, as shown in Table 1.

Reference input

In the 8MHz system clock, the average current input is 32 Weire. This current will be proportional to the system clock. It is recommended that ADS1251 use buffer reference. The recommended reference circuit is shown in Figure 2.

The reference voltage higher than 4.096V will increase the scale range, and the absolute internal circuit noise of the converter remains unchanged. This will reduce the noise of the full -size PPM, thereby improving effective resolution (see typical features of square root noise and VREF voltage).

Digital filter

The digital filter of ADS1251, called the Sinc5 filter, is based on the latest output calculation number result from the incremental Siegma -made maker. At the most basic level, the digital filter can be considered as the result of a weighted form average modulation, and the average value is represented as a digital output. Digital output rates or data rates are zoomed directly with the clock frequency. This allows changing the data output rate by changing the system clock frequency within a very wide range (five quantitatives). However, it should be noted that the -3DB point of the filter is 0.2035 times the data output rate, so the data output rate should be left enough to prevent the related signal attenuation.

Since the conversion result is essentially an average value, the data output rate determines the position of the concave production generated in the digital filter (see Figure 3). Note that the first slot is located at the frequency of data output rate, and the subsequent slot port is located at an integer multiple of the data output rate; this not only allows suppression of the base frequency, but also allows the hormone frequency. In this way, the data output rate can be used to set the specific trap frequency of the digital filter response.

For example, if the frequency of the power cord is needed, the data output rate can be simply set to the power cord frequency. For 50 Hz suppression, the system clock frequency must be 19.200kHz, which sets the data output rate to 50 Hz (see Table i and Figure 4). For 60Hz suppression, the system CLK frequency must be 23.040kHz, which sets the data output rate to 60Hz (see Table i and Figure 5). If you are required to reject 50 Hz and 60 Hz at the same time, the system CLK must be 3.840 kg; this sets the data output rate to 10 Hz and rejects 50 Hz and 60 Hz (see Table 1 and Figure 6).

There is an additional benefit to use lower data output rates. It can better inhibit the scope of signal interest at the frequency. For example, in 50 HeAt the data output rate of Ziz, the valid signal of 75 Hertz can be returned to the band frequently at 25 Hertz. This is because at 75Hz, when the frequency of the blocking band is higher than the first trap frequency, the inhibitory may only be 66DB (see Figure 4). However, set the data output rate to 10Hz at 75Hz offers 135DB suppression (see Figure 6). Similar benefits are also obtained at the frequency of data output rate (see Figures 7, 8, 9, and 10). For example, for the data output rate of 50 Hz, the inhibition of 55 Hz may only be 105 decibels (see Figure 7). However, at the 10Hz data output rate, the inhibition of 55Hz was 122DB (see Figure 8). If the slower data output rate does not meet the system requirements, it can be designed to simulate the front end to provide the required attenuation to prevent confusion. In addition, the data output rate can be improved and additional digital filtering can be performed in the processor or controller.

Application description SBAA103 is an electronic table that calculates ADS1250-54 frequency response. It can be downloaded from the TI website. It provides a simple tool to calculate the ADS1250 frequency response of any CLK frequency.

The digital filter is described by the passing function below:

The digital filter requires five conversion to be completely stable. The modulator has a sampling rate of 64; therefore, it requires 5 64 or 320 regulator results (or clocks) to complete it. Since the modulator clock comes from the system CLK (the modulator clock clk ÷ 6), the number of system clocks required for digital filter completely stable is 5 64 6 or 1920 CLK. This means that any major steps of simulation input require five complete conversion to solve. However, if the analog input occurs with a step -by -step change and DOUT/DRDY pulse, six conversions are required to ensure complete stability.

Control logic

Control logic for ADS1251 communication and control.

The order of power -on

Before powering on, all the number and simulation input pin must be low. When power is powered, these signal input may bias the voltage other than 0V; however, they should not exceed+VDD.

Once ADS1251 is powered on, the DOUT/DRDY line will be low in the first conversion. For the first conversion, the data of the input signal is effective.

Dutex/Dudi

DOUT/DRDY output signal alternate between the two operating modes. The first operation mode is the data ready mode (DRDY), which indicates that the new data has been loaded to the data output register and prepared to read. The second operation mode is the data output (DOT) mode, which is used to transform the data out of the data output register (DOR) serially. ScopeThe partition is shown in Figure 11-DRDY and DOUT functions.

The basic timing of double/driedy is shown in Figure 12. During the time definition of T2, T3, and T4, the functions in DRDY mode DOUT/DRDY tube feet. DOUT/DRDY tube foot status

Before the new data is transmitted to DOR, it is high. The results of the A/D conversion are written from the highest effective position (MSB) to the minimum valid position (LSB) within the time of T1 definition (see Figures 11 and 12). Then, the DOUT/DRDY line is low in the timeline defined by the T2, and then drives the line high within the T3 definition to indicate that the new data can be read. At this point, the function of DOUT/DRDY tube feet becomes DOUT mode. The data shifted on the tube foot after T7. If the MSB is high (because the result is negative) T3 is over, the Dout/DRDY signal will remain high. The device that communicates with ADS1251 can provide SCLK to ADS1251 after T6. The normal mode of reading data from ADS1251 is that the device read the ADS1251 locks the data on the rising edge of the SCLK (because the data is removed from the ADS1251 on the decrease of the SCLK). To retrieve effective data, the entire DOR must be read before the DOUT/DRDY tube foot returns the DRDY mode.

If SCLK is not provided to ADS1251 during the DOUT mode, the DOR MSB will appear on the DOUT/DRDY line until the time of the definition of T4 begins. If in DOUT mode (that is, the SCLK provides less than 24) is not fully read on ADS1251, the last reading state in DOUT/DRDY is until the time of the definition of T4. If more than 24 SCLKs are provided in DOUT mode, the DOUT/DRDY line will remain low until T4 defines the time.

The internal data pointer that removes the data on DOUT/DRDY decreased by the decrease of the time of the definition of T1 and T4 along the upper upper than the upwards. Set. This can ensure that the first data from the DRDY mode is always the greatest effective position of new data. Synchronous multiple converters

The normal state of SCLK is low; however, by keeping SCLK high, multiple ADS1251 can be synchronized. This is achieved by keeping the SCLK high, but less than 20, and the continuous DOUT/DRDY cycle (see Figure 13). The SCLK has been detected in the ADS1251 circuit that SCLK has been maintained for four consecutive DOUT/DRDY cycles at a high level of DOUT/DRDY.Keep in a reset state. The modulator will be released from the reset and the synchronization occurs on the decrease of the SCLK. For multiple converters, the decline of SCLK must occur at the same time on all devices. It should be noted that during synchronization, the DOUT/DRDY pulse of multiple ADS1251 in the system may have a time difference within a DRDY cycle. Therefore, in order to ensure synchronization, SCLK must maintain a high level of at least 5 DRDY cycles. The first DOUT/DRDY pulse after SCLK drops occurs at T14. The first DOUT/DRDY pulse represents valid data.

Power off mode

The normal state of SCLK is low; however, keep SCLK high, ADS1251 will enter the power -off mode. This is a continuous DOUT/DRDY cycle that maintains at least 20 SCLK high (see Figure 14). In the ADS1251 circuit, SCLK has maintained four continuous DOUT/DRDY cycles of high levels. DOUT/DRDY tube foot pulse is lower with a CLK cycle, and then keeps high, and the modulator is kept in a reset state. If SCLK keeps at a high level of 16 DOUT/DRDY cycles, ADS1251 enters the power loss mode. This part will be released from the power -off mode of the SCLK decrease. It should be noted that after the four DOUT/DRDY cycles, the DOUT/DRDY tube feet are kept at a high level, but will not enter the power -off mode in the other 16 DOUT/DRDY cycles. The first DOUT/DRDY pulse after SCLK drops occurs in T16, which means valid data. Subsequent DOUT/DRDY pulse will occur normally.

Serial interface

ADS1251 includes a simple serial interface, which can be connected to a microcontroller and digital signal processor in various ways. Communication with ADS1251 can start when DOUT/DRDY pulse is first detected after power -on.

It should be noted that the data from ADS1251 is a 24 -bit result. First, send MSB in a displacement binary binary replacement format, as shown in Table 3.

Data must check in before the ADS1251 enters the DRDY mode to ensure that valid data is received, as described in the DOUT/DRDY part of this data table.

isolation

The serial interface of ADS1251 provides a simple isolation method. The CLK signal can be ADS1251, and only two signals (SCLK and DOUT/DRDY) are used for isolation data collection.

layout

Power supply

The power supply must be well adjusted and low noise. For requesting ADS1251 veryHigh -resolution design, power suppression will be a problem. Avoid running digital lines under the device because they may couple noise onto the mold. High -frequency noise can be coupled to the analog part of the device, and the mixing back to the numeric strip of the digital filter affects the conversion result. This clock noise can cause offset errors.

Ground

The simulation and number part of the system design should be carefully and clean. Each part has its own horizon, and there is no overlap between them. GND should be connected to analog ground plane and all other simulation ground. Do not connect the simulation and digital grounding planes to the circuit board, but use the medium signal trajectory to connect two ground planes. For multiple converters, two ground planes are connected to the center of all converters at one position. In some cases, you may need to perform experiments to find the best point to connect two planes together. The printing circuit board can be designed to provide different analog/digital grounding connections through short connections. The initial prototype can be used to determine which connection is most effective.

Described

ADS1251 and all components in the design should adopt good decoupling practice. All counter -coupled capacitors, especially 0.1 μF ceramic capacitors, should be placed as close as possible as possible. 1 μF to 10 μF capacitors should be connected in parallel with 0.1 μF ceramic capacitors to separate VDD from GND.

System Note

Power and ground recommendations will be changed according to the requirements and specific design of the entire system. It is much more difficult to achieve 24 -bit noise performance than the realization of 12 -bit noise performance. Generally speaking, a system can be divided into four different stages:

Simulation processing

ADS1251's simulation part

#8226 ; The digital part of ADS1251

Digital processing

For the simplest system composed of the minimum analog signal (basic filtering and gain), microcontroller and a clock source, you can, you can A high resolution is achieved by power supply from public power supply. In addition, all components can share a public ground plane. Therefore, there is no difference between the simulation power and the ground, the digital power supply and the ground. The layout should still include a power plane, a ground plane, and a careful decoupling. In more extreme cases, the design can include:

multiple ADS1251

wide simulation signal processing

Or multiple microcontroller, digital signal processor or microprocessor

Many different clock sources

]

This design is difficult to reach a high scoreResolution. The method is to divide the system into as many parts as possible. For example, each ADS1251 can have its own analog processing front end.

The definition of the term

has tried to use consistent terms in this data table. In this regard, the definition of each term is as follows:

Simulation input differential voltage-For the simulated signal of completely differentials, the voltage range can be compared with the voltage range of the instrument amplifier. For example, if the two analog inputs of ADS1251 are 2.048V, the differential voltage is 0V. If one analog input is 0V and the other analog input is 4.096V, the difference voltage is 4.096V. In this case, no matter which input is 0V and which input is 4.096V. However, digital output results are completely different. The simulation input differential voltage is given by the following square program:

When the analog input differential voltage is positive, generate a positive number output, and when the simulation input differential motor voltage is negative As long as the difference is negative, digital output will be generated. For example, when the converter is configured with a 4.096V reference voltage and the simulation input difference is 4.096V, it generates a full -scale output. Negative bidding output-When the differential voltage is -4.096V, the marking output is generated. In each case, the actual input voltage must be kept within -0.3V to+VDD.

Actual analog input voltage-Any simulation input terminal is a voltage of GND.

Full marking range (FSR) -If, like most A/D converters, the full marking range of ADS1251 is defined as the input of the number of numerals to generate a full bidder. Input of output. For example, when the converter is configured with 4.096V reference voltage, the range of the difference is: [4.096V (full standard) - ( - 4.096V (negative standard)] 8.192V

] The minimum valid position (LSB) weight-this is to observe the change of the lowest valid output data, the theoretical voltage of the differential voltage of the input terminal must be changed. Calculated as follows:

Among them, n is the number of digits in the digital output.

The conversion cycle here refers to the time period between DOUT/DRDY pulse.

effective resolution (effective resolution ( ER) -In specific configuration, ADS1251 can be represented by two different units: bit RMS (reference output) and μVRMS (reference input). Calculate directly from the output data of the converter. Each one is based on the result of a given quantity. Statistical calculation. Noise appears randomly; the RMS value indicates a statistical quantity, that is, a standard deviation. The ER can be calculated as follows:

Each calculation in each calculation 2 VREF represents the full marking range of ADS1251.This means that both units are resolution absolute expression of different configurations that can be directly compared, regardless of what the unit is.

The frequency of FMOD-modulator and the sampling frequency of input.

fdata-data output rate.

Noise reduction-For random noise, the use of the average method can increase ER.As a result, the noise reduces the factors √N, where n is the average, as shown in Table 4.This can be used to achieve real 24 -bit performance at a lower data rate.To reach a 24 -bit resolution, it must accumulate more than 24 bits.36 -bit cumulators are needed to achieve 24 -bit ER.The following uses VREF 4.096V, ADS1251 outputs data at 20KHz, 4096 points require an average of 204.8ms. If the input signal is drifted in 200ms, the average benefit will be reduced.]