Features

charge balance ADC; 16 -bit without leakage code; 0.0015%non -linear; programming gain front end; income 1, 2, 32, and 128; differential input capabilities; three -line serial interface; soybeans; soybeans; soybeans; soybeans; soybeans; soybeans; soybeans; soybeans; soybeans; soybeans; soybeans; soybeans; soy beans Separate protein-QSPI #8482;-, Microsoft #8482;-, compatible with DSP; buffer simulation input ability; 3 v ( AD7715 -3) or 5 V (AD7715-5) operation; Low power supply current: 3 V power supply maximum 450 micro -safety; low -pass filter with programmable output update; 16 lead SOIC/PDIP/TSSOP.

General description

AD7715 is a complete simulation front end for low -frequency measurement applications. This part can directly receive a low -level input signal from the sensor and output serial numbers. It adopts δ-Δ conversion technology to achieve up to 16-bit leakage code performance. The input signal is applied to the front -end of the proprietary multi -programming gain based on an analog modulation. The modulator output is treated by the digital filter on the film. The first sinking wave of this digital filter can control the register programming on the chip, allowing the filter to cut off and output update rate.

AD7715 has differential analog input and differential reference input. It is powered by a single power supply (3 volts or 5 volts). It can process the single -pole input signal range of 0 MV to 20 MV, 0 MV to 80 MV, 0 V to 1.25 V, and 0 V to 2.5 V. V's bipolar input signal range. These bipolar range refer to the negative input of the differential analog input. Therefore, AD7715 performs all signal adjustment and conversion on the single channel system.

AD7715 is very suitable for intelligent, microcontrollers or system -based systems. It has a serial interface that can be configured as a three -line operation. The selection of gain settings, signal polarity, and update rate can be configured using the input serial port in the software. The components contain self -calibration and system calibration options to eliminate the gain and offset error in the component itself or in the system.

The CMOS structure guarantees extremely low power consumption, and the power consumption mode reduces the standby power consumption to 50 watts. This component has a 16 -drawing, 0.3 -inch wide plastic dual -column direct -column direct -inserted package (PDIP) and 16 -inch, 0.3 -inch wide shape (SOIC U W) packaging, and 16 -drawing TSSOP packaging.

Product Highlights

1, AD7715 The total power supply current under the 3V power supply and the 1MHz main clock consumes less than 450 Weian, so it is very suitable for use in low power consumption systems. The machine current is less than 10 Wei'an.

2. The programmable gain input allows AD7715 to directly accept input signals from the strain or sensor, thereby eliminating a large number of signal regulation.

3. AD7715 is an ideal choice for microcontroller or DSP processor application. It has a three -line serial interface, which can reduce the number of interconnected lines and reduce the number of optocouplers required in the isolation system. This part contains a chip register, allowing software to control the output update rate, input gain, signal polarity and calibration mode.

4. This component has excellent static performance specifications, 16 bits without leakage codes, accuracy of ± 0.0015%, and low -balanced square root noise ( lt; 550 nv). Through the calibration options on the film, the effects of endpoint error and temperature drift are eliminated, and zero -scale and full scale errors are eliminated.

Term

Points non -linearity

This is the biggest deviation between any code and the straight line of the endpoint of the function. The endpoint of the transmission function is zero -standard (do not confuse with the double pole zero point), the first code conversion (000 ... 000 to 000… 001), 0.5 LSB points and full standards, the last code conversion (111 ... 110 to to 111 ... 111) 0.5 LSB points on. The error is represented by a percentage of a full range.

Positive standard error

Positive standard error is the last code conversion (111.110 to 111.111) from the ideal AIN (+) voltage ( -)+++) V/gain-3/2 LSB). It is suitable for single and bipolar analog input range.

Single -pole offset error

The single -pole offset error is the first code conversion and ideal AIN+voltage ( -)+0.5 LSB) when working in a single pole mode. deviation.

Dual pole zero error

This is a medium -scale transition (0111.111 to 1000. 000) when working in the bipolar mode, from the ideal AIN+voltage ( -) — 0.5 — 0.5 LSB).

gain error

This is the measurement of the ADC quantity error. It includes a full marking error, but does not include zero -standard error. For single -pole input range, definitions are defined as (full marking error single pole offset error), and for the bipolar input range, the definition of the full marking error is the bipolar zero error).

Bilateral negative full marking error

This is the first code conversion and ideal AIN+voltage ( -) -vREF/gain +0.0.5 LSB when working in the bipolar mode The deviation.

Positive standard excess range

The excess range of the full margin means that it can be used to deal with the error caused by the error caused by the overload or digital filter overflow of the simulated modulator or digital filter overflow. Ain+input terminal (greater than AIN-)+V/gain (for example, input on the noise peak or overvoltage caused by the system gain error in the system calibration program)Voltage overhead.

The negatively benchmarking excess range

This is not allowed to make the simulated modulator overload or digital filter overflow, and process AIN+lower than AIN ( -) -V/gain. The available expenses of voltage. Please note that even in a single pole mode, the simulation input also accepts negative voltage peak values, provided that AIN+is greater than Ain (-) and greater than Agnd-30 MV.

The range of offset calibration

In the system calibration mode, AD7715 calibrate its offset relative to the simulation input. The discharge calibration scope specification defines the voltage range that AD7715 can accept and still accurately calibrate offset.

Full standard calibration range

This is an acceptable voltage range that AD7715 can accept in the system calibration mode, and can still correctly calibrate the standard.

Input range

In the system calibration scheme, the two voltage of the AD7715 analog input in order define the analog input range. The input range specification defines the minimum and maximum input voltage from zero to full standard. AD7715 can be accepted and still accurate calibration gain.

The register on the film

AD7715 contains four films on the register, which can be accessed through the serial port on the component. The first one is a communication register. It determines whether the next operation is read or write operations, and also decides which register of the operation or writing operation. All communication with the component must start with the writing operation of the communication register. After power -on or reset, the device expects to write a communication register. The data written to the register determines whether the next operation of the component is written or read, and determines which register of the read operation. Therefore, the writing access of any other registers on the parts starts to write operations to the communication register, and then the writing operation of the selected register. The read operation of any register (including the communication register itself and the output data register) starts with the writing operation of the communication register, and then starts with the reading operation of the selected register. The communication register also controls the standby mode and work gain of the component. DRDY status can also be obtained by reading from a communication register. The second register is to determine the calibration mode, filter selection, and setting registers for bipolar/single operation. The third register is the data register of the access component output data. The final register is a test register accessed when testing the device. It is recommended that users do not try to access or change the contents of the test register because this may cause the device to be unspecified. The following sections will discuss these registers more in detail.

Communication register (RS1, RS0 0, 0)

The communication register is an eight -bit register that can read data or write data from it. All communication with the component must start with the writing operation of the communication register. Data from the communication registerDetermine whether the next operation is read or write, and which register the operation occurs. Once the subsequent reading or writing operation of the selected register is completed, the interface will return to the position of the writing operation that is expected to perform the communication register. This is the default state of the interface. After power -on or reset, the AD7715 is in this default state, waiting for the writing operation of the communication register. When the interface sequence is lost, if the device is written enough (at least 32 serial clock cycles) when DIN is high, the AD7715 returns to the default state.

Set the register (RS1, RS0 0, 1); power -on/reset status: 28 HEX

Set the register as an 8 -bit register, which can be read or write data from it. The register control device runs in the case of calibration mode, output rate, monocular/bipolar operation, etc.

Test register (RS1, RS0 1, 0)

This section contains a test register for it for for it for it for for Test Equipment. It is recommended that users do not change the status of any bit in this register from the default (power -on or reset) state of all 0 to 0, because parts will be placed in one of its test mode and will not work properly. If parts enter one of the test mode, execution reset will exit the component from the mode. Another scheme that uses the component to break away from its test mode is to write 32 consecutive 1 consecutive 1, and then load all 0 to the test register to reset the interface.

Data register (RS1, RS0 1, 1)

The data register on the component is a reader that only reads 16 -bit registers, which contains the latest conversion results of AD7715. If the communication register data sets a part for the writing operation of the register, the writing operation must be actually performed to return the component to the position of the writing operation of the communication register (the default status of the interface). However, the 16 -bit data of the component will be ignored by AD7715.

Output noise

AD7715-5

Table 15 shows that AD7715-5 selects the output of the output of the waves, and the FS1 and FS0 selected by the FS1 and FS0 of the registers are selected -3DB frequency of parts. The given numbers are used in the bipolar input range of VREF to 2.5 V. These numbers are typical, produced under the input voltage of 0 V's differential analog input voltage, and partly used for no buffer mode (the buf bit of the register 0). At the same time, Table 16 shows the -3DB frequency of the output peak to the peak noise and components of the optional waves. It should be noted that these numbers indicate that there is no coding flickering resolution. They are not calculated based on the average square root noise, but based on peak noise. The number given is suitable for the bipolar input range and setting registers with a bipolar input range of 2.5 VBUF bit 0. These numbers are typical, generated under the analog input voltage of 0 V, and entered the closest LSB in the four houses and five.

At the same time, Table 17 and 18 show the average root noise and peak-peak resolution of AD7715-5 under the same conditions as the above conditions. The BUF bit of the register 1).

AD7715-3

Table 19 shows that AD7715-3 can choose the output of the output of the waved wave, and The -3 db frequency selected by FS1 and FS0. The number given is used in the bipolar input range of 1.25 V. These numbers are typical, produced in the 0 V simulation input voltage, and partly used for no buffer mode (the buf bit of the register 0). At the same time, Table 20 shows the output peak noise of the-3DB frequency of optional waves and parts. It should be noted that these numbers indicate that there is no coding flickering resolution. They are not calculated based on the average square root noise, but based on peak noise. The given numbers are used for the bipolar input range of 1.25 V and the buf bits of setting registers 0. These numbers are typical, generated under the analog input voltage of 0 V, and entered the closest LSB in the four houses and five.

At the same time, Table 21 and Table 22 show the average root noise and peak-peak resolution of AD7715-3 under the same conditions as the above conditions. The BUF bit of the register 1).

The calibration order

AD7715 contains many school quasi -options, as shown in Table 13. Table 23 summarizes the standards of calibration, the operation and operation duration involved. There are two ways to determine the end of the calibration. The first is to monitor DRDY in order. DRDY not only indicates when the sequence is completed, but also a effective new sample in the data register of the component. This effective new sample is the result of normal conversion in the order of calibration. The second method of determining when the calibration is completed is to monitor the MD1 and MD0 bits of setting registers.

These positions returned to 0,0 after the calibration command, indicating that the school sequence has been completed. This method does not indicate whether there are effective new results in the data register. However, it gives earlier instructions than DRDY. The duration to the mode bit (MD1 and MD0) returns 0, and 0 indicates the duration of performing calibration. The order when DRDY becomes lower also includes normal conversion and pipe delay TP to correctly zoom in the result of the first conversion. TP will never exceed 2000 × TCLK in.

circuit description

AD7715 is a digital filter ∑-ΔADC, which is used to measure low -frequency signals in a wide dynamic range, such as industrial control or process control signals in applications. It contains a calibration micro-controller, clock oscillator, digital filter and two-way serial communication unit-Nications port-Nications. This component only consumes a power current of 450 μA, which is very suitable for battery power supply or circuit power supply instruments. There are two versions of this part. AD7715-5 specifies to run from the nominal 5 V simulation power supply (AV), and AD7715-3 specifies to run from the nominal 3.3 V simulation power supply. Both versions can be operated under the voltage of the digital power supply (DV) of 3.3 V or 5 V.

This section contains a programmable gain full differential analog input channel. The optional gain on the input is 1, 2, 32, and 128. When the reference input voltage is 1.25 V, the allowable components to accept a single pole signal between 0 MV and 20 MV and 0 V to 2.5 V to the allowable component or ± 20 mV to 2.5 V to 2.5 V to the 2.5 V to 2.5 V to to 2.5 V. The bipolar signal within the range of ± 2.5 V, the input range of the single pole mode is 0 mv to 10 mv to 0 V to +1.25 V, and the bipolar mode is ± 10 mv to ± 1.25 V. Note that the bipolar range is related to Ain ( -), and it has nothing to do with Ain ( -).

The input signal of analog input is continuously sampled continuously by the frequency of the main clock, MCLK in and selected gain. The charge balancing ADC (δ-Δ modulator) converts the sampling signal into a digital pulse string containing digital information. The programmable gain function of the analog input is also included in the ∑-Δ modulator, and the input sampling frequency is modified to obtain a higher gain. Sinc Digital low-pass filter processing the output of the ∑-Δ modulator, and update the output register at a rate determined by the first trap frequency of the filter. The output data can be read randomly or regularly from the serial port at any rate until the output register is updated. The first trap (so its -3DB frequency) of the digital filter can be programmed by setting the register position FS0 and FS1. In the case of the main clock frequency of 2.4576MHz, the programmable range of the first wave frequency is from 50Hz to 500Hz, which gives a programmable range from 13.1Hz to 131Hz. In the case of the main clock frequency of 1 MHz, the programmable range of the first wave frequency is 20 Hz to 200 Hz, which provides a programmable range of 5.24 Hz to 52.4 Hz-3 DB frequency.

The basic connection figure of AD7715-5 is shown in Figure 4. This shows that the AV and DV pins of AD7715 are driven by analog 5 V power. Some applications have independent power supply for AV and DV drivers. The reference voltage with an AD780 accuracy is 2.5V to provide a reference source for parts. In terms of numbers, the component is configured with CS operations connected to DGND. Quartz crystal or potteryPorcelain resonator provides the main clock source for the part. In most cases, a capacitor must be connected on the crystal or resonant to ensure that it does not oscillate the pan -sounded place of its basic operating frequency. The values of the capacitor change according to the specifications of the manufacturer.

Simulation input

Simulation input range

AD7715 contains a differential analog input to Ain (+) and Ain ( -). This input provides a programmable gain and differential input channel, which can handle single or bipolar input signals. It should be noted that the double -pole input signal refers to the corresponding Ain ( -) input of the input pair.

In the no buffer mode, the input co-mode range is from AGND to AV, provided that the absolute value of the input voltage is between Agnd-30MV and AV+30MV. This means that in the no buffer mode, this part can handle the range of single and bipolar input range of all gains. In the buffer mode, the simulation input can handle larger source impedance, but the absolute input voltage range is limited between AGND+50MV and AV-1.5V, which also limits the scope of the co-mode. This means that in the buffer mode, there are some restrictions on the allowable gain of the bipolar input range. Be careful when setting up a common modulus voltage and input voltage range to avoid exceeding the above -mentioned restrictions, otherwise linear performance will decrease.

In the no buffer mode, the simulation input directly observes the input sampling capacitor CSAMP. Under this no -buffer mode, the leakage current is the maximum of 1 millimeter. As a result, analog input saw a dynamic load switching input sampling rate (see Figure 5). This sampling rate depends on the frequency of the main clock and the selected gain. CSAMP is charged to Ain+at each input sampling cycle and discharged to Ain ( -). The validable transmission resistance of the switch is usually 7kΩ.

CSAMP must be charged in each input sampling cycle through RSW and any external source impedance. Therefore, in the no buffer mode, the source impedance means that the charging time of CSAMP is longer, which may lead to part of the gain error. Table 24 shows the external resistance/capacitance value allowed in the no buffer mode, so that the gain error of 16 -bit level is not introduced on the component. Note that these capacitors are the total capacitance on the input, and the external capacitors plus 10 PF capacitors from the device pin and the lead framework.

In the buffer mode, simulate the high impedance input level of the buffer large buffer large input film. CSAMP is charged through this buffer, so that the source impedance does not affect the charging of CSAMP. The offset leakage current of this buffer is 1 millimeter. In this buffer mode, large source impedances will cause a small DC offset voltage in the source impedance, but will not produce gain errors.

Input sampling rate

The modulator of AD7715The sample frequency remains in FCLK IN/128 (19.2 kHz@FCLK IN 2.4576 MHz) without considering the selected gain. However, the gain is greater than the zoom of the combination of multiple input samples of each modulator cycle and the ratio of the ratio of reference capacitors to the input capacitance. As a result of multiple sampling, the input sampling rate of the device changes with the selected gain (see Table 25). In the buffer mode, the input is buffer before the input sampling capacitor. In the no buffer mode, the simulation input directly observes the sampling capacitance, and the effective input impedance is 1/CSAMP × FS. The CSAMP is the input sampling capacitor, and the FS is the input sampling rate.

Dual/single input

The analog input on AD7715 can accept the single or bipolar input voltage range. The range of bipolar input does not mean that the component can process the negative voltage on its analog input, because the negative voltage of the analog input cannot exceed -30 MV to ensure the correct operation of the component. The input channel is completely different. Therefore, refer to the voltage of AIN+input upper poles and bipolar signals is the corresponding voltage on the input of Ain ( -). For example, if Ain ( -) is 2.5 V and the AD7715 configuration to a single -pole operation with a gain of 2 and V is 2.5 V, the input voltage range on the input of Ain ( -) is 2.5 V to 3.75 V. If AIN ( -) is configured to be 2.5 V and AD7715, the gain is 2.5 V and VREF is 2.5 V, and the analog input range on the input is 1.25 V to 3.75 V (that is, 2.5 V ± 1.25 V). If Ain ( -) is located in agng, the part cannot be configured to be a bilateral range exceeding ± 30 mv.

B selects polar or single polarity options by programming the B/U bit of the register. This is a single or bipolar operating programming channel. Single or bipolar operating programming channels will not change any input signal adjustment; it just changes the point on the data output encoding and calibrated transmission functions.

Reference input

AD7715 Reference input, REF input positive and REF input negative poles provide differential reference input capabilities. The coexistence range of these differential inputs is from Agnd to AVDD. For AD7715-5 and AD7715-3, the nominal reference voltage VREF (Ref in (+) -s (-)) of the specified operation is 2.5 V and 1.25 V, respectively. This part works when the VREF voltage drops to 1V, but because the output noise (as far as LSB is concerned), the performance will be reduced. To make AD7715 work normally, the REF-I (-) must always be greater than the Ref-I (-).

Two reference inputs provide a high impedance, dynamic load is similar to simulation input in the buffer mode. The maximum DC input leakage currentFor ± 1 mAh, the source resistance may cause the device gain error. In this case, the sampling switch resistance is usually 5 kΩ, and reference capacitors (C) change with gain. The sampling rate on the input is FCLK IN/64, which does not change with gain. For gain 1 and 2, CREF is 8 PF; for gain 32, CREF is 4.25 PF; for gain 128, CREF is 3.3125 PF.

The output noise properties summoned in Table 15 to 22 are suitable for the simulation input of 0 V, which effectively eliminates the impact of noise on the benchmark. To obtain the same noise performance as shown in the noise meter throughout the input range, AD7715 requires a low noise reference source. If the reference noise in the bandwidth is too large, the performance of AD7715 will be reduced. In the application of the incentive voltage of the bridge sensor on the analog input, the reference voltage of the component is also exported, and because the application is measured, the impact of the noise in the incentive voltage will be eliminated. AD7715-5 Reference voltage sources include AD780, REF43, and Ref192, while AD7715-3's recommendation reference voltage sources include AD589 and AD1580. It is generally recommended to decide the output of these reference signals to further reduce the level of noise.

Digital filter

AD7715 contains a low-pass digital filter in the tablet to process the output of the component ∑-Δ modulator. Therefore, this part not only provides a modular conversion function, but also provides a certain degree of filtering. When the filtering function is provided in the digital domain instead of the simulation domain, users should know that there are many system differences.

First, because the digital filter occurs after the A-D conversion process, it can remove the noise injected during the conversion process. Simulation filter cannot do this. In addition, digital filter is easier to program more than analog filter. According to the design of the digital filter, this gives the user's ability to program the cut -off frequency and output update rate.

On the other hand, the simulation filter can remove the noise superimposed on the analog signal before the analog signal reaches the modulus. Digital filtering cannot be done. Even if the average of the signal is within the restriction range, the peak of noise peak multiplied to the signal near the benchmark may make the simulation modulation and digital filter saturated. To alleviate this problem, the AD7715 has an extra volume in the ∑-Δ modulator and digital filter, allowing 5%over-procedure offset at the analog input range. If the noise signal is greater than this value, the simulation input filtering should be considered, or the input channel voltage should be considered, so that the full marker is half of the simulation input channel full marker. This provides a transcendent ability greater than 100%, but the cost is to reduce the dynamic range by 1 (50%).

In addition, the digital filter does not provide any suppression at the integer multiple of the sample frequency of the digital filter. However, the input sampling of this part provides attenuation with the multiple of the sampling frequency of the digital filter, makingThe attenuation band actually occurs near the multiple of the sampling frequency F (as defined in Table 25). Therefore, the unsteading zone appears at N × FS (where n 1, 2, 3 ...). At these frequencies, there are ± F3 wide frequency bands that are transmitted to any side of the output (F3 is the cut -off frequency of digital filter).

Filter characteristics

The digital filter of AD7715 is a low -pass filter that has (SINX/X) response (also known as sinc). The transmission function of this filter is in the Z domain:

in the frequency domain

where n is the modulation The ratio of the device to the output rate, FMOD is the modulator rate.

FIG. 6 shows the frequency response of the filter with a deadline of 15.72Hz, which corresponds to the first filter frequency of the first filter of 60Hz. The picture shows DC to 390 Hz. This response is repeated at any side of the sampling frequency of the digital filter and the multiple of the sampling frequency of the filter.

The response of the filter is similar to the average filter, but it has more sharp attenuation. The output rate of the digital filter corresponds to the position of the first wave of the filter frequency response. Therefore, for a figure with an output rate of 60Hz in FIG. 6, the first wave of the filter is 60Hz. The (SINX/X) filter's trap is repeated with the number of the first waves. The filter provides attenuation of more than 100 decibels at these indamations.

The cut -off frequency of the digital filter is determined from the value of FS0 to FS1 digits from loading to setting registers. Different cut -off frequencies through FS0 and FS1 will not change the section of the filter response; it will change the frequency of the slot. The output update of the part corresponds to the frequency of the first slot.

Because AD7715 contains this low -pass filtering in the film, there is a stable time associated with the step function input, and after the step change changes, the data on the output is invalid until the stable time passes. The fixed time depends on the output rate selected for the filter. The stable time of the filter to the full standard level can be 4 times the output data cycle. For synchronous step input (using the FSYNC function), the stable time is 3 times the output data cycle.

Post filtration

The chip missionary provides samples at a 19.2kHz output rate, FCLK-in is 2.4576MHz. The digital filter on the tablet is extracted from the output rate corresponding to the programming output rate of the filter to provide data. Because the output data rate is higher than the Nyquist criteria, the output rate of the given bandwidth meets most application requirements. However, for given bandwidth and noise performance, some applications may require higher data rates. Applications that need higher data rates really need to be in ADAfter the digital filter of 7715, some post -filtering is performed.

For example, if the required bandwidth is 7.86 Hz, but the required update rate is 100 Hz, the data can be obtained from AD7715 at a rate of 100 HZ to give the -3 DB bandwidth of 26.2 Hz. The post -filtering can be applied here to reduce the bandwidth and output noise to 7.86 Hz bandwidth level, while maintaining the output rate of 100 Hertz.

Filtering can also be used to reduce the output noise from devices below 13.1Hz below 13.1Hz. At the 128 gain and 13.1Hz bandwidth, the output uniformly root noise is 520 NV. This is essentially device noise or white noise. Because the input is cut off, the noise has a basic flat frequency response. By reducing the bandwidth below 13.1Hz, the noise in the synthetic band can be reduced. A decrease in bandwidth by 2 times will cause output RMS noise to decrease by about 1.25. This extra filtration leads to a longer settlement time.

Simulation filter

As mentioned earlier, the digital filter does not provide any suppression at the integer multiple of the sampling frequency of the modulator. However, due to the high sampling rate of AD7715, these frequency bands only account for a small part of the spectrum, and most of the broadband noise is filtered out. This means that compared with the traditional converter without film filtering, the simulation filtering requirements before AD7715 are greatly reduced. In addition, because the co -mode inhibitory performance of the 95 -point decibel in this component expands to thousands of Hertz, the co -model n