The second generation Topswitch The II series is more cost -effective than the first generation of the topswitch series and provides some enhanced features. The TOPSWITCH II series will expand the power range of 100/115/230 input input from 100 watts to 150 watts, and the power range of 85-265 volt integrated input is expanded from 50 watts to 90 watts. This brings the advantages of Topswitch technology to many new applications, such as television, monitor, audio amplifiers, etc. Many significant circuit enhancement reduces the sensitivity of the circuit board layout and the transient of the circuit, and now makes the design more uniform

typical anti -gratifying applications.

It's easier. Standard 8L PDIP packaging options can reduce the cost of low power consumption and high efficiency applications. The internal lead frame of the packaging uses its six pins to directly transmit heat from the chip to the circuit board, so as to save the cost of the radiator. TOPSWITCH integrates all the functions required by the switch mode control system into a three -terminal single -chip integrated circuit: power MOSFET, PWM controller, high -voltage startup circuit, ring circuit compensation and fault protection circuit.

Note: 1. Packaging outline: to-220/32. Packaging shape: DIP-8 or SMD-8 3.100/115 volt, double input 4. Suppose proper heat dissipation to maintain the maximum switch connection temperature below 100 ° C. 5. Welded to 1 square meter (6.45 cm), 2 ounces of copper bag (610 gm/m) 6. P is the maximum actual continuous power output level under the conditions shown. The continuous power capacity in the given application depends on the heat environment, transformer design, required efficiency, minimum input voltage, input storage capacitance, etc. When using the upper switch II in the existing switching design

functional box chart.

Pointing function description

Drainage sales:

Output MOSFET drain connection. The internal bias current is provided by the internal switch high -voltage current source during the startup operation. Internal current.

Control sales:

Error amplifier and feedback current input pins used for duty control ratio control. The internal flow regulator is connected to provide internal bias current during normal operation. It is also used as a connection point for power bypass and automatic restart/compensation capacitor.

Source port number:

Y packaging-output MOSFET source connection for high-voltage power return. Public points and reference points of the first -side circuit.

P and G components-Public points and reference points of the first-side control circuit.

Power (high -voltage RTN) pin: (only P and G package) output MOSFET source connection for high -voltage power return.

Point configuration.

Topswitch II series function description

The upper switch is a self -biased and protective linear control current occupation ratio converter with open leakage output. High efficiency is achieved by using CMOS and as many functions as possible. Compared with the bipolar or discrete solutions, the CMOS process has significantly reduced the bias current. Integrated the external power resistor for current and/or providing an initial start -off current.

During the normal work period, the occupation ratio of the MOSFET internal output MOSFET decreased linearly with the increase of the control pipe foot current, as shown in Figure 4. In order to achieve all required control, partial pressure and protection functions, the drain and control pins are executed as described below.

The relationship between the duty cycle and control pin current.

(A) Normal operation and (b) automatic restarting waveform.

Topswitch II series function description (continued)

Control voltage power supply

Control pins voltage V is the power or bias voltage of the controller and drive circuit. An outer bypass capacitor that is closely connected between controlling the foot and the power pipe foot is needed to provide a gate -drive current. The total power capacity connected to the pin (C) also sets up the timing and control circuit compensation automatically. V is adjusted in any of the two operation modes. The stagnation adjustment is used for initial startup and overload operation. Paided regulation for separation of the duty cycle error signal and control circuit power supply current. During the startup process, the control pin current is provided by the high -voltage switch current source between the internal connection between the drain and the control foot. The current source provides sufficient current to supply the control circuit and charge the total external capacitor (C).

When the voltage reaches the upper limit of the threshold for the first time, the high -voltage current source is turned off, the PWM modulation and the output transistor are activated, as shown in Figure 5 (a). During normal operation (when the output voltage is adjusted), the feedback control current provides V power current. The parallel regulator can keep the voltage at 5.7 V through the diversion control pipe foot feedback current, and through the pulse width modulation error signal sensor R, the diversion control foot feedback current exceeds the required DC power supply current. The low dynamic impedance of the tube (Z) sets the gain of the error amplifier when used in the main feedback configuration. The dynamic impedance, external resistance and capacitors of the control foot determine the compensation of the power system control circuit.

If the total external capacitance of the control pin (C) should be discharged to a lower threshold, the output MOSFET is closed and the control circuit is placed in a low -current standby mode. High -voltage current re -connected and charged external capacitors. The charging current is displayed as the negative electrode, and the release current is displayed as the positive electrode, as shown in Figure 6. The stagnation automatic restart comparator is turned on and off the high -voltage current source by the high -voltage current source as shown in Figure 5 (b).Keep it in a window that is usually 4.7 to 5.7 V. The automatic restart circuit has a counter divide by 8 to prevent the output MOSFET from turning on again until eight discharge charging cycles ends. The counter effectively limited the power consumption of the upper switch by reducing the automatic restarting duty ratio to 5%. Automatically restart the circulation until the output voltage adjustment is reached again.

The reference source of the band gap

All the internal voltage of all critical switching switching from the temperature compensation band gap benchmark. The benchmark is also used to generate temperature compensation current source, which is trimmed by the current source to accurately set the oscillator frequency and MOSFET gate driver current.

oscillator

The internal oscillator performs linear charging and discharge of internal capacitors between the two voltage levels to generate a sawtooth wave for pulse width modulation. The oscillator sets the pulse width modulator/current limit lock at the beginning of each cycle. The nominal frequency of 100kHz is to minimize EMI and maximize efficiency in the application of power supply. The fine -tuning of the current benchmark has improved the frequency accuracy.

Pulse width modulator

The pulse width modulator drives the voltage mode control circuit by driving the duty duty ratio and current into the inverse proportional output MOSFET to the control pipe foot Generate a voltage error signal. The error signal on R is filtered through the RC network with a typical angle frequency of 7kHz to reduce the switching noise. The filtering error signal is compared with the internal oscillator sawtooth wave to produce a duty cycle. As the control current increases, the duty occupation ratio decreases. The clock signal from an oscillator sets a lock memory, which opens out the output MOSFET. The pulse width modulator resets the locks and close the output MOSFET. The maximum duty cycle is set by the symmetrical settings of the internal oscillator. The modulator has a minimum turnover time to maintain the current -switching current consumption has nothing to do with error signals. Note that the minimum current must be put into control sales before the duty cycle starts.

The gate driver

The gate drive is designed to open the output MOSFET to minimize the co -mode EMI. Gallery drive current has been fine -tuned to improve accuracy.

Error amplifier

Paiders can also perform the function of error amplifier in the initial feedback application. The piano regulator voltage is exported accurately by the temperature compensation band benchmark. The gain of the error placed is controlled by

to control the dynamic impedance of the pin. Control sales to cut the external circuit signal to the V voltage level. The control pipe foot current exceeding the power supply current is separated by parallel regulation, and flows through the voltage error signal.

Weekly current limit

(1) Normal operation, (2) automatic restart and (3) typical waveform of power outage reset.

The weekly peak of the drain current restriction circuit is usedThe MOSFET drive resistance is used as a sensing resistance. The current limitation comparator compares the output of MOSFET, the general Drainsource voltage V and threshold voltage. High leakage pole current causes V to exceed the threshold voltage and turn off the output MOSFET until the next clock cycle starts. The threshold voltage of the current limit comparator is temperature compensation, which is minimized due to changes in the valid peak current limit caused by the output MOSFET R temperature -related changes.

After the output MOSFET is turned on, the cutting -edge consumption circuit will inhibit current limit comparator in a short period of time. The anterior edge is set up, so that the current peaks caused by the reverse recovery time of the first -side capacitance and the secondary rectifier will not cause the switch pulse to end early.

After the hidden time of the front edge, the current limit can be reduced in a short time. This is due to the dynamic characteristics of MOSFET. In order to avoid triggering current limits in normal operations, the drain current waveform should be maintained in the shown package.

Shipping/Automatic Restart

In order to maximize the power consumption of the switching and switch, if the specified conditions continue, the turnover/automatic restart circuit will be in the automatic restarting duty cycle ratio 5 usually 5. When %are turned on and off the power. Lost adjustment will interrupt the external current that enters the control pin. V adjustment changes from the diversion mode to the above -mentioned stagnation automatic restart mode. When the failure is excluded, the power output is adjusted, the V adjustment returns the parallel mode, and the power supply returns to normal work.

Excessive protection

The temperature protection is provided by the precision analog circuit. When the knot temperature exceeds the thermal shutdown temperature (usually 135 ° C), the circuit is closed out and outputs MOSFET. Activate the power -on resetting circuit by removing and restoring the input power supply or instantly driving the control sales below the power -on resetting threshold, reset the 闩 lock and allow the power switch to restore the normal power operation. V is adjusted in the lagging mode. When the power supply is closed, the control sales will appear 4.7 V to 5.7 V (typical) jagged waves.

High -voltage bias current source

This current source allows the upper switch to deviate from the drain and the leaky foot, and charge the external capacitance of the control pin during starting or lagging operation (C). During the automatic restart and the shutdown shutdown during the shutdown shutdown. The current source is connected and disconnected at about 35%of the valid duty ratio. This duty ratio is determined by the ratio of control pipeline (i) and discharge current (i and i). When the MOSFET switch is output, the current source is turned off when working normally.

A schematic diagram of the 4W Topswitch II spare power supply of the 8 -lead PDIP.

Application instance

The following are only two of the possible Topswitch implementation. For other examples, see the data manual and design guide.

Use the 4 W backup power of the 8 -line PDIP

This power supply must be used for some spare functions (in real time clocks, remote control ports) that must be activated, even if the main power supply is closed.

5V secondary power supply is used to provide spare functions. The 12V non -isolation output is used for PWM controller for the main power supply and other first -side functions.

For this application, the size of the rectifier and the input filter is the same as the main power supply, which is not displayed. The input DC rail can change from 100 V to 380 V DC, which corresponds to the full -purpose communication input range. TOP221 is encapsulated in a 8 -pin power supply DIP package.

The output voltage (5V) is directly induced by the Zina diode (VR1) and the optocoupler (U2). The output voltage determines the sum of the voltage drop on the Qina voltage and the optocoupler LED (the voltage drop on the R1 can be ignored). The control pins of the output transistor driver of the optical coupling transistor driver. C5 bypasses the control pin, provides control loop compensation, and sets automatic restart frequency.

The leakage voltage peak of the transformer was absorbed by R3 and C1 through the diode D1. The bias winding is rectified and filtered by D3 and C4, which provides non -isolation 12V output. The output is also used for the set electrode of the bias optocoupler output transistor. The isolation 5V output winding is rectified by D2 and is filtered by C2, L1 and C3.

Use the 20 W -purpose power supply of the 8 -lead PDIP

FIG TOP224P in PDIP packaging works under the input voltage of GM 85 to 265. This example demonstrates the advantages of the high -power 8 -needle line framework used together with the Topswitch II series. This low -cost package directly transmits heat to the circuit board through six sources, eliminating the radiator and related costs. When input at low lines, the efficiency is usually 80%. The output voltage is directly induced by the optocoupler U2 and the Qina diode VR2. The output voltage is determined by the voltage drop on the voltage of the Qina diode (VR2) and the optocoupler (U2) LED and the resistor R1. By adjusting the value of the number of turns and the Qina diode VR2, other output voltage can be achieved.

The AC power supply was rectified and filtered through the BR1 and C1 to form a high -voltage DC bus, which was applied to a winding of T1. On the other side of the transformer one side is driven by integrated TOPSWITCH II high -voltage MOSFET. D1 and VR1 clamping transformer leaks caused by the front -edge voltage peak. The secondary winding of the power is rectified and filtered by D2, C2, L1, and C3 to generate a 12V output voltage. R2 and VR2 provide a slight pre -load on the 12V output end to improve the load adjustment during light loads. The bias winding is rectified and filtered by D3 and C4 to generate the bias voltage of the upper switch. L2 and Y1 safety capacitors C7 attenuation is caused by the high -voltage switching waveform of the one -to -polar side and the first to the second capacitanceThe co -mode launch current. The leakage attenuation between the L2 and C1 and C6 is launched by a differential module caused by a gradient in harmonic waves of trapezoidal or triangular junior current waveform. The C5 filtering controls the internal MOSFET gate driver's charging charging peak value, determine the automatic restoration frequency, and compensate the control loop with R1 and R3.

Key application precautions

General criteria

Maintaining the source of the source is very short. Use KelvinConnection to connect to the source of the control pink barrier container.

The ringing of the peak voltage and the drain voltage was minimized when closed. Under all conditions, including startup and overload, the use of Qina or TVS Zina diode restricted the drain voltage below the penetrating voltage of the upper switch. The maximum suggestion of the top2xx series is 200 V, and the corresponding maximum reflection output voltage of the first side is 135 V. See the 1996-97 data manual and design guide or the steps on our website 4: AN-16.

The design of the transformer should ensure that the invested current change caused by the saturation of the transformer should be within the absolute maximum normative range (as shown in Figure 13, and the first 100 ns is ∏i). As a guidance, for most common transformer iron hearts, this can be achieved by maintaining peak -magnetic flux density (under maximum current) below 4200 Gauss (420MT). Transformer electronic meter version. 2.1 (or higher version) provides necessary information for non -continuous conduction mode for continuous and Rev.1.0 (or higher versions).

During the test period, do not insert the upper switch into the heat " IC socket. External control pin capacitors may be charged to over -high voltage and cause damage to the upper switch.

When testing the upper switching device