Explanation

As a member of the Swift DC/DC regulator family, TPS54310 Low input voltage high output current synchronous buck-pwm converter integrated the required source of active source element. Including the characteristics listed on the substrate are real, high -performance, providing high -performance voltage errors under the conditions of the large -state is under transient conditions; the underwriting lock is 3 V. Slowly start the circuit to limit the impact current; the power output is good for processor/logic reset, fault signal and power sorting.

The TPS54310 device can be used to enhance the 20 -pin TSSOP (PWP) power board #63722; to eliminate the bulky radiator. TI provides assessment modules and SWIFT designer software to help quickly obtain high -performance power supply tools to provide design to meet the development cycle of corrosive equipment.

Figure Figure

Application information

shows a typical

TPS54310 application. TPS54310 (U1) can provide

TPS54310 schematic diagram

3.3V. In order to obtain the appropriate thermal performance, the power board under the TPS54310 integrated circuit needs

The input voltage

The input of the circuit is nominal 5 volts of DC power, and applied to the contact 1. Optional input filter (C2) is a 220μF POSCAP capacitor with a maximum allowable ripple current to be 3A. C8 is the decoupled capacitor of TPS54310, which must be as close to the device as much as possible.

Feedback circuit

The resistance separation network of R5 and R4 set the output voltage of the circuit to 3.3 V. R5, R2, R6, C4, C5, and C6 constitute the circuit compensation network of circuit. For this design, use type 3 topology.

Working frequency

In the application circuit, 350kHz operations are selected by keeping RT and SYNC opening. A resistor with 68-kΩ to 180-kΩ is connected between RT (pin 20) and simulation grounding, which can be used to set the switch frequency from 280 kHz to 700 kHz. To calculate the RT resistance, use formula 1:

Output filter

The output filter consists of 1.2 μH inductor and 180 μF capacitor. The inductor is a low-DC resistance (0.017Ω) type, CoilCraft Do1813P-122HC. The capacitor used is 4-V special polymer type, and the maximum ESR is 0.015Ω. Compensate the feedback loop, so that the frequency of unit gain is about 75khz.

The layout of grounding and power board

TPS54310 has two internal grounding (analog and power supply). Within TPS54310, simulated ground connection to all noise sensitive signals, and the power supply signal is connected to the power signal with a large noise. The power board must be directly connected to Agnd. The noise injected between the two grounds will reduce the performance of the TPS54310, especially under a higher output current. However, the ground noise on the ground surface can also cause problems with some control and bias signals. For these reasons, it is recommended to use separate simulation and power ground plane. These two planes should be directly connected at the integrated circuit to reduce noise between the two ground. The unique component of the power supply ground plane should be directly connected to the input capacitor, output capacitor, input voltage decoupling capacitor and PGND tube feet of TPS54310. The layout of the TPS54310 evaluation module represents the recommendation layout of the 2 -layer board. The document of the TPS54310 evaluation module can be found under the TPS54310 product folder and application description (TI Literature Number SLVA109) on the website of the Texas instrument.

Precautions for thermal performance layout

In order to run under a full -rated load current, the simulation floor must provide sufficient heat dissipation area. According to the environmental temperature and airflow, it is recommended to use a 3 -inch X -3 -inch plane of 1 ounce of copper, but it is not mandatory. Most applications have larger internal ground planes, and the power board should be connected to the largest area available. The additional area of the top or bottom also helps heat dissipation. When 3 A or larger operation is required, any available area should be used. Tong holes with a diameter of 0.013 inches are connected from the exposed area of the power board to the analog ground floor layer to avoid the through the hole through the hole. The six pores should be located in the power board area, and the other four over -holes are located under the device package. The size of the pores under the package can be increased to 0.018, but it is not in the exposed hot pad area. In addition to the ten -enhanced thermal pores that are recommended, other pores should include areas other than equipment packages.

Recommended grounding method of 20 stitch PWP power board

Detailed description

UVLO lock (UVLO)

The TPS54310 contains an underwriter locking circuit to keep the device disable when the input voltage (VIN) is insufficient. In the process of power -powered, the internal circuit remains not active until the vehicle recognition number (VIN) exceeds the nominal UVLO threshold voltage 2.95 V. Once the UVLO starting threshold is reached, the device starts. The device has been working until the vehicle recognition number (V in) is lower than the vehicle recognition number (UVLO) comparator. In the UVLO comparator, the 2.5-μS rising and decreased along the slip circuit reduces theThe possibility of turning off the device.

Slowly start/enable (SS/ENA)

Slowly start/enable pins to provide two functions; first, the pin is turned off by keeping the device until the voltage exceeds about 1.2 V startup. The threshold voltage plays the role of enable (closed) control. When the SS/ENA exceeds the enable threshold, the device starts. The reference voltage of the feed to an error amplifier rose from 0 V linear to 0.891 V within 3.35 ms. Similarly, the converter output voltage is adjusted within about 3.35 ms. The possibility of voltage lag and a decrease in 2.5μs decreased along the glue circuit that caused the possibility of enableness due to noise triggering.

The second function of the SS/ENA pin provides an external way. It is connected to a low -value capacitor between SS/ENA and agng to extend the slow start time. Adding capacitors to SS/ENA pins has two effects on startup. First, a delay occurs between the release of the SS/ENA pin and the starting output. The delay to the slow startup capacitor value is proportional, and it continues to the SS/ENA pin to achieve the enable threshold. The launch delay is:

Secondly, when the output becomes activated, the slow startup rate set at the outside is controlled and output to the rate of proportional to the slow startup capacitor to proportions. Before the rise, you can observe the short -term rise of the internal slow initiative. The slow startup time of the capacitor settings is:

Due to the short increase of internal rates, the actual slow start may be less than the approximate value above.

VBIAS regulator (VBIAS)

VBIAS regulator provides internal analog and digital modules, providing a stable power voltage when the temperature and input voltage change. VBIAS pin requires high -quality, low ESR, ceramic side electric container. It is recommended to use X7R or X5R electrical media, because their values are more stable at temperature. The barrier container should be placed near the VBIAS pin and returned to Agnd. Allow VBIAS external loading, but it should be noted that internal circuits need at least 2.70 V VBIAS, and external loading on VBIAS with communication or digital switching noise may reduce performance. VBIAS pins can be used as reference voltage for external circuits.

Voltage benchmark

The voltage reference system generates accurate voltage signals by adjusting the output of the temperature stable band gap circuit. During the manufacturing process, the band gap and zoom circuit of the error amplifier are trimmed at the output end of the error amplifier to generate 0.891V, and the amplifier is connected as a voltage follower. The fine -tuning program increases the high -precision adjustment of the TPS54310 because it eliminates the offset error in the scale and error amplifier circuit.

oscillator and pulse width modulation slope

Use synchronous tube feet as static numbersInput can set the internal fixed value of the oscillator frequency to 350 kHz or 550 kHz. If the application requires different operating frequencies, it can be connected to the RT pin and float the synchronous pins by connecting the resistor, and the oscillator frequency is adjusted from 280 kHz to 700 kHz from the outside. The switching frequency is similar from the bottom formula, where R is from RT to

Activity galaxy nucleus:

Error amplifier

High performance, broadband, broadband, broadband, broadband Width, voltage error Putting large device settings TPS54310, except for most DC/DC converters. Users can flexibly use various output L and C filter components to meet specific application needs. Type 2 or Type 3 compensation can use external compensation components.

pulse width adjustment control

The signal from the error amplifier output, oscillator and current restriction circuit is processed by PWM control logic. Refer to the internal box diagram, the control logic includes the PWM comparator, the door, the PWM memory, and the part of the adaptive dead area and the control logic block. During the steady -state operation of the current limit threshold, the PWM comparator output and the oscillator pulse string alternately reset and set the PWM memory. Once the pulse width is set up, the low -side effect transistor will maintain the minimum duration of the duration of the oscillator pulse. During this period, the pulse width modulation the slope discharged quickly to its valley voltage. When the slope starts charging, the low -side effect tube is closed, and the high -side effect tube is opened. When the pulse width modulation of the slope voltage exceeds the output voltage of the error amplifier, the pulse width modulation comparator resets the lock memory, thereby turning off the high -side effect tube and opening the low -side field effect tube. Before the pulse discharge of the next oscillation device is discharged to the pulse width, the low -end field effect transistor is kept open.

Under a transient conditions, the output of the error amplifier may be lower than the pulse width modulation of the slope valley voltage or the peak voltage of the pulse width. If the error amplifier is a high level, the pulse width is never reset to the lock memory, and the high -side effect is kept open until the oscillator pulses sends the signal to the control logic, closed the high -side effect tube, opens the low side side Field effect tube. The device works under its maximum occupation ratio until the output voltage rises to the adjustment setting point, and sets VSENSE to the same voltage as V. If the output of the error amplifier is low, the pulse width will continue to modify the locks, and the high -end FET will not be opened. The low -voltage side FET keeps turning on, until the VSENSE voltage is reduced to the range where the PWM comparator changes the state. TPS54310 can continue to sink current until the output reaches the adjustment set value. The referee

If the current limit comparator has a card trip exceeds 100 ns, the pulse width is used to reset the pulse width to the output of the error amplifier output by the pulse width. The high -side field effect tube is closed, and the low -side effect tube is opened to reduce the energy in the output inductance, thereby reducing the output current. ElectricityRepeat this process in each cycle of streaming comparator.

Dead zone control and MOSFET driver

The time control of the adaptive dead area control through the opening time of actively control the MOSFET drive Current flow. The high -voltage side drive is turned on when the grid drive voltage of the transistor of the low -voltage side effect is lower than 2 V. The low -voltage side drive is turned on at the high -voltage side effect transistor grille voltage when the voltage is lower than 2 V. The design of high -voltage and low -voltage drives has a source and exchange capacity of 300 mAh, which can quickly drive the power field effect of the transistor gate. Low -end drives are provided by the vehicle identification number, while high -end drives are provided by guide and sales. The guide circuit uses an external guidance capacitor and the internal 2.5Ω guide switch connected to the vehicle recognition number and the guidance pin. The integrated guidance switch improves the driver efficiency and reduces the number of external components.

Over -current protection

The current of the high -edged MOSFET and the differential amplifier through induction and compare it with the preset over current threshold to achieve a weekly current limit. High side MOSFET closed within 200 NS after reaching the current limit threshold. 100 NS cutting -edge consumer circuit can prevent current restrictions from accidentally jumping gates. The current limit detection occurs only when the current flows from the vehicle recognition number to the output filter. The load protection during the current remittance operation is provided by the heat.

Hot shutdown

When the knot temperature exceeds 150 ° C, the device uses the heating barrier and closed power MOSFET and disables the controller. When the knot temperature drops to 10 ° C below the heating checkpoint, the device is released from the shutdown state and started under the control of the slow starting circuit. When the overload state lasted several milliseconds, the heat clearance was protected. In the continuous failure state, the device continuously circulates; the soft startup circuit is started, and it is heated due to faults, and then closed when reaching the heat shutdown point.

Good power (PWRGD)

Good power supply voltage is monitoring voltage sensor. If the voltage on VSENSE is lower than 10%of the reference voltage, the PWRGD output is pulled down. If VIN is smaller than the UVLO threshold, or SS/ENA is low, or asserting the heat shutdown, PWRGD is also pulled down. When the VIN UVLO threshold, SS/ENA ENABLE threshold, VSENSE GT; 90%V, the leakage output of the PWRGD tube foot is high. The lagging voltage equal to a 3%voltage and a decrease of 35μs along the dehydration circuit can prevent good power comparison. Referee

Mechanical data

PWP (R-PDSO-G **) power board #63722; plastic small shape

The size of the valve body does not include mold flying or protruding parts.

The thermal performance of the package can be improved by connecting the hot pad to the external thermal plane.The thermal pad is connected to the back of the mold and the possible selected lead through electricity and heat.