Features

AD5544 Tel: 16 -bit resolution; the entrance is ± 1 lsb (level B); AD5554 Tel: 14 -bit resolution; minimum effectiveness Bit ± 0.5 (level B); 2 mAh full-standard current ± 20%, VREF ± 10 V; 0.9 μS precipitation time to ± 0.1%; Zero-scale reset; 4 independent 4-quadrant multiplication reference input; SPI compatibility, 3-line interface; dual-cushioning delivery device enable; multi-channel switching at the same time; internal power reset; temperature range: -40 ° C to+125 ° C; compact compact Type 28 guide SSOP and 32 -guide LFCSP.

Application

Automatic testing equipment; instrument digital control calibration.

General description

AD5544/AD5554 four-bit, 16-/14-bit, current output, digital modulus (DAC) designed to work within the range of 2.7 V to 5.5 V power supply.

Foreign reference input voltage (VX) determines the full marking output current. Integrated feedback resistance (R) provides temperature tracking. When the full-size voltage output, the external I-To-V precision amplifier is combined.

Dual buffer serial data interface provides high -speed, 3 lines, using serial data SPI and microcontroller compatible input (SDI), chip selection (CS) and clock (CLK) signals. In addition, when multiple packages are used, the serial data output pin (SDO) allows chrysanthemum chains. An ordinary, level -sensitive, load DAC selection (LDAC) input allows all DAC outputs to update all DAC outputs at the same time. In addition, the output voltage is forced to 0 when the system is connected to 0 when the system is connected.

MSB PIN allows the system to reset the assertion (RS) to force all registers to zero code at MSB 0, or forced to a half -scale code when MSB 1.

AD5544 is packaged in a compact 28 -lead SSOP and 32 lead LFCSP. AD5554 is encapsulated in the compact 28 lead SSOP.

EV-AD5544/45SDZ can be used to evaluate DAC performance. For details, see the User Guide of UG-285 Evaluation Board.

Preface Figure

Typical performance features

Operation theory

AD5544 and AD5554 include four 16 -bit and 14 -bit current output DACs, respectively. Each DAC has its own independent multiplication reference input.Both AD5544 and AD5554 use a three -line, SPI -compatible serial data interface, with configurable semi -standard asynchronous RS pin (MSB 1) or zero -point scale (MSB 0). In addition, a LDAC selection circuit can achieve 4 -channel synchronous update to achieve changes in the synchronous output voltage of the hardware.

Model converter (DAC)

Each part contains four current to R-R trapezoidal DAC. Figure 20 shows typical equivalent DACs. Each DAC contains a matching feedback resistor for external I-To-V converter amplifier. The RX pin is connected to the output end of the external amplifier. The IX terminal is connected to the reverse input of the external amplifier. The AX pin should be connected to the loading point, which requires a completely 16 -bit accuracy. These digital converters are designed to work under negative reference voltage and positive reference voltage.

V power pins are only used for the opening and level of logic driving the DAC switch. Note that the matching switch is used in series with the internal 5 kΩ feedback resistor. If the user tries to measure the value of R, the V power must be performed to achieve continuity. During the high -temperature application period, the additional V partial pressure tube foot is used to protect the substrate, and the zero -scale leakage current of the zero scale per 10 ° C is minimized to the minimum. DAC output voltage is determined by the digital data in V and below (D):

Note that the output polarity is the opposite of V polarity of the V vers of the DC reference voltage.

These digital converters are also designed to accommodate the exchange reference input signal. Both AD5544 and AD5554 can adjust the reference voltage within the range of -15 V to +15 V. The reference voltage input displays the constant nominal input resistance of 5 kΩ ± 30%. On the other hand, IA, IB, IC, and ID DAC output depend on code and generate various output resistance and capacitors. The choice of external amplifiers should consider the impedance changes generated on the reverse input node of the amplifier on the reverse input node of the amplifier. The feedback resistance is connected with the DAC trapezoidal resistance to control the output voltage noise. For the application of the multiplier mode, external feedback compensation capacitor C may be required to provide a critical damping output response of the reference input voltage step jump. Figure 21 shows the gain and frequency performance of 23PF external feedback capacitors connected to the 23PF external feedback capacitors on the IX and RX terminals on AD5544 and AD5554, respectively. In order to maintain good simulation performance, it is recommended to bypass 0.01 μF and connect with 1 μF. In this case, a clean power supply with a low ripple voltage ability should be used. The switching power supply is usually not suitable for this application due to high ripple voltage and PSS frequency dependency characteristics. It is best to guide the power supply of AD5544/AD5554 from the system simulation power supply voltage. Do not use digital power supply (see Figure 22).

Serial data interface

AD5544/AD5554 uses 3 lines (CS, SDI, CLK) SPI compatible serial data interface. The serial data of AD5544/AD5554 are sent to a serial input register by the clock in 18 -bit and 16 -bit data formats, respectively. First load the MSB bit. Table 5 Define the 18 data characters of AD5544, and Table 6 defines 16 data characters of AD5554. According to the data settings and data maintenance time requirements specified in the interface timing specifications (see Table 1 and Table 2), put the data on the SDI pin, and timing at the register on the edge of the CLK.

Only when the CS chip chooses a pins in a low activation state, the data can be input to the data. For AD5544, when the CS pin returns a high state of logic, only the last 18 bits enter the serial register; the additional data bit is ignored. For AD5554, when the CS pin returns a high state of logic. Because most microcontrollers output serial data with 8 -bit bytes, the data bytes of the three right -to -alignments can be written into AD5544. Keeping the CS lines between the first byte, the second and the third byte and the third byte transmission will lead to the successful serial register update.

Similarly, the data bytes of two right -right alignment can be written into AD5554. Keeping the CS line low between the first and second bytes will cause the serial register to be updated successfully.

When the data is correctly aligned in the displacement register, the transmission of the new data to the target DAC register is activated by the positive edge of the CS to the target DAC register. For AD5544, Table 5, Table 7, Table 8, and Figure 3 define the characteristics of software serial interfaces.

For AD5554, Table 6, Table 7, Table 9, and 4 define the characteristics of the software serial interface. Figure 23 and Figure 24 show the equivalent logic interface of the AD5544 key digital control pipe foot. AD5554 has a similar configuration, but it has 14 data bits. The other two pins, RS and MSB, provide hardware control to preset functions and DAC registers. If these functions are not needed, the RS pin can be bound to high logic. The asynchronous input RS PIN forced all input and DAC registers to zero code state (MSB 0) or half -scale state (MSB 1).

Powering and resetting When the V power is opened, the internal reset will be selected All inputs and DAC registers are forced to zero code state or half -scale state, depending on the MSB pin voltage. The V power supply should have a smooth positive slope and will not sag to obtain consistent results, especially in the area of V 1.5 V to 2.3 V. V power supply does not affect the power -on reset performance. DAC register data is kept at zero scale orHalf -scale settings are loaded until valid serial register data occurs.

ESD protection circuit

All logical input tube feet include reverse bias ESD protection Zina diode, which are connected to the ground (DGND) and V. Essence

Power supply order

As a standard practice, it is recommended to power on V, V and ground before any reference. The ideal order of power is as follows: AX, DGND, V, V, VX and digital input. The inconsistency of the order of power may increase the reference current, but once V and V are powered, the equipment will return to normal work.

Layout and power bypass

It is best to use a compact and minimum layout design. The wire of the input terminal should be as direct as possible, and the wire length should be the smallest. The grounding path should have low resistance and low inductance.

Similarly, in order to obtain the best stability, it is best to use high -quality capacitors to bypass the power. The power cord of the device should be used to use 0.01 μF to 0.1 μF. Low ESR 1 μF to 10 μF 钽 or electrolytic capacitors should also be used under V to minimize any transient interference and filter any low -frequency ripple (see Figure 26). Due to the decrease in the frequency of power suppression ratio (PSRR), users should not be the V application switch regulator.

ground

DGND and AX tube feet of AD5544/AD5554 are used for numbers and simulation ground. In order to minimize the digital ground, the DGND terminal should be remotely connected to a point of the simulation ground (see Figure 26).

Application information

AD5544/AD5554 is essentially a two -element multiplication DAC. In other words, they can be easily set to a single output operation. Full margin output polarity is inversely proportional to the reference input voltage.

In some applications, the capacity of a full four -elephant limit multiplication may need to be generated. The additional external amplifier (A2) that is configured as a puppet and amplifier is easy to achieve (see Figure 27).

In this circuit, the total gain of the first and second amplifiers (A1 and A2) provides 2, which increases the output voltage span to 20V. External amplifier bias using and reference voltage offset 10V can generate a complete four -element multiplication circuit. The transmission equation of this circuit shows that when the input data (d) increases from code 0 (v -10 v) to medium scale (v 0 V) to full scale (v 10 V), it will generate negative output voltage and positive positive positive The output voltage.

Reference

Select the current output D.When the benchmark used by AC, pay attention to the output voltage and temperature coefficient specifications of the benchmark. Select a precise reference of a low output temperature coefficient to minimize the source of errors. Table 10 lists some reference materials that can be obtained from Analog Devices, Inc.

The main requirements of the amplifier selection

The current steering mode is a amplifier with low input bias current and low input bias voltage. Due to the DAC code -related output resistance, the input bias voltage of the computing amplifier multiplied by the variable gain of the circuit. Due to the input offset voltage of the amplifier, changes in the noise gain between the two adjacent numbers will cause the output voltage to change. This output voltage changes are superimposed on the expected output changes between the two code, and the differential linear error is generated. If the error is large enough, it may cause the DAC non -monotonous.

The input bias current of the computing amplifier also displays off at the voltage output, because the bias current in the feedback resistor R.

The co -mode inhibitory of the operation amplifier is important in the voltage switch circuit, because it generates an error related to the code at the voltage output side of the circuit.

If the DAC switch is driven by real broadband, low -resistant sources (V and agng), they will soon stabilize. Therefore, the conversion rate and stability time of the voltage switch DAC circuit depends to a large extent on the output op amp. In order to get the minimum stable time in this configuration, minimize capacitors at the V node (voltage output node in this application) of DAC. This is completed by using a low input capacitor buffer large and careful circuit board design.

As shown in Table 11 and Table 12, the simulation equipment provides a wide range of amplifiers for precision DC and communication applications.

Character size