General description

WINBOND w881111af /w88112f supports ATAPI CD-ROM specifications (SFF 8020). Some ATAPI operations are performed by hardware and minimized system overhead, including ATAPI commands and data packet transmission, data transmission, ATAPI soft reset commands, and executing the driver diagnosis command. It also supports shadow drivers.

Winbond W88111AF/W88112F supports various types of microprocessors, DRAM and DSP.

W88111AF/W88112F supports the driving speed of up to 12/20 times. It also supports CD-ROM, CD-ROM/XA, CD-I, Video CD, Photo CD and CD Plus format.

The functions of W88111AF/W88112F include CD-ROM data solution, real-time errors. The 3rd layer of Reed Solomon product code (RSPC) correction, error detection and data transmission

W88111AF/W88112F has some The real -time ECC correction function of each P -word and Q character. It can also execute duplicate ECC transmission to improve the reliability of data.

W88111AF/W88112F supports DRAM with a maximum of 1 trillion bytes. It also supports the flexibility of the ring control register to increase the external RAM control.

The host interface of W88111AF/W88112F supports the use of PIO, single word DMA and multi -word DMA mode. There is an 8 -byte FIFO to increase the throughput of the IDE interface.

W88111AF/W88112F supports multiple pieces of transmission from external RAM to host.

W88112F supports accelerated error correction/detection to improve system performance.

W88112F supports automatic target head search, automatic head comparison and decoder interrupt status to reduce firmware overhead.

W88111AF/W88112F general features

T support the ATAPI CD-ROM standard (SFF 8020)

T supports CD-ROM, CD-ROM/XA, CD-I,, CD-I, Video CD, Photo CD, and CD Plus format

T supports the driving speed of up to 12 times

T supports various types of microprocessors and DSP

T supports various supports of various support Industry standard DRAM

T supports the environmental control register, which increases the flexibility of DRAM control

T supports CD-ROM data solution

T supports each P characterReal-time correction with a byte error with Q characters

T supports error detection of CD-ROM data

T support repeated error correction and detection channels

T8 byte by byte FIFO increases the IDE interface throughput

T transmits data to the host with PIO, single DMA, and multi -word DMA mode

T multi -piece transmission

T100 pin pqfp

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[ 123] W88112F enhancement function

T supports 45NS DRAM

t error correction/detection acceleration as high as 33%

T automatic target title search

T automatic title comparison

T decoder interrupt status collection

T high -speed driving status effective timing control

block diagram

[ 123] pin configuration

The register description

IR-index register (read/write) When URS (pin 32) is low, The microprocessor can access the index register. Value IR specifies which internal registers are accessed when URS (PIN 32) high -time microprocessors access. Note that after each reading or writing any register, the 4 minimum effective bits of IR will increase, except for PFAR (00H). Since IR does not automatically increase from 00h to 01H, the continuous read address 00h will repeat the register PFAR (00H). This feature speeds up the Atapi command package.

PFAR-package FIFO access register (read 00h) When scod (20H.2) is high, the ATAPI command package from the host is advanced from 12 bytes to receive groups. Mark Tendb (01H.6) to check whether the data packet FIFO is full. The microprocessor can read the ATAPI command package by repeating the register PFAR (00H). Once the microprocessor reads PFAR, once the microprocessor reads the PFAR, the return value FFH is returned.

Package FIFO can also be used to receive command parameters less than 12 bytes. First, the control bit Scod (20H.2) is set to high to select the package FIFO port designed by ATAPI data. When DRQ (37H.3) changes from 0 to 1, the low position of ATBLO (34H) is locked as the FIFO threshold. When the number of bytes in FIFO reaches a threshold, the logo TENDB (01H.6) becomes low activation and logo FPKT (30H.1) to high activation. Once FPKT becomes higher, any data is written into the ATAPI data port.

Interrupt control register (write 01H) bit 7: pfneen-package FIFO non-airIf the bit is high, when PFNEB (01H.7) becomes low activation, it activates UINTB (pin 36).

bit 6: TENDEN-transmission end interruption. When Tendb (01H.6) becomes low activation, if the bit is high, activate UINTB (Pin36). Tan Deng is the choice of high -end driver if the host is in Hiien (2EH.7).

bit 5: SRIEN-sector's ready interruption When SRIB (01H.5) becomes low-electricity, if the bit is high level, activate UINTB (PIN36)

bit bit 4, 3, 2: Reserve

bit 1: DTEN-data transmission enables SET DTEN HIGH to enable data transmission logic. This bit should be set to trigger data transmission before any of the following items:

· The host writes the data packet FIFO

Reading DF7 In order to reduce the interference of the microprocessor, the following operations:

· Triggering ADTT (17h.2)

· Dangda APKTEN (18H.7) and the drive is selected for selection

bit 0: Reserved the reasons for the reasons for the interruption (read 01H) bit 7: PFNEB-package FIFO non-empty interrupt logo as the data packet FIFO through

Atapi data port. If PFNEEN (01H.7), when PFNEB becomes low -activated, activated UINTB (pin 36) has been enabled. After the microprocessor reads the last byte through the register, the PFNEB is disabled by the power factor correction (00H).

bit 6: Tendb-transmission end interruption logo at the end of the data transmission, this bit becomes a low position:

· The host writes the data packet FIFO

· From the obedience External RAM read host

· The host reads DF7 (47H)

marked TDIR (30H.5) and FPKT (30H.1) from register DF0 (40H) What type of transmission end.

If Tenden (01H.6) is enabled, when Tendb becomes low activation, activate UINTB (Pin36).

This logo will be discontinued to write any value to the register Tack (07H).

bit 5: SRIB-sector's ready interrupt sign. This bit is used to indicate that a sector is ready to access. Read the register STAT3 (0FH) to stop SRIB.

bit 4: HCIB-host command interruption sign is activated by the following incident:

· If ARST is enabledIEN (2FH.1), the host will issue the ATAPI soft reset command

· If the shien (2eH.2) is enabled, the host will send an order to the non -existing drive

[123 ]. If if The hiien (2EH.7) is used, and the host will issue an execution of the driver diagnosis command

· If the hiien (2eH.7) is enabled, then atac (2FH.6) will become a high activation state

] · If Hiien (2EH.7) is enabled, set the host position SRST bit in the ATAPI device control register 3: TBSYB-transmission busy logo When the following events are triggered to the host data transmission, this bit becomes low activation: [123 123 ]

· Write any value to the register THTRG (06H)

· Settitt Adtt (17h.2) High host reads the last byte to be transmitted, TBSYB will be discontinued. Bit 2: MBTIB-multiple transmission interrupt logo This bit is activated by the following incidents:

· When RPIEN (2AH.5) is enabled, RPINT (30H.3) becomes a high activation state

] When MBKIEN (13H.2) is enabled, MBTI (30H.4) becomes a high activation state

Micro -processor can read the register MISS2 (30H) to determine which event occurs. Bit 1: DFRDYB-data FIFO is ready to transmit data transmission, and automatically fills 8 byte data FIFO. This drill is used to indicate that the data FIFO is ready for the host to read.

bit 0: SCIB-Subcode interrupt logo If scinen (2ch.4) is enabled, when one of the following events is enabled, this bit becomes low activation:

· ISS (22H (22H (22H .0) Beginial activation status

· NESBK (22H.1) becomes high activation state

· MSS (22H.2) becomes high activation state

When the subcode is interrupted, the microprocessor can read the reasons why the register Subsa (22H) is read to determine the interrupt. Write the register Sciack (22H) to interrupt the sub -code.

Preliminary/Confident (Reading/writing 02H/03h) Before triggered data transmission, 12 -bit transmission byte/word counter. The number of bytes should be reduced by the number of bytes when the counter is transmitted with 8 -bit data. Use 16 -bit data transmission. After the host reads a byte or word, the counter will be reduced by one until the counter is zero, and the transmission end interruption is activated.

TACL/TACH-Transmission Address Cooler- (Written 04H/05H) Before triging data transmission, the external RAM address to be transmitted through 16-bit transmission address counter should be set. This number in this counter specifies the first data address that is used to start with the beginning of the block. The block number should also be specified through the transmission block register TBL/TBH (24 hours/25 hours). After the host reads a byte/word, TACL/TACH increases to the next available data address.

TBL/TBH — transmission block register (read/write 24 hours/25 hours) Before triging data transmission, the external RAM block of the data to be transmitted should be transmitted through the transmission block register. TBL/TBH forms a nine -bit register to specify the first RAM block transmission, while the TACL/TACH (04H/05H) specifies the relative to this memory block. At the end, the number of RAM blocks in TBL/TBH will not automatically increase each transmission, unless the register MBTC0 (12H) is used by multiple pieces. THTRG-transmission to host trigger register- (write 06h) No matter what the written value is written, this register is used to trigger data transmission.

When UDTS (1FH.6) is lower, THTRG is triggered from external RAM to the data transmission of the host. Trigger THTRG automatically fills the data FIFO, and then mark DFRDYB (01H.1) when the data FIFO is ready to become low activation state.

When UDTS (1FH.6) is high, the path of the data transmission is from the register DF0-DF7 (40H-47H) to the owner. In this case, the data count of less than 8 should be set to use the register TBCL (02H) to trigger THTRG and the position UDTT (1FH.7). After the THTRG is triggered, it should be set to 1 and 0.

TACK-Transmission Confirmation- (Written 07H) Write to the register TACK to make Tendb (01H.6) and its corresponding microprocessor interruption.

The four registers of the head 0 to 3-head registers (read 03h to 07h) are used to save head-byte information of each sector. The title register should be read immediately after Stavab (0.7) becomes low -activated state. Note that if the headline is set up when ECC is enabled, it is not credible. If the bit Shden (0BH.0) has been enabled, the register HEAD0-3 is used to save the subtitles by the subtitles.

BIAL/BIAH-Initial address register- (write 08H/09h) Before enabling the external RAM buffer, it should be set/biah to control the first byte to follow the data of each data sector to synchronize the synchronization of each data sector. Essence The RAM block used to buffer is added by the number in the register DDBL/DDBH (28H/29h). In order to facilitate subsequent data transmission microprocessors, appropriate value should be set upAfter being placed in BIAH/BIAL (Mode 1 is FF, F0H, Mode 2 is FF, E8H), the first user data byte will be blocked at 00h at each data of each data.

BACL, the Bach-buffer address counter (read 0AH/0BH) enables the external RAM buffer, the cushion writer will automatically increase the value specified by BIAL/BIAH, and a data word is buffered each time. EIAL/EIAH-ECC initial address register- (read 08H/09h, write 0CH/0DH) EIAL/EIAH is used to maintain the initial address offset of the data blocks that must be corrected. The content BIAL/BIAH (08H/09H) will automatically load them to EIAL/EIAH at each data synchronization, so that it does not need to read or write EIAL/EIAH during the normal operation. ECC's RAM block is controlled by the register DDBL/DDBH (28H/29h).

SCBL/SCBH-sub-code block register- (Read/write 26h/27h)

SCBL/SCBH forms a nine-bit register, which contains the latest available sub-data block number to read Take. The number in the SCBL/Scbh plus 1 point to the RAM block, that is, the buffer passing into the child code. The number in the SCBL/ScBh adds a buffer at the end of the sub -code.

DDBL/DDBH-decoding data block register (read/write 28h/29h) DDBL/DDBH constitutes a nine-bit register, which contains the latest decoding data block decoder interruption. The number of this block is applied to the specified TBL/TBH (24 hours/25 hours) before the data transmission of the host. This decoding data block number plus 1 point to buffer input serial data and add a DRAM block buffer at the end of each data block.

Ctrl0-Control register 0- (write 0AH) bit 7: Dece-decoding logic enables to set this bit to the high decoding logic. Bit 5: Edcen-error detection and correction The use will be set to highly enable ECC and EDC logic to enable high.

bit 4: Acen-automatic school correction When it is set to high during the period 2 ECC, the error correction type is automatically determined by the format position in the format of the subtitled byte. When this is in the mode 2 ECC, the error correction type is controlled by F2RQ (0BH.2).

bit 2: BUFEN-buffer enable the DSP data buffer to be enabled to enable it. When this bit is a high register head 0-3 (04H-07H) and Zi 0-3 (14H-17h) is the serial data from the external RAM instead of input. When BUFEN is low, any settings of Qcen or PCEN are meaningless.

bit 1: qcen-q code word correction When it is high, Q code wordRSPC correction logic is enabled.

bit 0: pCEN-P code word correction When it is high, when the bit is high, the P code word RSPC correction logic is enabled.

Ctrl1-control register 1- (write 0bh) bit 7: SIEN-synchronous insertion Established when the bit is high, the sector boundary is determined by the internal simultaneous inserting logic.

bit 6: SDEN-synchronous detection Enable When the bit is high, the sector boundary is determined by the input serial data.

bit 5: DSCREN-The interpretor enables the setting to enable the disruption logic to enable it.

bit 4: Cwen-correction data is written and enabled to set this bit to high. You can write the corrected data into the external RAM.

bit 3: M2RQ-Mode 2 ECC request to set this bit to high-enable mode 2 ECC correction logic. Mode 1 ECC correction will be executed as low.

bit 2: F2RQ-Form 2 Request

If this bit is set to high, the request processing data M2RQ (0BH.3) high in mode 2 form-2 format.

bit 1: MCRQ-mode byte examination, please check the fourth head bytes when the bit is high, and set the M2RQ (0BH.3) to determine whether to perform ECC correction Essence

bit 0: SHDEN-subtitle switch is enabled. When the bit is high, the register HEAD0-3 is used to provide sub-title bytes. STAT0-Status register 0- (read 0CH) bit 7: CRCOK-cyclic redundancy check is normal. This bit is used to indicate whether the circulating redundant check that can be used recently can be passed.

bit 6: IlSyn-illegal synchronization mode

If SDEN (0BH.6) is high, when the synchronous mode is detected by less than 2352, it should The bit becomes high after/insert the number of bytes after the last synchronization mode. Bit 5: NoSyn-No synchronization mode

If Sien (0bh.7) is high, when the synchronization mode is not detected at 2352 bytes, this bit becomes high. After synchronization mode. Bit 4: LBKF-long block logo

If Sien (0BH.7) is low, when the synchronization mode is not detected at 2352 bytes, the bit becomes high. After the pattern. Bit 3: WSHORT-WORD SHORT When the serial data rate is too high, it cannot be by W88111AF/W881112F.

bit 2: SBKF-short block logo If SDEN (0BH.6) is low, when the synchronous mode is detected less than 2352 bytes, the bit becomes high after detecting/inserting the previous synchronization mode after the previous synchronization mode Essence

bit 2: F2RQ-Form 2 Request if this bit is set to high, then the request processing data M2RQ (0BH.3) high in mode 2 form-2 format.

bit 1: MCRQ-mode byte test request When the bit is high, the ECC logic will check the fourth header byte and set M2RQ (0BH.3) to determine whether to perform ECC correction Essence

bit 0: SHDEN-subtitle switch is enabled. When the bit is high, the register HEAD0-3 is used to provide sub-title bytes. STAT0-Status register 0- (read 0CH)

bit 7: CRCOK-cyclic redundant inspection is normal. This bit is used to indicate whether the circular redundancy check that can be used recently can be passed.

bit 6: IlSyn-illegal synchronization mode If SDEN (0BH.6) is high, when the synchronization mode is detected less than 2352, the bit becomes high to detect/insert the word after the last synchronization mode. Section number.

bit 5: noSyn-without synchronization mode. If Sien (0BH.7) is high, when the synchronization mode is not detected at 2352 bytes, this bit becomes high. After synchronization mode.

bit 4: LBKF-long block logo If Sien (0BH.7) is low, when the synchronization mode is not detected at 2352 bytes, the bit becomes high. After the pattern.

bit 3: WShort-Word Short when the serial data rate input is too high and cannot be by W88111AF/W88112F.

If SDEN (0BH.6) is low, when the synchronization mode is less than 2352 bytes, the bit becomes high after detecting/inserting the previous synchronization mode.

bit 1: FDIF-fast decoder interrupt sign. If FDIEN (10H.3) is enabled, when the head/sub-headwheel is prepared, the level becomes higher before the ECC is completed and the CRC is completed. At the same time, UINTB (pin 36) and STAVAB (0FH.7) become a low activation state, thereby accelerating the following microprocessor operation. When CRC is completed, FDIF is suspended. When CRC is completed. Therefore, if Fdien (10H.3) is enabled, CRCVAB (10H.7) should be used to determine the interruption activation, CRCOK (0CH.7) is available. Bit 0: UEBK-blocks that cannot be corrected by blocks are used to indicate at least one data is corrected in the latest available data blocks. STAT1-Status register 1- (read 0DH) bit 4: HDERA-head erasing. If at least one erase is detected in the head bytes that do not include mode bytes, this bit is high. The deleting mode bytes will cause RMOD3-0 (0EH.7-4) to become higher. Bit 0: SHDERA-subtitle erase is cleaned if the erase of two bytes is detected in at least one subtitled byte by byte by byte by byte, which is high.

If BUFEN (0AH.2) is disabled, wipe it from the pin C2PO. Otherwise, the title and subtitle can be retrieved from the external RAM when buffering the sector.

DHTACK-DRAM to the host transmission confirmation- (0EH) When writing dhtack, no matter what data was written, the data transmission end of TENDB (0EH.6) from the external RAM to the host will be invalid. STAT2-Status Register 2- (Read 0EH)

bit 7-4: RMON [3: 0] -RMOD [2: 0] Direct Locking, if there is, RMOD3 is one of the other 5 in the high mode bytes. If the pattern byte wipe is detection.

bit 3: Mode 2-Mode 2 Selected signs that reflect M2RQ (0BH.3). Bit 2: Nocor-non-correction If the EDCEN (0AH.5) and Qcen (0AH.1) or PCEN (0AH.0) enable ECC logic if the position is enabled, then if the ECC logic interrupts the following situation, it will become high: [[[[[[[[[[[[[ 123]

· Cwen (0bh.4) was disabled.

· The mode is not matched when the MCRQ (0BH.1) is detected.

· The mode erase was detected when MCRQ (0BH.1) was detected. If you set the C2PO logo for the fourth headline, indicate unreliable mode data.

· When the ECC logic is set to mode 2, the window 2 is enabled. Do not correct Table 2. Form 2 can be enabled by the control bit F2RQ (0BH.2) or the table unit in the subtitle. If Acen (0AH.4) is enabled, it is byte.

· When the ECC logic is set to mode 2 and enables ACEN, the window position is erased. If the form position is eradicated, the C2PO logo is set up for the two table units in the subtitles.

· When SDEN (0BH.6) is enabled, iLSyn (0CH.6) becomes higher. Bit 1: RFERA-original form wiper When the table unit is detected, this digit becomes higher. If the two table units in the sub -mode byte byte byte (byte 18 and 22) are set up with the C2PO logo. When SRIB (01H.5) becomes low activation, RFRA becomes effective and keeps valid until the next stop synchronization.

bit 0: roform-original watch unit If the format of the sub-mode byte by the serial data is high, this bit is high. RFORM format becomes valid when the sign SRIB (01H.5) becomes low when activated, and keeps valid synchronization before the next block

FRST-firmware reset register- (write 0FH) Write to the register Frst. No matter what value is written, most of the logic of w88111AF/W88112F will be reset, except the following:

· The register CCTL1 (1AH) And output pin clko

· Register DSPSL (1BH)

· Register HICTL1 (20H)

· Register SICTL0 (21H)

· Register RAMCF (2AH)

· Register MEMCF (2BH)

· Register SICTL1 (2CH)

· Register MISC0 (2EH)

· Register MISS1 (2FH )

· The register MISC1 (2FH.7-5, 3-0)

· Atapi driver select the bit DRV

· Atapi device control the SRST in the register in the register And nien bit (2FH.1) is set by firmware resetting.

STAT3-Status register 3- (read 0FH) bit 7: STAVAB-effective state effective.

bit 5: ECF — Error correction logo This bit is used to indicate at least one byte that is already available in at least one byte.

bit 4: EINC-ECC incomplete sign If Eincen (10H.1) is enabled, the correction of the following block is triggered before the previous block is completed. When Eincen is enabled, Einc will become higher.

bit 1: C2DF-C2 is detected in the block logo. If C2WEN (10H.2) is high, when at least one C2PO logo is detected, the C2DF becomes high in the previous neighborhood.

bit 6,3,2,0: Reserved the control writing register (write 10h) bit 7: Definition 0

bit 6: swen-synchronous writing and enabled if this bit is high if this bit is high. The change of BUFEN (0AH.2) will be synchronized to the end of the next sector. The buffer of the C2PO logo is also opened by Swen If C2WEN (10H.2) and BUFEN (0AH.2). Bit 5: SDSS-sub-code and DSP synchronization The bit of CD-DA format data synchronization. If this bit is high, the serial data of the external RAM will start the sub -code block at the first left lower passage bytes after the end.

bit 4: DCKEN-Digital signal processor clock is enabled if the bit is high, the internal decoder logic uses clock from DSP. DCKEN should be set to high at the dece(0AH.7) Before high.

bit 3: fdien-fast decoder interruption. If FDIEN (10H.3) is set to high, the head/subtitle byte is ready before the completion of the ECC and CRC:

] · · FDIF (0CH.1) –1

· Stava (0FH.7) - 0

· SRIB (01H.5) – 0 read register STAT3 (0FH) Turn off the above SRIB (01H.5) to 1. If the fdien (10H.3) is set to high, the following events will occur when the CRC is completed:

· fdif (0ch.1) —0

· CRCVab (10 hours 7 minutes) - 0

· SRIB (01H.5) – 0

· CRCOK (0CH.7) can use the read register STAT4 (10h) to ban the above SRIB as 1.

SRIB (01H.5) becomes a low activation state when it is rapidly interrupt. If FDIEN is enabled, CRC ends. CRCVAB is applied to whether CRCOK is ready when determining that SRIB becomes low.

bit 2: C2WEN-C2 logo is written and enabled. If the bit is set to high and bufen (0AH.2) is high, the C2 logo that enters the serial data will be locked in the external RAM. If Swen (10H.6), this operation will be synchronized to the end.

bit 1: DRST-decoder reset will set this bit to the high-will reset the decoding logic. DRST automatically clear.

bit 0: Eincen-ECC incomplete interruption. If the bit set is high, the correction of the current block is triggered before the amendment of the previous block.

STAT4-Status register 4 (read 10h)

bit 7: CRCVAB-CRC is valid

If FDIEN (10H.3) is enabled, CRCVAB is completed when CRC is completed Become low activation state. Reading this If FDIEN is enabled, the register will stop SRIB (01H.5) due to the completion of CRC.

bit 6-0: Reserve CRTRG-Correction Trial trigger- (write 11h) Write to the register CRTRG. No matter what data is written, the decoding logic will be triggered to execute another correction sequence of the same piece.

bit 7-1: Reserved bit 0: CRRL-Correct the retry register load

When writing the register CRTRG (11H), the bit is set to high, and reload EdCen (0Ah. 5) Settings, qcen (0AH.1) or PCEN (0AH.0) for used for itDecoding logic.

MBTC0-Multi-block transmission control 0- (read/write 12h) This register is only used for W88111AF to specify multiple transmission logic behaviors. This host interface supports multiple block transmission, without the need for microprocessor intervention:

MBC [4: 0] - The number of blocks to be transmitted is reduced 1 (for example 3)

· TBCL (02H), TBCH (03H) - The number/word number to be transmitted in each block is reduced 1 (for example 1175)

· tacl (04h), tach (05H), the starting point of the block (the block ( For example, F4H, FFH)

· TBL (24 hours), TBH (25 hours), the first block number of the first block to be transmitted (example 5)

· Atblo (34h) Atblh (35H) -The total number of bytes to be transmitted (eg 9408)

· Adtt (17 hours 4) Note: Stbcen (18H.3) should not be set in multiple transmission operations. When ADTT is set, the host will receive Hirq, check the status, and then start reading data. After the host reads the last byte/word of a block (except the last block), perform the hardware sequence as follows:

· TBCL (02H), TBCH (03H), reload

· TACL (04H), tach (05H), reload

· TBL (24 hours), TBH (25 hours), automatic increase

· MBC [4: 0] - Automatically Reduction

Tendb becomes active at the end of the last piece of data transmission. Bit 7: MBVAB-Multi-counter effective sign is used to indicate that multi-counter MBC [4: 0] is stable enough to be a microprocessor.

bit 6: MBINC-Multi-increase sign

If the microprocessor is set up with INCMBC (13H.0) and multiple pieces, then the bit becomes a high excitement. Finish. Bit 4-0: MBC [4: 0] -We multiple counter before triggering multiple pieces of transmission, the number of blocks to be transmitted is reduced to MBC [4: 0]. If MBC [4: 0] is zero, execute single transmission. MBTC1-Multi-block transmission control 1- (read/write 13h) bit 7-3: Reserved bit 2: MBTIEN-multiple transmission interruption. ] The block counting is not zero, then blocking.

bit 1: MBTFEN-multiple transmission interrupt logo is enabled. If the bit is high, when the data transmission of each data block is over, if the block count in MBC [4: 0],Not zero.

bit 0: INCMBC — Increased multiple counters to set the bit to the high of the multi -counter MBC [4: 0]. This function is transmitted to the host through the DMA mode in the data. Because the data count is not specified in the DMA mode transmission, the number of blocks to be transmitted can be increased before the new block is available.

Enhance the control register (write 14h) bit 7-2: Reserve 1: IR7F-provides a logo UTBY at IR7. When the bit is high, mark UTBY (1FH.7) can be read by the index register. 7 monitoring.

bit 0: DISAI-Disable automatic increase When the bit is high, the automatic increase in the RACU/RACH/RACL address counter has been disabled. Note that before RFTRG (2AH.6), DISAI should be 0.

The 0th child to the third child-the subtitle register (read time: 14h to 17h) These registers are used to save the sub-title bytes. If BUFEN (0AH.2) is disabled, the subtitle byte is locked from the serial data that is transmitted. If BUFEN (0AH.2) is enabled, the Subheader bytes are retrieved from the external RAM.

The automatic sequence trigger the register (written into 17h) After the trigger operation is completed, the following position will be cleared by itself.

digit 7: Reserved bit 6: CSRT-Clear soft retirement trigger to set this bit to the level of the ATAPI device control register SRST.

bit 5: DSCT-Disk Search to complete the trigger. If ABYEN (18H.1) is high, setting DSCT HIGH will trigger the following operations:

· Set BSY

] · Differential scanning heat method (37H.4) --1

· Clear Bsyn (18H.1) is low, then set DSCT HIGH to set DSC (37H.4) to 1. Bit 4: SIGT-ATAPI signature trigger will set this bit to high to use the ATAPI signature initialization task register.

· Atfea (31 hours) —00 hours

· Atr (31H) –01H

· Atint (32 hours) –01 hours

[123 ] · · Spa center (33 hours) - 01 hours

· Atblo (34 hours) –14 hours

· Atbi (35 hours) --ebh

· Atsta (37 hours) —00 hours

Note that the register ATDRS (36H) is not cleared by triggering SIGT to comply with the ATAPI protocol.

bit3: CPFT-Clear package FIFO trigger will set this bit to the high-level data packet FIFO. Bit 2: ADTT-automatic data transmission trigger If PIO (1FH.2) is high, set ADTT high will trigger the following PIO data transmission sequence:

· Set BSY

· DTEN (01H (01H .2) –1

· Scott (20H.2) –0

· Atint (32 hours) –02 hours

· If StBCEN (18H 18H is enabled ), Then Atblo/Atbhi (TBCL, H+1) '2 data transmission logic will start to automatically fill the data FIFO. The following order is executed when DFRDYB (01H.1) becomes low:

· DRQ (37H.3) —

· Clear BSY

· · · · · · · · · Hirq (2 hours and 3 minutes) 1 After the interruption is detected, the host will check the status and then read the data. Stbcen (18H.3) is not used in automatic multiple transmission. On the contrary, Atbul, ATBHI should be set through the firmware to: (mbkc+1) '((TBCL, H+1)' 2) If PIO (1FH.2) is low, set ADRTG high will trigger the following DMA data reading Sequence:

· Set BSY

· DTEN (01H.1) –1

· Scott (20H.2) –0

] · Atint (32 hours) ─ 02 hours 1: DRQT-DRQ trigger If PIO (1FH.2) is high, set this bit to high to trigger the following hardware sequences:

· DRQ (37h.3) –1

· Hirq (2 hours and 3 minutes) 1 When PIO low (DMA mode) is PIO (DMA mode), this bit should not be triggered. Bit 0: SCT-State Complete the trigger that sets this bit to high to trigger the following hardware sequences:

Preliminary/confidentiality

· check (37h.0)-check (3eH.0) (3eH.0)

· Corrosion (37H.2) -Accioccal oxide (3eh.2)

· Dr. (37H.6) - Dr. (3EH.6)

· Atint (Atint ( 32 hours) - 03 hours

· Clear BSY

· Hirq (2 hours 3 minutes) 1

· apkten (18H.7) –1, if Autoen (18H (18H (18H (18H .4) Very high

· Rising (18H.5) - 0 After the interruption was de