Features

10 -bit digital converter; the maximum conversion rate of 170 MSPS; low PLL clock jitter at 170MSPS; automatic gain matching; automatic offset adjustment; 2: 1 input multi -path reusopter ; Break the electricity through dedicated pins or serial storage; 4: 4: 4: 4, 4: 2: 2, and DDR output format mode; variable output driving strength; stagnation field detection; external clock input; re -generated Hsync output; can Programming output high impedance control; Hsyncs of each VSync counter; green synchronization (SOG) pulse filter; lead -free packaging.

Application

Advanced TV; plasma display; LCD digital TV; HD TV; RGB graphics processing; LCD display and projector; scan converter.

General description

AD9984A is a complete 10 -bit, 170 millisecond/second single -piece simulation interface, which is optimized to capture YPBPR video and RGB graphics signals. Its 170 MSPS encoding rate capacity and 300 MBA full power simulation bandwidth support all HDTV video modes with up to 1080P, as well as the graphics resolution of the UXGA (1600 × 1200, 60 Hz).

AD9984A includes a 170 triple ADC with an internal benchmark, a PLL and programmable gain, offset and clamp control. Users only provide 1.8V power and analog input. Three -state output can be powered from 1.8V to 3.3V.

The PLL on the AD9984A film from three levels (for YPBPR video) or horizontal synchronization (for RGB graphics) generate sampling clock. The frequency of the sample clock output ranges from 10 MM to 170 MM. Through the internal coast, the locking loop maintains its output frequency without synchronous input. Step 32 provides the phase adjustment of the sampling clock. Maintain output data, synchronization and clock phase relationship.

The automatic offset function can be enabled to automatically restore the signal reference level and calibrate any offset difference between three channels. You can enable the gain matching function between automatic channels to minimize any gain between three channels.

AD9984A also provides complete synchronization processing for compound synchronization and green applications. The clamp signal is generated inside, or it can be provided by the user through the clamping input pin.

AD9984A is manufactured by advanced CMOS technology, and uses a low -section four -table package (LQFP) or 64 -leading frame chip chip -level packaging (LFCSP) that saves space -saving, lead, and 80 leadership. Specify within the temperature range of 70 ° C.

Operation theory

AD9984A is a complete integrated solution partyThe case is used to capture and digitize an analog RGB or YPBPR signals in order to display it on high -end TV, tablet monitors, projectors and other types of digital monitors. In the high -performance CMOS process, the interface can capture signals with a pixel rate of up to 170MHz.

AD9984A includes all necessary input buffer, signal DC recovery (clamp), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. All controls can be programmed through 2 -line serial interface (IC). The complete integration of these sensitive simulation functions makes the system design simple and clear, and the sensitivity to the physical and electrical environment is lower.

The typical power consumption of this device is less than 900 MW, and the operating temperature range is 0 ° C to 70 ° C. There is no need to consider environmental factors.

Digital input

All digital input work on AD9984A to 3.3V CMOS levels. The following digital input is 5V tolerance voltage (that is, 5V does not cause any damage: Hsync0, Hsync1, vsync0, vsync1, SOGIN0, SOGIN1, SDA, SCL, and clamping clamps. 123] AD9984A has six high impedance simulation input pins, which are used in red, green and blue channels. They can accommodate signals from 0.5 V to 1.0 V p-P. , 15 -needle D connectors or RCA connectors to the interface board. AD9984A should be as close to the input connector as possible. The matching impedance trajectory (usually 75Ω) should be used to enter the signal route to the IC input pin.

At the input pin, the signal should be connected (75Ω to the signal grounding circuit), and the capacitance of 47 NF capacitors is coupled to the AD9984A input. In the ideal world of the ideal, the width signal bandwidth can get the best performance. The broadband input of AD9984A (300 MHz) can continuously track the signal when entering the signal from a pixel -level to the next pixel -level, and can grow long and long and long and long and long and long and long and long and long and long and long and long and long and long and long and long, they can grow long and long and long and long and long and long and long and long and long and long and long and long and long and long and long, they can grow long and long and long and long and long and long and long and long and long and long and long and long and long and long and long and long and long and long and long and long, they can grow long and long and long and long and long and long and long and long and long and long and long and long and long and long and long and long and long and long and long, they can grow long and long and long and long and long and long and long and long and long and longer The pixels are digitized in a flat pixel time. However, in many systems, there is no matching, reflection, and noise, which may cause excessive bells and distortion of the input waveform. More difficult. The small inductors that are connected in the input series are proved to be slightly reduced in the wide condition range and it is effective. In the circuit shown in FIG. 4 (For example, Fair Rite 2508051217z0) provides good results in most applications.

C and vsync input

The interface also accepts Hsync and Vsync signals, which are used to generate pixel clocks, clamp timing, and coast and field information. These signals can be a synchronous signal directly from the graphic source, or it can be a pre -processed TTL or CMOS -level signal.

Hsync input includes a Schmitt trigger buffer for anti -noise and long -up time signals. In a typical PC -based graphics system, synchronous signals are just TTL -level drivers, and non -shielding wires are fed into the display cable. Therefore, no need to terminate.

Serial control port

The serial control port is designed for 3.3V logic; however, it can tolerate 5V logical signals. For more information, see the 2 -line serial control port part.

Output signal processing

Digital output works between 1.8 v and 3.3 v (v).

Clamp

RGB clamping

In order to correctly digitize input signals, the input DC offset must be adjusted to adapt to the range of the car ADC.

The RGB signal generated by most graphics systems is black on the ground and white is about 0.75 volts. However, if the synchronous signal is embedded in the graph, the synchronization prompts are usually on the ground. Black is 300 millivoli and white is about 1.0V. Some common RGB line amplifiers boxes use transmitters to follow the buffer to divide signals and improve their drive capabilities. This will introduce a DC offset of 700 MV to the signal, and the AD9984A must remove the offset in order to correctly capture it.

The key to clamping is a part of the identification signal (time) when a known graphic system is generated. Then introduce offset, when there is a known black input, the offset causes ADC to produce black output (code 0x00). Then, when other signals are processed, the offset is maintained in situ, and the entire signal is shifted to eliminate the offset error.

In most PC graphics systems, black is transmitted between the video cable between the event. When using a CRT display, when the electron beam is written on the screen (on the right), the horizontal line is written, and the electron beam quickly turns to the left side of the screen (called the horizontal return), and a black signal is provided to prevent the electronic beam interference image.

In a system that has an embedded synchronization, a signal that is darker than black signals than black signals (Hsync) will be briefly realized to send a signal to the CRT. Because the input is not at the black level at this time, it is important to avoid clamping during Hsync. Fortunately, Hsync (known as the Corridor) usually provides a good black reference for a while. This is the time to clamp.

You can simply execute clamps by using clamp source (register 0x18, bit 4) 1Create clamping timing. The polarity of the signal is set by a clamp polar bit (register 0x1b, bit [7: 6]).

A simpler time -clamping timer method uses the AD9984A internal clamping timer. Compraward placing register (register 0x19) is programmed by pixels that should be passed after the back edge of Hsync before the start of the compromation. The second register Clamp Duration (register 0x1A) sets the duration of clamping. Both are 8 -bit values, providing considerable flexibility in clamping generation. Although HSYNC can change greatly, clamping time is the reference of Hsync's back edge, because the corridor (black reference) always follows Hsync. The effective starting point for building clamping is to set the clamp to 0x04 (providing 4 pixels to make the graphics signal stable after synchronization), and set the duration duration to 0x28 (provided 40 pixels to re -establish black reference) reference) Essence

Clamping is completed by placing appropriate charge on the external input coupling container. The value of this capacitor will affect the performance of the clamper. If it is too small, there is significant changes in amplitude in the horizontal line time (between clamping intervals). If the capacitor is too large, the clamping device needs to be recovered for a long time from the large changes in the input signal offset. The recommended value (100 NF) causes the 85 Hz XGA signal from the step error of 100 MV to within 60 lines of 1 LSB, and the duration of the duration is 20 pixel cycles.

YPBPR clamping

YPBPR graphics signal is slightly different from the RGB signal, because the DC reference level of the color difference signal (the black level in the RGB signal) is located at the midpoint of the video signal, and the Not the bottom. These three inputs are composed of brightness (y) and color difference (PB and PR) signals. For the color difference signal, the medium range range of the ADC range (512) needs to be cut instead of the bottom of the ADC range (0), and the Y channel is stabbed to the ground.

By setting a clamp selection bit in the serial bus register, the clamping can be locked to the medium scale instead of ground. Each of the three converters has its own choice, so that they can independently fix them on medium or ground. These are located in the register 0x18 [3: 1]. The medium standard reference voltage is generated by each converter.

gain and offset control

AD9984A contains three programmable gain amplifiers (PGA), one each of the three simulation inputs. The range of PGA is sufficient to accommodate the input signal, and its input range is 0.5V to 1.0V. The gain is set in three 9 -bit registers: red gain (register 0x05, register 0x06), green gain (register 0x07, register 0x08) and blue gain (register 0x09, register 0x0A). For each register, 0D gainThe setting corresponds to the highest gain, and the 511D gain setting corresponds to the minimum gain. Please note that increasing gain settings will lead to a decrease in the contrast of the image.

The offset control of the mobile analog input, resulting in changes in brightness. Three 11 -bit registers, red offsets (registers 0x0B, register 0x0c), green offset (register 0x0D, register 0x0e), and blue offset (register 0x0F, register 0x10) are provided independent settings for each channel. Note that the function of the offset register depends on whether to enable automatic offset (register 0x1B, bit 5).

If you use a manual offset, the nine digits of the offset register (for the red channel, the register 0x0B, the bit [6: 0] plus the register 0x0c, the bit [7: 6]) control the absolute addition to the number of the channel to the channel Offset. The offset control provides a adjustment range of ± 255 LSB, and the offset of 1 LSB corresponds to the output code of 1 LSB.

Automatic offset

In addition to the manual offset adjustment mode, AD9984A also includes automatic calibration of each channel offset circuit. By monitoring the output of each ADC during the corridor of the input signal, AD9984A can self -adjust to eliminate any offset error in its own ADC channel and any offset error in the graphic or video signal.

To activate the automatic offset mode, set the position of the register 0x1b to 1. Next, the target code register (register 0x0b to the register 0x10) must be programmed. The value of programming to the target code register should be the output code required for AD9984A during the reference of the corridor.

For example, for the RGB signal, all three registers are usually programmed as code 2, and for the Y PB PR signal, the green (Y) channel is usually programmed as code 2, blue and red channels (PB and PR) Usually set to 512. The target code register has 11 digits per channel, and it is two supplementary formats. This allows any values between -1024 and +1023. Although any value within this range can be programmed, the offset range of AD9984A may not reach each value. The expected target code range is (but not limited to) the ground clamping is -160 to -1 and +1 to +160 when the ground clamping is 350 to 670 when the medium scale clamping is 350 to 670. Please note that the target code 0 is invalid.

Contains negative target codes to copy the functions existing in manual offset adjustment. The advantage of simulation is that it can easily adjust the brightness on the display. By setting the target code to the value that is not corresponding to the ideal ADC range, the final result is the image brighter or darker. The target code higher than the ideal value will produce brighter images, and the target code lower than the ideal value will produce a darker image.

The ability of programming target code provides a lot of freedom and flexibility. Although in most cases, all channels are set to 1 or 512, but the flexibility of choosing other values makes it possible to insert intentionally tilt between channels. It also allows the ADC to tilt so that the voltage outside the normal range can be used. For example, setting the target code to 40 allows digitalization and assessment of synchronous prompts usually lower than black levels.

The internal logic of the automatic offset circuit requires 16 data clock cycles to perform its functions. This operation is executed immediately after clamping the pulse. Therefore, it is important to end at least 16 data clock cycles before activating the video. This is the case whether the AD9984A internal clamp circuit or an external clamp signal is used. The automatic offset function can be programmable to run continuously or one -time operation (see 0x2C bit [4] automatic offset maintenance). In the continuous mode, the update frequency can be programmed (register 0x1b, bit [4: 3]). It is recommended to update every 192 HSYNCS.

Basic automatic offset operation guidelines are shown in Table 6 and Table 7.

Automatic gain matching

AD9984A includes matching the gain between the three channels to the circuit within 1%of each other. The gain of each channel is necessary to achieve good color balance on the display. In products without this function, the gain matching is achieved by writing software. The software evaluates the output of each channel. The calculation of the gain does not match, and then write the value of the value of each channel to compensate. With automatic gain matching function, this software routine is no longer needed. To activate the automatic gain match, set the position of the register 0x3C [2: 0] to 110.

Automatic gain matching and automatic offset have similar time order requirements. It requires 16 data clock cycles to execute its function, and start immediately after the pulse is over. Different from automatic offset, the 16 clock cycle of automatic gain matching does not require these 16 clock cycles to occur within the reference of the corridor, although it is recommended to do so. During the automatic gain matching operation, the data output of AD9984A is frozen (remained at the value before operation). The automatic gain matching function can be programmable to run continuously or one -time operation (see 0x3C bit [3] automatic gain matching part). In the continuous mode, the update frequency can be programmed (register 0x1b, bit [4: 3]). It is recommended to update every 192 HSYNCS.

Green synchronization

Synchronous (Sogin0, Sogin1) on the green input operation in two steps. First, they use a negative peak detector to set a baseline to cut the level. Secondly, they set the voltage level of the SOG slicer (register 0x1d, bit [7: 3]) to the programmable level (usually 128 MV) above the negative peak value. Each Sync Word input must be coupled with the green analog input through its own capacitor. The value of the capacitor must be 1 nf± 20%. If you do not use green synchronization, you do not need this connection. Green synchronization signals are always negative.

Reference bypass

Reflo and Refhi are connected to each other through 10 μF capacitors (see Figure 6). Enter the ADC circuit to use these references.

The clock produces

PLL is used to produce pixel clocks. Hsync input provides reference frequency for PLL. Pressure -controlled oscillator (VCO) generates higher pixel clock frequency. Pixel clock is compared with Hsync input with the PLL removal value (register 0x01 and register 0x02). Any error is used to transfer the VCO frequency and maintain the lock between the two signals.

The stability of this clock is a very important factor that provides the clearest and stable image. In each pixel time, the signal is converted from the old pixel amplitude and fixed to its new value; this is called the conversion time. The input voltage must be stable before the signal must be converted to the new value; this is called a stable time. The ratio of the rotation time to the stable time is a function of graphical DAC bandwidth and transmission system bandwidth (cable and terminal). This ratio is also a function of the overall pixel rate. If the dynamic characteristics of the system remain unchanged, the rotation and stability time are also fixed. This time must be reduced from the total pixel cycle to retain the stable cycle. At the higher pixel frequency, the total loop time is shorter and the stable pixel time is shorter.

Any jitter in the clock will reduce the accuracy of the sampling time, and it must be subtracted from the stable pixel time. In the design of the AD9984A clock, in order to minimize the jitter, quite cautious measures have been taken. In all working mode, the clock jitter of the AD9984A is very low, so that the effective sampling time caused by shake can be ignored.

The loop of the loop is determined by the design of the loop filter, the charging loop of the loop of the loop, and the VCO range settings. The design of the ring filter is shown in Figure 8. Table 10 lists the recommended settings of the VESA standard display mode and the charge pump current.

Provide four programmable registers to optimize the performance of PLL. These registers are 12 -bit removal registers, 2 -bit VCO range registers, 3 -bit charge pump current registers, and 5 -bit phase adjustment registers.

12 -bit removal register

As long as the multiplication of Hsync and PLL divisoring is within the working range of VCO, the input Hsync frequency can accommodate any Hsync. PLL multiplys the frequency of the HSYNC signal to generate a pixel clock frequency from 10MHz to 170MHz. Divide the register to control the accurate multiplication factor. As long as the output frequency is in Fan FanInside, the register can be set at any value between 2 and 4095.

2 -bit VCO range register

In order to improve the noise performance of AD9984A, the operating frequency range of VCO is divided into four overlap areas. The VCO range register sets this working range. The frequency range of the four areas is shown in Table 8.

Three -bit charge pump current registers

This register change the current of the driver's low -pass circuit filter. Table 9 lists possible current values.

5 -bit phase adjustment registers

The phase of the sampling clock generated by generated can be shifted at the best sampling point in the clock cycle. The phase adjustment register provides 32 migration steps, each step 11.25 °. HSYNC signals with the same phase shift can be obtained through the HSOUT pin. If the external pixel clock is used, phase adjustment is still available. COAST PIN or internal coast is used to allow PLL to continue running at the same frequency during the same frequency without entering the Hsync signal or in Hsync (eg from the equilibrium pulse). This can be used during vertical synchronization or at any other time for Hsync signals.

The polarity of the coastal signal can be set through the coast polar register (register 0x18, bit [6: 5]). In addition, the polarity of the HSYNC signal can be set through the Hsync polar register (register 0x12, bit [5: 4]). For Hsync and Coast, the value 1 is a high activation state. The internal taxi function is driven by VSYNC signal. This signal is usually the time when the Hsync signal can be interfered by additional balanced pulses.

Synchronous processing

The Sync processing part of AD9984A input is digital Hsyncs and vsyncs, simulated Sync ONGREEN or Sync-On-Y signals, optional available available Combination of external coast signal. From these signals, the components generate accurate shake clocks, puppet field signals, HSOUT and VSOUT signals, each vsync Hsync count and programmable sogout from its locking loop. The main synchronous processing blocks are synchronous slicers, synchronous separators, HSYNC filters, Hsync regenerations, VSYNC filters and coast generators.

Synchronous slicer extract synchronous signals from the green graphic or bright video signal connected to Soginx input, and output digital compound synchronization.

Synchronous separator extract vsync from the composite synchronization signal. This signal can come from the synchronous slice or Hsyncx input.

hThe Sync filter is used to eliminate any non -non -non -non -turbid pulse in Hsyncx or SOGINX input, output is suitable for mode detection and clocks to be cleaned and low -jitter signal.

Hsync regenerator is used to re -create a clean HSYNC signal. Although it is not a low jitter, it can be used for mode detection and calculation of Hsync of each VSync.

vsync filter is used to eliminate bruises vsync, maintain a stable timing relationship between Vsync and HSYNC output signals, and produce a puppet field output.

Coastal generator generates a stable coastal signal, allowing the ring -locking ring to maintain its frequency without HSYNC pulse.

Synchronous slicer

The purpose of synchronous slicer is to extract synchronous signals from the green graphics or brightness video signal connected to the SOG input. The synchronization signal is extracted in two steps. First, the SOG input is restrained to its negative peak (usually 0.3V lower than the black electricity flat). Next, the signal enters a comparator with a variable anemine level (set by register 0x1d, bit [7: 3]), but it is nominally higher than the clamp level 0.128 V. Synchronous slice output is a digital compound synchronization signal containing Hsync and vsync information (see Figure 10).

Synchronous separator

As a part of synchronous processing, the task of synchronous separator is to extract vsync from a composite synchronization signal. Its working principle is that the VSYNC signal is much longer than the Hsync signal keeping activity. By using digital low -pass filters and digital comparators, synchronous separators refuse the pulse (such as Hsync and equilibrium pulse) with a short duration (such as Hsync and equilibrium pulse), and only vsync (see Figure 10) with a longer duration (see Figure 10).

The threshold of the digital comparator can be programmed to obtain the maximum flexibility. To program the threshold duration, write the value (n) to the register 0x11. The obtained pulse width is n × 200ns. For example, if n 5, the number comparator threshold is 1 μs. Any pulse less than 1 μs is rejected, and any pulse greater than 1 μs passes.

Remember two factors when using synchronous separators. First, the obtained clean VSYNC output from the original vsync delay equal to the duration of the number comparator threshold (N × 200NS). Secondly, there are certain variability in the 200NS double value. The maximum variability under all operation conditions is ± 20%(160 ns to 240 ns). Because normal vsync and HSYNC pulse width differences are about 500 times or more, 20%of mutation is not a problem.

Synchronous filter and regeneration

Hsync filter is used to eliminate HsyncOr any non -turbine input in the SOG input, the output is suitable for mode detection and the clean and low jitter signal generated by clocks. Hsync regeneration is used to re -create a clean but not low -jitter HSYNC signal. This signal can be used to detect and calculate the Hsync of each Vsync. Hsync regeneration has a high degree of tolerance for the irrelevant pulses and lost pulses on Hsync input, but it is not suitable for PLL to create a pixel clock due to jitter.

Hsync regeneration is running automatically, and it can be run without setting. Hsync screenter needs to set the screenwriter window. The filter window sets a cycle time window surrounding the front edge of Hsync in an effective Hsync. The general idea is that the unrelated pulse on the synchronous input occurs outside the filter window, so it is filtered out. To set the filter window timing, program the value (x) into the register 0x23. The filter window time is 25 ns around the ± x of the front edge of the regeneration Hsync. Like the synchronous separator threshold multiplier, there is a difference in the existence of a 25 NS multiples to show that all operating conditions (20 ns to 30 ns range).

The second output of the Hsync filter is a state bit (register 0x25, bit 1), and it indicates whether there is no turbine on the input synchronization signal. External pulse is usually used to replicate protection purposes, so this status can be used to detect such pulses.

Filter Hsync (instead of the original Hsyncx/SOGINX signal) of the PLL -generated pixel clock is controlled by the second place of the register 0x20. The regeneration Hsync (instead of the original Hsyncx/soginx signal) is controlled by the synchronous processing processing by the register 0x20. It is recommended to use the filtered Hsync and the re -generated Hsync. For descriptions of the filtering Hsync, see Figure 11.

vsync filter and the puppet domain

vsync filter to eliminate bruises vsync, keep the time order between Vsync and Hsync output signals Relationship, and produce a puppet field output.

The working principle of the filter is to check the position of Vsync relative to Hsync. If necessary, move it slightly in time. The purpose is to prevent Vsync and Hsync cutting the front edge at the same time, thereby eliminating the confusion of when the first line of the frame is eliminated. The register 0x14 is enabled by the bit 2. It is recommended to use the vsync filter in all cases (including interval scanning video), and the filter needs to be used when using Hsync, which uses each VSync counter. Figure 12 and 13 show that the puppet field is determined in the two cases.

Power Management

For the sakeDisplay requirements for low -standing power requirements AD9984A include power -off mode. The power -off state can be manually controlled (by pin 17 or register 0x1e, bit 3), or it can be automatically controlled by the chip. If the automatic control (register 0x1e, bit 4 1) is selected, the determination of AD9984A The status of synchronous detection bits based on the register 0x24: bit 2, bit 3, bit 6 and 7. If Hsync or Sync on Green input is detected on any input, the chip will be powered on; otherwise, it will be powered off. For manual control, AD9984A allows flexible control through special pins and register positions. For the special pipe foot, the hardware watch the door dog circuit to control the power failure, and the software controls the power of the storage position. When using manual power break control, whether or not the pin is used, the polarity of the power -off pin must be set (register 0x1e, bit 2). If it is not used, it is recommended to set the polarity to high activity, and use a 10 kΩ resistor to ground the pin hard line.

In the power -off mode, several circuits continue to work normally. The serial register and synchronous detection circuit keep the power supply so that AD9984A can wake up from the power off state. The band -in circuit keeps the power, because synchronous detection requires it. Green synchronization and SOGOUT function continue to work, because when synchronous detection is performed by auxiliary chips, SOGOUT is required. All these circuits require the minimum power to work. The typical standby power of AD9984A is about 50 MW.

There are two options to choose from during power off. These are controlled by bit 0 and position 1 in the register 0x1e. Bit 0 controls whether the sogout foot is in high impedance. In most cases, users do not place exudate during normal operation during high impedance. The options for putting water seepage in high impedance mainly include allowing factories to test mode. Bit 1 keeps power on AD9984A, and at the same time, only the output is placed in high impedance. This option is very useful when the data output of the two chips is connected to a PCB and the user wants to switch between the two chips immediately.

The sequential figure

Figure 14 to the timing chart in Figure 17 shows the working situation of AD9984A. When creating the output data clock signal, its rising edge always occurs between data conversion, which can be used for external lock output data. There is a pipeline in AD9984A that must be refreshed first before getting effective data. This means that there are six data sets before effective data.