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2022-09-21 17:24:28
ADRF6755 is 100 MHz to 2400 MHz I/Q modulator.
Features
Integrated I/Q modulator of an integrated segmentation of the ring lock ring and the voltage control oscillator; Output 1DB compression: 8dbm, LO 1800MHz; output IP3: 20.5 dBM, LO 1800 MHz; noise limit: LO 1800 MHz is -161 dbm/hz; baseband modulation bandwidth: 600 Mix (3 decibels); Rate: 1Hz; SPI and I2C compatible serial interface power supply: 5V/380mA.
General description
ADRF6755 is a highly integrated orthogonal regulator, frequency synthesizer, and programmable attenuator. The operating frequency range of the device is from 100 MM to 2400 MMC, which can be used for satellite, honeycomb and broadband communication.
The ADRF6755 modulator includes a high -mode score n -frequency synthetic synthetic (frequency resolution less than 1Hz) and a 47DB digital control output attenuation with 1DB step.
The control of the registers on all films is achieved through the SPI interface or IC interface selected by the user. The device runs from 4.75 to 5.25 volts.
I2C interface timing characteristics
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Typical performance features
VCC 5 V ± 5%, operating temperature range -40 ° C to+85 ° C, I/Q input 0.9 v p-p Different sine wave, in the sine wave, in the 500 MV DC bias, Refin 80 MHz, PFD 40 MHz, baseband frequency 1 mHz, lomon turn off, ring bandwidth (LBW) 100 kHz, inductive coupling coefficient 5 mAh, unless there is another explanation. The nominal conditions are defined as a low frequency of 25 ° C, 5.00 V and 1800 MHz. The worst case is defined as temperature, power supply voltage and LO frequency with the worst situation.
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Operation theory 
Overview 
ADRF6755 device can be divided into the following basic construction blocks: 
123] 
orthogonal transit device
Attenuator
voltage regulator
IC/ SPI interface 2
The following sections will be introduced in detail these built -in base blocks.
Lock phase ring synthesizer and VCO
Overview
Lock phase loop (PLL) consisting of 25 -bit fixed mold n -frequency synthesizer The frequency resolution within the range is less than 1Hz. It also has an integrated voltage control oscillator (VCO), which has a basic output frequency from 2310 MM to 4800 MM. The RF division controlled by the register CR28 Bit [2: 0] expands the lower limit of the local oscillator (LO) frequency range to 100 MHz. For more detailed information about the register CR28, see Table 6.
Refer to the input part
Reference input level is shown in Figure 52. SW1 and SW2 are normally closed switches. SW3 often opens. When starting power off, SW3 is turned off, and SW1 and SW2 are turned on. This ensures that Refin sales will not be loaded during power off.
Reference Input path
Reference multiplier on the film allows the input of reference signal multiplier. This increases the frequency of PFD. Increasing PFD frequency can improve the noise performance of the system. Double PFD frequency can usually increase the inner phase noise performance up to 3DBC/Hz.
5 -bit R frequency frequency device allows the input reference frequency (REF) to divide down to generate the reference clock that generates to PFD. Allow a division ratio from 1 to 32.
Refer to the additional division in the input path with 2 (÷ 2) function to allow a larger range of division.
PFD frequency equation is:
Among them: Frefin is the reference input frequency. D is double position. R is a binary programming division of the programming reference pressure division (1 to 32). T is the set position of the R/2 division (CR10 [6] 0 or 1).
If there is no need to remove the method, it is recommended to use 5 bits to disable R removing instruments and 2. If you need to divide the method, you can use the CR5 [4] 1 and CR10 [6] 1 to enable the division to be divided by 2, and the rest of the division removal in the 5 -bit R remoer. If you need a strange number division method, set CR5 [4] 1 and realize all removal in 5 digits of R in 5 digitsLaw.
RF divider
RF score N splitter allows the frequency frequency ratio in the PLL feedback path between 23 and 4095. The relationship between the score n divisor and the LO frequency is described in the INT and FRAC relationship part.
Internal and fractal relationships 
The low -frequency equation is:
In the formula: LO is the vibration frequency. FPFD is the PFD frequency.
INT is an integer component of the required division factors, controlled by the CR6 and CR7 registers.
FRAC is a decimal part of the required factors, controlled from CR0 to CR3 register.
RFDIV is set in the register CR28 digits [2: 0], and controls the setting of the instrument from the output end of the PLL.
The frequency detector (PFD) and the charge pump
PFD receiver from the input from the R -binter and the N counter, and generate it with them The output of the phase difference and the frequency difference is proportional (the simplified schematic diagram is shown in Figure 55). PFD includes a fixed latency element for setting the width of the reverse gap pulse to ensure that there is no dead area in the PFD transmission function.
Lock detection (LDET)
When the PLL locks to an error frequency of less than 100Hz, the LDET (pin 44) emits signals. When writing the register CR0, the new PLL collection cycle starts, and the LDET signal becomes lower. When the lock is completed, the signal returns to a high position.
Pressure -controlled oscillator
The VCO core in ADRF6755 consists of three independent VCOs. Each VCO has 16 overlapping frequency bands. This 48 -frequency configuration allows the frequency range of VCO to expand from 2310 MM to 4,800 MM. Three VCOs are divided by a programmable removal RFDIV and controlled by the register CR28, bit [2: 0]. The frequency frequency device provides a frequency frequency of 1, 2, 4, 8, and 16 to ensure that the frequency range is expanded from 144.375 MM (2310 Mixh/16) to 4,800 MI (4800 Mix/1). Then, the orthogonal circuit in the modulator path provides a full LO frequency range from 100 Might to 2400 MM.
FIG. 56 shows the scanning of V and LO frequency, showing the overlap in the range of three VCOs from 100MHz to 2400MHz and multiple overlapping bands in each VCO. Note, Figure 56 includes mergedRFDIV provides further division of the basic VCO frequency; therefore, each VCO is used in multiple different occasions of the entire LO frequency range. Choose three 16 -band VCOs and a radio frequency divider, which can cover a wide range of frequency range without producing a large VCO sensitivity (K) or the low -phase noise and blooming performance generated by it. 
VCO shows the change of KVCO because VTUNE changes within the band and between bands. Figure 57 shows the change of KVCO throughout the frequency range. When using AdisIMPL to calculate the loop filter bandwidth and a single ring circuit filter component, Figure 57 is very useful #8482; ADISIMPL is an analog device company. Design of ring filter. It reports parameters of specific input conditions, such as phase noise, integrated phase noise and collection time.
Automatic calibration
When the register CR0 is updated, the VCO and band selection circuit will automatically select the correct VCO and band. This is called automatic calibration. The automatic school is set up by the register CR25.
Among them: BSCDIV register CR25, bit [7: 0] .pfd PFD frequency.
For the PFD frequency of 40 MHz, the BSCDIV is set to 100 to set the automatic schoolkit time to 70 microseconds.
Note that if the frequency of PFD changes, BSCDIV must be re -calculated. The recommended automatic calibration is set to 70 microseconds. During this period, the output of VCO VTune and the ring filter was disconnected and connected to the internal reference voltage. The typical frequency collection is shown in Figure 58.
After the automatic calibration, the normal lock -locking ring movement is restored, and usually obtains the correct frequency within the range of 100 Hz frequency errors within 170 μs. For the maximum cumulative level jump to 100 kHz/2RFDIV, the automatic calibration can be turned off by setting the register CR24 and the bit 0 1. This enables the cumulative frequency of less than 100 kHz without automatic calibration procedures (for RFDIV ÷ 1, for RFDIV ÷ 2, 50 kHz, push according to this), which significantly improves the collection time (see Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 59).
Set the correct low frequency
There are two steps to program the correct low frequency. The user must calculate the RFDIV value based on the required LO frequency and PFD frequency and the N -divided frequency ratio required in PLL.
1. Calculate the value of the RFDIV, which is used to the register CR28, bit [2: 0] from the registers in Table 6 belowProgramming with CR27 and Bit 4.
2. Use the following formula, calculate the value of n [[:
where: n is n-removing method The device value.
RFDIV is the settings in the register CR28, bit [2: 0].
LO is the frequency of this vibration. 
This equation is another representation of equation 2.
Examples of the correct and low frequency of programming
Assume that the PFD frequency is 40MHz, and the required LO frequency is 1875MHz.
From Table 6, 2RFDIV 1 (RFDIV 0)
N-removing the value of the orthodigo consisting of an integer (int) and a fraction (FRAC) (FRAC) According to the following equal form:
int 46, frame 29360128
and then programming the corresponding register according to the register mapping. The programming order of the register is very important. Write the CR0 startup PLL collection cycle. If the program of programming needs to change the value of the CR27 [4] (see Table 6), CR27 should be the last programming register, which adds CR0 to the front. If the program of programming does not need to change the value of CR27 [4], you can omit the writing of CR27. In this case, CR0 should be the last programming register.
orthogonal transfer device
Overview
The basic box diagram of the ADRF6755 orthogonal adjustment device circuit is shown in Figure 60. The VCO/RF frequency division generates a signal at a 2 × LO frequency, and then divides the signal down to give the signal at the LO frequency. The signal is then divided into the same phase component and orthogonal component to provide the LO signal of the drive mixer.
I and Q baseband input signals are converted from V-TO-I level to current, and then drive two mixers. The output of these mixers is merged into a single -end output. The single -end output was then fed to the attenuator, and finally it was fed to the external RFOUT signal tube foot.
The baseband input
baseband input, QBB, QBB, IBB, and IBB must be driven from the differential source. The nominal driving level of 0.9 V p-P differential (450 mv P-P) should be biased towards a co-mode level of 500 MV DC. To set the DC bias level at the baseband input terminal, see Figure 61.
The average output current of each AD9779 output is 10 mAh. At each baseband input terminal, the 10 mum current current flowing per 50 ω resistance to the need to generate the need to generate500 millivoltter DC bias.
Differential baseband input (QBB, QBB, IBB, and IBB) consisting of the base of the PNP transistor. The high impedance of the PNP transistor is about 30kΩ, and the linkage is 2PF. The impedance is about 30 kΩ below 1 MM, and at a higher frequency start attenuation. It is recommended to use a 100Ω differential terminal at the baseband input terminal. If the input baseband signal is shown, this will control the input impedance. This ensures that the input impedance seen by the input circuit keeps flat on the base band width. Typical configuration is shown in Figure 62.
The swing range of the output current AD9779 from 0 mAh to 20 mAh. The AC voltage swing is 1 V p-p single-end or 2 V p-p differential, and the 50Ω resistor is installed in place. The 100Ω differential terminal connection resistor at the baseband input end has the effect of limiting this swing without changing the 500 MV DC bias conditions. Low -pass filter is used to filter the DAC output and remove the image when the driver is driven.
Another consideration is that the baseband input actually generates 240μA current from each of the four inputs. When setting a DC bias of 500 MV, the current must be considered. In the initial example of FIG. 61, the 12 MV error occurred due to the 240 μA current flowing through the 50Ω resistor. The accuracy of DC bias should be 500 mv ± 25 mv. It is also important that this 240μA current has a DC grounding channel.
Optimization
By using the following optimization technologies, the carrier feeding and border suppression performance of ADRF6755 can improve the specifications in Table 1.
The carrier feeding zero position
The carrier feeder is caused by the DC offset occurred between the P and N inputs input between the differential base bands. Usually, these inputs are set to DC bias about 500 MV. However, if the DC offset is introduced between p and n input between one or two I and Q inputs, the carrier feed will be affected in a positive or negative manner. Note that DC bias levels are kept at 500 MV (average P and N levels). When the offset of the Q channel changes, the offset of the I channel usually remains unchanged until the minimum carrier feed level is obtained. Then, while keeping the new Q channel offset, adjust the i -channel offset until it reaches the new minimum value. This is usually executed at a single frequency, so it is not optimized throughout the frequency range. Multiple optimizations must be performed at different frequencies to ensure the best carrier feed through the entire frequency range. 
Edge suppression of relative gain and relative phase offset between the i channel and the Q channel can be optimized by adjusting these two parameters. Only adjusting one parameter will only increase the band inhibitory to one point. In order to obtain the best band suppression, it is necessary toIt iterative adjustment between the position and the amplitude.
Attenuator
The digital attenuation device consists of 6 attenuated blocks: 1DB, 2DB, 4DB, 8DB, and 2 16DB blocks, and each block is controlled separately. Each attenuation block is composed of the field -effect transistor (FET) switch and the resistor, which forms a PI or T -shaped quizer. The state of the FET switch is controlled by the control line, each attenuation block can be set to pass the state (0DB) or attenuation status (1DB to 47DB). Various combinations of six blocks provide attenuation from 0DB to 47DB with an increment of 1DB.
voltage regulator
The voltage regulator is powered by 5 V power supply provided by VCC1 (pin 11), and the rated regulatory output voltage regough is generated on the pin 12. The pin must be connected by the Vreg6 packaging pin (outside the integrated circuit) to Vreg1.
Use parallel combinations of 10 PF and 220 μF capacitors to separate the regulator output (regout). The 220 μF capacitor recommended to obtain the best performance can separate broadband noise, thereby generating better phase noise. Each VregX foot should have the following decoupled capacitor: 100 NF multi -layer ceramics, and the other 10 PF is connected in parallel, and both are as close as possible to the detected device (DUT) power pipe foot. It is recommended to use X7R or X5R capacitors. For more information, please refer to the evaluation committee.
Integrated circuit interface
ADRF6755 supports 2 -line IC compatible serial bus, which can drive multiple peripheral devices. Serial data (SDA) and serial clock (SCL) input information between any device connected to the bus. Each device is recognized by a unique address. ADRF6755 has two seven -digit portal address for reading and writing operations. The 7 -bit MSB of the machine address is set to 1. The bit A5 from the machine address is pins (pin 27). Set from the position of the address [4: 0] to all 0. From the address of 7 MSB of 8 -bit words. The LSB setting of the word reads or writes (see Figure 63). Logic 1 corresponds to reading operations, and logic 0 corresponds to writing operations.
To control the equipment on the bus, the following protocol must be followed. The host starts the data transmission by establishing a startup condition. This condition is defined from high to low on the SDA, while SCL remains high. This means that the address/data stream is subsequently. All peripheral equipment response to the startup condition and move the next 8 -bit (7 -bit address and R/W bit). The position is transmitted from MSB to LSB. The peripheral peripheral of the identification address responded by lowering the data cable during the ninth clock pulse. This is called confirmation. All other devices then exit the bus and keep it idle. In the idle state, device monitor the SDA and SCL lines, waiting for the starting state and the correct transmission address. R/W bits determine the direction of the data. Logic on the first byte LSB 0It means the host writes information to the peripheral. Logic 1 on the first byte LSB represents the host read information from the peripheral.
ADRF6755 is used as a standard on the bus. The data on the SDA pin (pin 29) is 8 bits, supporting 7 -bit addresses plus R/W bit. ADRF6755 has 34 sub -addresses, allowing users to access internal registers. Therefore, it interprets the first byte as the device address and the second byte is interpreted as the starter address. Support automatic incremental mode, allows reading or writing data from the beginning of the child and each subsequent address without manual addressing the subsequent sub -address. Data transmission is always terminated by stopping conditions. Users can also access any unique sub -address register one by one without updating all registers.
Conditions can be detected at any stage of data transmission. If these conditions are inconsistent with the normal reading and writing operations, they will immediately jump to idle conditions. If the user emits an invalid subset, the ADRF6755 will not send a confirmation and return to the idle state. In the case of no response, the SDA line did not lower on the ninth pulse. Please refer to the example writing and reading data transmission in Figure 64 and FIG. 65, the timing protocol in FIG. 66, and the more detailed timing diagram in Figure 2.
SPI interface
ADRF6755 also supports the SPI protocol. Components are powered on in IC mode, but it is not locked in this mode. In order to maintain the IC mode, it is recommended that users connect the CS cable to 3.3V or GND to disable the SPI mode. Unable to lock the IC mode, but you can choose and lock the SPI mode.
To select and lock the SPI mode, three pulses must be sent to the CS pin, as shown in Figure 67. When the SPI protocol is locked, it cannot be unlocked when the device is still in power. If you want to reset the serial interface, the power of the part must be turned off, and then the power is powered again.
Select the serial interface
CS pin control IC or SPI interface selection. Figure 67 shows the selection process required to lock the SPI mode. To use the SPI protocol to communicate with parts, three pulses must be sent to CS PIN. At the third ascending edge, this part selects and locks the SPI protocol. Consistent with most SPI standards. During all SPI communication with the components, the CS tube foot must be kept low and kept high at other times.
SPI serial interface function 
FIG. 68 shows an example of the operation of ADRF6755. The data is recorded in the register of the CLK rising edge through a 24 -bit writing command. The first 8 digits indicate the writing command 0xd4; the latter 8 digits represent the register address; the last 8 digits indicate the data of a specific register. Figure 69 shows an example of reading operation. In this example, the shortened 16 -bit writing command is first used to select the appropriate register used to read the operation. The first 8 digits represent the writing command 0xd4, and the last 8 digits represent a specific register. Then, the second pulse of the CS line is low, using the 16 -bit read command to retrieve the data from the selected register. The first 8 digits indicate the reading command 0xd5, and the last 8 digits represent the content of the reader. Figure 3 shows the timing of SPI reading and SPI writing operations.
Program mode
ADRF6755 has 34 8 -bit registers, allowing program control to control many functions. You can use the SPI or IC interface to program the register set. For detailed information about the interface and timing, see Figure 63 to Figure 69. The register is recorded in Table 8 to 28.
Some settings in ADRF6755 are dual buffer. These settings include FRAC value, INT value, 5 -digit R frequency frequency value, reference multiplier, R/2 -point frequency, RFDIV value and charge pump current settings. This means that two events must be occurred before the component is set for any dual buffer settings. First, the new value is locked into the device by writing an appropriate register. Next, new writing operations must be performed on the register CR0. when? The register CR0 is written, and the new PLL collection occurs.
For example, the update score value needs to be written into the register CR3, register CR2, register CR1, and register CR0. The register CR3 should be written first, then the register CR2 and register CR1 should be written, and the register CR0 is finally written. The new collection starts after writing the register CR0. The dual buffer ensures that the writing position takes effect after writing the register CR0.
12 -bit integer values 
The register CR7 and register CR6 of the feedback factors (N) programming (N) is programmed; please refer to the equations 5 for details. The int value is a 12 -digit number, and its MSB is programmed by the register CR7 digit [3: 0]. LSB programmed by register CR6, bit [7: 0]. Low -frequency settings are described by equation 2. Equation 4 provides an alternative of this formal formula, which details how to set N-removing value in detail. Note that these registers are dual -buffer. 
The register CR3 uses the register CR0 programming feedback to remove the score value (FRAC); please refer to Formula 5. The FRAC value is a 25 -digit number, and its MSB is programmed by the register CR3. LSB is programmed by register CR0, bit 0. Low -frequency settings are based on equation 2. Formula 4 describes another choice of this equation, which details how to set N-removing value in detail. Note that these registers are dual buffer.
The RFDIV value
The RFDIV value depends on the value of the LO frequency. The RFDIV value can be selected from the list of Table 6. Apply the selected RFDIV value with the LO frequency and the PFD frequency value to the equivalent 4 to calculate the correct N splitter value.
Test the input path
Reference input path is composed of reference multiplier, 5 reference frequency divisor, and division by 2 functions (see Figure 53). The frequency converter is programmed by the fifth place of the register CR10. By programming 5 digits and dividends with 2 registers CR5, Bit 4, through the register CR10, bit [4: 0]. R/2 Activalers programped 6th place through the register CR10. Note that these registers are dual -buffer.
Charging pump current
register CR9, bit [7: 4], specify the charge pump current settings. When the R value is 4.7kΩ, the maximum charge pump current is 5mA. The following formulas are applicable:
The charging pump current has 16 settings between 312.5 μA and 5mA. For the circular filter specified in the application solution, the charging pump current of 5 mAh (register CR9 [7: 4] 0xf) provides a loop bandwidth of 100 kHz. This is the recommended ring bandwidth settings.
Transmission disable control (txdis)
Transmission disable control (TXDIS) is used to disable radio frequency output. TXDIS is usually kept low. When asserting (high), it disables radio frequency output. The register CR14 is used to control which circuits are disconnected when talking about TXDIS. In order to meet the turbulent isolation power specifications and turn on/off the setting time specification at the same time, the value of 0x80 should be loaded to the register CR14. This effectively ensures that the atomer is always enabled when asserting TXDIS, even if other circuits are disabled.
Powering/up -to -power control bit
Four programmable power -on and lower -power control bits are as follows:
register CR12, bit 2. PLL's main power control position, including VCO. This bit is usually set to the default value 0 to start PLL. 
register CR28, bit 4. Control RFDIVIDER. This bit is usually set to the default value 0 to start the frequency division.
register CR27, bit 2Essence Control LO monitor output Lomon. When the monitor outputs the power off, the default value is 0. Setting this bit to 1 will power the monitor to power to one of the four options controlled by the register CR27 digit [1: 0], -6 DBM, -12 DBM, -18 DBM or -24 DBM.
register CR29, bit 0. Control the power of the positive transit device. The default value is 0, which will reduce the power of the regulator. Write a 1 in this bit to power the modulator.
Lock detection (LDET)
By setting the position of the register CR23 to 1 to enable the lock detection. Lock detection circuit is based on monitoring up/lower pulses from PFD. As the capture is carried out, the width of these pulses is reduced until they are less than the target width (set by CR23 [2]). At this time, the number of continuous PFD cycles began to count, and the width of the upward/down pulse was maintained less than the target width. When the counting reaches the target count (set up by CR13 [6] and CR23 [3]), LDET will be set. Table 7 gives the true value table that declares the LDET.
The appropriate setting to be used depends on the PFD frequency and the accuracy required when declared LDET. LDET settings do not affect the collection time of PLL. It only affects the time of LDET.
VCO automatic calibration
VCO uses automatic calibration technology to select the correct VCO and band, as described in the automatic calibration part. The register CR24, bit 0, control whether the automatic calibration is enabled. For normal operations, automatic calibration must be enabled. However, if you use 100 kHz/2 or lower cumulative frequency steps, y