Features

operation of up to 11.3 gbps

2 line digital interface

Digital input bandwidth [123 123 [123 ]

Avable distance threshold

Digital optional output voltage

Digital optional output pre -phase

adjustable input threshold voltage

low power consumption

With a chip on the back of the 50Ω back to VCC

a single 3.3V power supply

output disable

MM × 3-MM, 16 stitches, VQFN packaging in line with ROHS

Application

10D Ethernet optical receiver

4X, 8X, and 10x optical fiber channel optical receiver

SONET OC-192/SDH-64 optical receiver

SFP+and XFP transceiver module

XenPak, XPAK, X2, and 300 -pin MSA forwarder modules

cable driver and receiver

OneT8501PB device is A high -speed 3.3V limit amplifier is used for multiple fiber and copper cable applications. The data rate is from 2 GBPS to 11.3 GBPS.

The device provides a second -line serial interface that allows the bandwidth, output amplitude, output to seize phase, input threshold voltage (chip level), and signal loss assessment level for digital control. The bandwidth and service level reservation settings can also be selected by the external rate.

OneT8501PB provides a gain of about 34 decibels to ensure that the full differential output of the input signal is as low as 20 MVPP. The output amplitude can be adjusted to 350 MVPP, 650 MVPP or 850 MVPP. In order to compensate the frequency correlation loss of the micro -band line or strip line connected to the device output terminal, it includes a programmable front phase in the output level. It also provides a set of setting signal loss detection and output disable.

The device uses small size 3-mm × 3-mm that meets the ROHS standard, 16-pin VQFN packaging, usually the power consumption is less than 170mW.It is characterized by working at a temperature of -40 ° C to 100 ° C.

Equipment information

(1), please refer to the appointment appendix at the end of the data table.

Typical application circuit

pin configuration

Typical features

Unless there are other instructions, the typical working conditions are VCC u003d 3.3V, TA u003d 25 ° C, AMP1 u003d 0, AMP0 u003d 1 (register 3) and maximum bandwidth.

Overview

This compact, low power consumption, 11.3-Gbps limited amplifier amplifier is a high-speed high-speed The data channel is combined with a simulated input threshold adjustment. One uses the two peak detectors to lose detection blocks with a dual -line interface with a control logic block and a band benchmark voltage source and bias current to generate modules.

Simplified box diagrams about OneT8501PB, see the function box diagram.

Function box diagram

Function description

High -speed data path

High -speed data signal via input signal quotation via input signal quotation Foot DIN+/DIN-, is used in data paths. The data channel consists of a 100Ω differential terminal resistor and a digital control bandwidth switch input buffer for a digital control bandwidth switch for rate selection. Rate1 and Rate0 pins can be used to control the bandwidth of the filter. Use the default bandwidth settings; however, these settings can be changed by using register 4 to 7 through serial interface. For more information on the selection of rates, see Table 19. The gain level and the output buffer follow the input buffer, which provides a 34DB gain together. This device accepts input amplitude level from 5 MVPP to 2000 MVPP. The enlarged data output signal can be obtained at the output pin DOUT+and DOUT, including 2 × 50- the back terminal to VCC on the chip.

Differentiated to eliminate compensation internal offset voltage, so as to ensure that even for very small input data signals can work normally. The displacement can be disabled so that the input threshold voltage can be adjusted to optimize the code rate or change the cross -eye to compensate the input signal pulse width distortion. By setting OCDIS u003d 1 (bit 1 of register 0), the offset is disabled. You can use the register to set THADJ [0..7] (register 1) to adjust the input threshold level. For more information on the input threshold adjustment, see Table 19.

The low -frequency deadline is as low as 80 kg, and a built -in filter capacitor. rightFor applications that need to be lower -end frequency, additional external filter capacitors can be connected to COC1 and COC2 pins. The value of 330 PF causes a low frequency cutter of 10 KHz.

The production of the bandwap voltage and partial voltage

OneT8501PB limited amplifier to power supply from a single 3.3 voltage power supply connected to the VCC pin. This voltage refers to the ground (GND).

The gap voltage circuit on the film generates a reference voltage independent of the power supply voltage. From this, all other internal voltage and bias currents can be exported.

Equipment function mode

High -speed output buffer

The output amplitude of the buffer can be set by AMP [0..1] through the serial interface. 3) Set to 350 MVPP, 650 MVPP or 850 MVPP. In order to compensate the frequency correlation loss of the transmission line connected to the output terminal, the OneT8501PB has the output -level adjustable pre -phase. You can use the register to set peadj [0..3] (register 2), and set the phase to set the phase to 0 to 8dB with the stepgage of 1-DB.

Selection

There are 16 possible internal filter settings (4 digits) to adjust the small signal bandwidth to adapt to the data rate. For fast rate selection, you can use Rate1 and Rate0 pin to select 4 default values. Use serial interfaces to customize bandwidth settings instead of using the default value. The default bandwidth and the register used to change the bandwidth settings are shown in Table 1.

If the selection of the register selection is set to low, for example, RSASEL u003d 0 (7th in the register 4), the default bandwidth of the register is used. If the register selection bits are set to high, for example, RSASEL u003d 1 (7th in the register 4), when Rate0 u003d 0 and Rate1 u003d 0, the content of RSA [0..3] (register 4) is used to set input filtering Bandwidth. The setting of the register RSA, RSB, RSC, RSD, and the corresponding filter bandwidth are shown in Table 2.

If you use a serial interface, you do not have to use Rate1 and Rate0 pins. If the Rate1 is not connected, the interior is pulled up; if the Rate0 is not connected, the internal pull is low, so select the register 7. Therefore, the content of the RSD [0..3] (register 7) can be used to adjust the bandwidth through serial interface.

Signal loss detection

Signal loss detection is completed by 2 independent liquid level detectors to cover a wider dynamic range. The peak of the input signal and the output signal of the gain level is monitored by the peak detector. Peak and signal lossThe predetermined signal loss threshold voltage in the discharge block is compared. As a result of comparison, a service level signal that indicates that the input signal is lower than the specified threshold level. The level of service level assertion can be set through serial interface. Two LOS range can be set through the Lorng bit (bit 2 register 0) through the serial interface. By setting position loss u003d 1, using the high range of service level assessment (35 MVPP to 80 MVPP), the low range of the service level assessment value is used by setting bit loss u003d 0 (15 MVPP to 35 MVPP).

There are 128 possible internal service level settings (7 digits) each service level to adjust the level of service level. For fast service levels, you can use Rate1 and Rate0 pin to select 4 default values; however, you can customize the service level settings instead of using the default value. The default service level assertion level and the register used to change the service level is shown in Table 3.

If the Los register selection bit is set to low, for example, Losasel u003d 0 (the bit 7 of the register 8), then use the default Los assert level of the register. If the register selection bit is set to high, for example, losasel u003d 1 (7th in the register 8), then when Rate1 u003d 0 and Rate0 u003d 0, the contents of Losa [0..6] (register 8) are used to set service services Evergreen. If you use a serial interface, you do not have to use Rate1 and Rate0 pins. If the Rate1 is not connected, the interior is raised; if the Rate0 is not connected, the internal pull is low, so select the register 11. Therefore, the content of LOSD [0..6] (register 11) through serial interface can be used to adjust the service level assertion.

Programming

2 Line interface and control logic

OneT8501PB uses 2 -line serial interface to control digital control. For example, the two circuits input SDA and SCK are driven by serial data and serial clocks of the microcontroller, respectively. Two inputs include 100-k upper pull-up resistors to VCC. In order to drive these inputs, TIs are recommended to use open leak output.

Line interface allows writing access to the memory mapping to modify the control register and read access permissions to read control and status signals. OneT8501PB is only from the device, which means that it cannot start transmission by itself; it always depends on the availability of the SCK signal during the transmission. The main device provides clock signals and start and stop commands. The data transmission protocol is as follows:

1. Start the command;

2.7 bit from the machine address (1000100), and then the eighth bit, that is, the data direction bit (R/W). 0 means writing, 1 means reading;

3.8 -bit register address;

4.8 -bit register dataword;

5. Stop command;

About fixed -time, one8501pb is compatible with I2C. The typical timing is shown in Figure 13, and the complete data transmission is shown in Figure 14. Table 4 defines the parameters of Figure 13.

Business: SDA and SCK lines remain high.

Starting data transmission: When the SCK line is high, the status of the SDA line defines one or more start -up conditions from high levels to low levels. Each data transmission starts with a starting condition.

Stop data transmission: When the SCK line is at high electricity, the status of the SDA line defines stop conditions (P) from low to high. Each data transmission is over at a stop condition; however, if the host still wants to communicate on the bus, it can generate a repeated start -up condition and address another standing station without a primary priority.

Data transmission: Only one data byte can be transmitted between the beginning and stop conditions. The receiver confirms the data transmission.

Confirmation: Each receiving device must generate a confirmation position when the address is addressing. The sender releases the SDA cable, and during the clock pulse, the confirmed device must drop the SDA cable in this way, so that the SDA cable is stable at the low position within the high cycle of the response clock pulse. Setting and maintaining time must be considered. When the receiver does not confirm the address of the machine, the data cable must be kept at a high position. The host can then generate a stop condition to stop the transmission. If the machine receiver does confirm the address of the machine, but after a period of time during the transmission process, you cannot receive more data bytes, the host must stop the transmission. This is instructed by the instructions from the device on the subsequent first byte. From the cause of the data cable to be at a high level, the main device generates stop conditions.

Application and implementation

Note

below below The information in the application chapter is not part of the TI component specification, and the TI does not guarantee its accuracy or integrity. TI's customers are responsible for determining the applicability of the component. Customers should verify and test their design implementation to confirm the system function.

Application information

FIG. 15 shows the typical application of digital control. In this case, DIN+and DIN-are connected to cross-blocking large devices (ROSA), and Dout+and DOUT-are connected to the SFP connector. Micro -processor and SCA connection.

Typical application

FIG. 15 shows typical application circuits using OneT8501PB.

Design requirements

For this design example, the parameters listed in Table 20 are used as input parameters.

Detailed design program

The role of series resistors is to improve the signal integrity between the VCSEL driver and VCSEL. As VCSEL impedance changes with its type, the series resistor provides better matching impedance for the modulation current output.

The output amplitude adjustment is set to: AMP0 u003d 1 and AMP1 u003d 0 (see the register 3). DIN+, DIN-, DOUT+and DOUT-AC coupling with 0.1 μF.

Application curve

Power suggestion

OneT8401pb design is used in the input power supply voltage range of 2.95 V to 3.6 V Work.

For SFP+modules, one8501pb must be used because its communication co -modular voltage is low.

The power current of ONE8501PB depends on the output amplitude settings.

The typical settings of the SFP+module are 650 MVPP output voltage. In this case, the typical power supply current is 50 mAh, resulting in 165 MW.

Layout

layout guide

For high-speed transmission lines and high-performance connection cables, use 50Ω-100Ω output. The length of the transmission line must be as short as possible to reduce losses and pattern -related jitter. TI recommends separate DOUT+and DOUT-transmission cables from DIN+and DIN-transmission cables to the maximum extent to minimize the transmission of the transmitter to the string of the receiver.

layout example