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2022-09-21 17:24:28
AD7767 is 24 -bit, 8.5 MW, 109 decibels, 128 KSPS/64 KSPS/32 KSPS modulus converter
Features
Over-sampling approaching (SAR) structure High-performance DC accuracy, low power consumption; 115.5 decibel dynamic range, 32 KSPS ( AD7767 -2); 112.5 decibel dynamic dynamic dynamic dynamic dynamic dynamic dynamic dynamics Scope, 64 KSPS (AD7767-1); 109.5 decibel dynamic range, 128 KSPS (AD7767) -118 decibel THD; ultra-low power; 8.5 MW, 32 KSPS (AD7767-2); 10.5 MW, 64 KSPS (AD77677- 1); 15 mW, 128 KSPS (AD7767) high DC accuracy; 24 bits, no code (NMC); inl:? 3 PPM (typical), ± 7.6 PPM (maximum); low temperature drift; zero error drift: 15 nv/℃; gain error drift: 0.4ppm/℃; low -pass FIR filter on the tablet; linear phase response; passing ripple: ±0.005db；阻带衰减：100分贝；2.5 V电源，带1.8 V/2.5 V/3 V/3.6 V逻辑接口选项；灵活的接口选项；多设备同步；菊花链能力；断电功能；温度范围: 40 ° C to+105 ° C.
Application
Low -power PCI/USB data collection system; low power consumption wireless collection system; vibration analysis instrument; high -precision medicine collection.
General description
AD7767/AD7767-1/AD7767-2 is a high-performance, 24-bit, over-sample synthetic aperture radar modulus (ADC). AD7767/AD7767-1/AD7767-2 combines the advantages of large dynamic range and input bandwidth, consumes 15 MW, 10.5 MW and 8.5 MW, respectively, and is included in a 16-guide Tssop package.
AD7767/AD7767-1/AD7767-2 is an ideal choice for ultra-low power data collection (such as PCI and USB systems), which can provide 24-bit resolution. AD7767/AD7767-1/AD7767-2 has an excellent signal-to-noise ratio, broad dynamic range, and excellent DC accuracy, which is very suitable for measuring small signal changes in the wide dynamic range. This is especially suitable for the application of small changes in the input in the input in large communication or DC signals. In this application, AD7767/AD7767-1/AD7767-2 accurately collects communication and DC information.
AD7767/AD7767-1/AD7767-2 includes a car digital filter (with a linear phase response), which eliminates external noise by filtering an input voltage of the sample. The over -sampling architecture also reduces the requirements of front -end anti -aliasing. Other features of AD7767 include Sync/PD (synchronization/Power off the feet, allow multiple AD7767 devices to synchronize. The increase in SDI tube feet provides options for the chrysanthemum chain to connect to multiple AD7767 devices.
AD7767/AD7767-1/AD7767-2 Use a 5-volts of reference voltage to run from 2.5 volt power. The working temperature of these devices is -40 ° C to+105 ° C.
Related equipment
Absolutely absolutely Maximum rated value
T 25 ° C, unless there is another instructions.
The stress higher than the absolute maximum rated value may cause permanent damage to the device. This is just a stress rated value; the functional operations of the equipment in the operation chapter of this specification or above or any other conditions do not mean. Long -term exposure to absolute maximum rated conditions may affect equipment reliability.
Typical performance features
AV DV 2.5V ± 5%, V 1.8V ~ 3.6V, V 5V, MCLK 1MHz, co -mode input v/2. T 25 ° C, unless there is another explanation. All FFTs are generated with four Blackman-Harris windows with 8192 samples.
The term 
signal -to -noise ratio 
Total harmonic distortion (THD)
THD is the ratio of harmonic equity and the ratio of the base wave. For AD7767, it is defined as:
Among them: V1 is the average root amplitude of Kobo. V2, V3, V4, V5 and V6 are six harmonics.
The non -harmonic non -mixed dynamic range (sfdr) 
Dynamic range
The dynamic range is the ratio of the average root value of the fully standard to the average root noise measured during the input short circuit. The value of the dynamic range is expressed in decibels.
Mutual distortion
When the input consists of a sine wave of two frequencies (FA and FB), any non -linear active device will be in the harmony and difference of the MFA ± NFB Frequently produce distortion products, where M, n 0, 1, 2, 3, etc. Mutual disturbance items refer toM and N are not equal to 0. For example, second-order items include (FA+FB) and (FA-FB), third-order items include (2FA+FB), (2FA-FB), (FA+2FB), and (FA-2FB).
AD7767 uses the CCIF standard for testing, which uses two input frequencies near the top of the input bandwidth.
In this case, the second -order item is usually between the frequency of the original string, and the third -order item is usually close to the frequency of the input frequency. Therefore, the second and third -order items are specified. Mutual disturbances are based on the THD specifications, where it is the ratio of RMS of a single distortion product and the ratio of the basic principle expressed by decibels to the amplitude of the RMS amplitude.
Integral non -linearity (INL)
Inl is the maximum deviation of the straight line of the point point of the function end of the ADC.
Fortune non -linearity
DNL is the difference between the measurement value between the two adjacent codes of the ADC and the ideal 1LSB change.
Zero error
Zero error is the difference between the ideal medium -scale input voltage (when the two inputs are short) and the actual voltage of the actual scale output code in the generation.
Zero error drift
Zero error drift is a change in the actual zero error due to temperature changes by 1 ° C. It indicates the percentage of a full range at room temperature.
gain error
The first conversion (from 100 ... 000 to 100 ... 001) should occur at 1/2 LSB above the nominal liability of analog voltage.
The last conversion (from 011 ... 110 to 011 ... 111) should occur at 1.5 LSB beam below the simulation voltage. The gain error is the difference between the actual level of the last transition and the difference between the actual level of the first transition and the difference between the ideal level.
gain error drift
gain error drift is a change in the actual gain error value caused by temperature change by 1 ° C. It indicates the percentage of a full range at room temperature.
The co -mode suppression ratio
The co -mode suppression ratio refers to the ADC output power and the frequency F when the ADC output power and the frequency F are applied to the 100 MV input by V and V. The ratio of sine wave power.
Among them, PF is the power at the ADC output mid -frequency F, and PF is the power at the ADC output mid -frequency F.
Operation theory 
AD7767/AD7767-1/AD7767-2 Transmitting function
AD7767/AD7767-1/AD7767-2 The result is output in a 24-bit serial dual format. The full differential input V and V are scaled by AD7767/AD7767-1/AD7767-2 relative to the reference voltage input (VREF+), as shown in Figure 28.
Inverter operation
Internally, the input waveform applied to the SAR core is converted, and at a rate of equal to MCLK to output the equivalent numbers to the equivalent numbers to the rate Digital filter. By adopting the sampling, the quantitative noise of the converter is transmitted on the width width of 0 to F. This means that the noise energy containing a signal band in interest is reduced (see Figure 29). 
The digital filtering after the output of the converter is to remove external quantification noise (see Figure 30). This also has the effect of reducing the data from F at the F/8, F/16, or F/32 at the F/8, F/16, or F/32 of the data from the filter input, which depends on the model used.
The digital filter consists of three independent filter blocks. Figure 31 shows the three components of the filter. The extraction order of the first filter block is set to 2, 4 or 8. The remaining sections were selected for 2 people each. 
Table 6 shows the three available models of AD7767, which lists changes in the order of output data rates relative to the extraction rate. This makes the balance between additional filtering and reduced bandwidth become the focus, thereby using a filter option with a larger extraction rate to improve the noise performance while reducing the available input bandwidth.
Note that the output data rate shown in Table 6 is achieved when using the maximum MCLK input frequency of 1.024MHz. The output data rate is linearly related to the MCLK frequency, and the digital power dissipates with the frequency of MCLK.
The stable time of the filter implemented on AD7767, AD7767-1 and AD7767-2 is related to the length of the filter used. Set the stable time of the filter in the response of the filter in the time domain. Table 7 shows AD7767/AD7767-1/AD7767-2. 
Simulation input structure
AD7767/AD7767-1/AD7767-2 configuration to the differential input structure. In the analog input, VIN+and VIN-, pin 4 and pin 5, respectively. Using differential input provides inhibitors of common signals to vehicle recognition number+and vehicle recognition number-pin. 
Pay attention to ensure that the analog input signal does not exceed the regulations, refer to the power supply voltage (VREF+) greater than 0.3 V in the absolute maximum rated part. If the input voltage exceeds this limit, the diode will become positive bias and start the conduction current. The maximum can be processed by the two -polar tube.
The impedance of analog input can be modeled as a parallel 
is 10 V. The maximum input voltage.
AD7767 interface
AD7767 provides users with a flexible serial interface, and users can realize the most ideal interface application solution. The AD7767 interface includes seven different signals. Five signals are input signals: MCLK, CS, synchronous/PD, SCLK and SDI. The other two signals are output: DRDY and SDO.
Initial power
When the initial power is powered on, the application continuous MCLK signal. It is recommended to reset AD7767 to clear the filter to ensure the correct operationEssence The reset is completed, as shown in Figure 5, all events are compared to McClek compared to the rising edge. The negative pulse in the SYNC/PD input starts reset, and the DRDY output switch to the logic high and keep it high until the valid data is available. After connecting the power supply, the AD7767 takes time by converting the SSC/PD pins to the valid data of the Logic High device output. This settlement time TSettling is the MCLK frequency and extraction rate. The settlement time model of each AD7767 should be referred to when reviewing.
Reading data
AD7767 outputs its data conversion results on the serial data output tube (SDO). TWOS-Complete, 24-bit. MCLK is the main clock, controlling all AD7767 conversion. SCLK is the serial clock input of the device. All data transmission is related to the SCLK signal. 
AD7767 provides options (CS) to select the input signal using the chip in its data reading cycle. The CS signal is the door of the SDO pin, allowing many AD7767 devices to share the same serial bus. It sends to each of these devices as an instruction signal that allows the use of bus. When CS is logical, the SDO line of AD7767 is three -state.
You can start two different modes to read the data from AD7767 device: The mode of CS decrease edge appears before the DRDY decrease and CS decline may appear before the drop edge of the DRDY (when the CS is set to the logic low).
When the CS decrease, after the decrease of the DRDY decrease, the MSB of the conversion result can be descended with the CS on the SDO row. The remaining positions (MSB-1, MSB-2, etc.) of the conversion result are delayed to the SDO row to drop the edge of the SCLK along the CS decrease. Figure 3 detailed this interface scheme.
When CS is at a low level, the AD7767 serial interface can work in the 3 -line mode, as shown in Figure 4. In this case, the MSB of the conversion result is on the edge of the doctor. The remaining positions (MSB-1, MSB-2, etc.) of the data conversion result from the subsequent SCLK decline along the time to SDO.
Power off, reset and synchronization
AD7767 synchronization/PD pin allows users to synchronize multiple AD7767 devices. This pin also allows users to reset AD7767 device and turn off their power. These characteristics are implemented relative to the rising edge of MCLK, as shown in Figure 5, marked as A, B, C, and D.
To close, reset, or synchronize the device, AD7767 synchronization/PD pin should be taken low. On the first rising edge of MCLK, AD7767 was powered off. Digital pin transmission-options set to high logic, indicating that the data in the output register is no longer effective. Check the status of synchronization/PD pins on each follow -up rising along the MCLK. When the first rising along the SYNC/PD tube foot was at a high level, the AD7767 was powered off. At the next rising edge, the filter of AD7767 reset. At the upper edge of the rise, collect the first new sample.
The stable time T starting from the filter reset must output effective data at the settlement device (see Table 7). After the output is low, it becomes low to indicate when the valid data on the SDO can be read.
Chrysanthemum chain
Chrysanthemum chain equipment allows many devices to use the same digital interface line through the output of multiple ADCs in a data cable. This feature is particularly useful for Reduce-component count and wiring connection, for example, in isolation multi-converter applications or systems with limited interface capacity. Data reading is similar to the timing of the displacement register, where the data decreases along the time along the SCLK.
The box diagram in FIG. 36 shows how to connect the device to realize the chrysanthemum chain function. The plan shown is operated by transmitting the output data of the SDO tube of the AD7767 device to the SDI input of the next AD7767 device in the chain. The data then continues to pass the chain until it is on the SDO tube of the first device in the chain.
Read data in the chrysanthemum chain mode
The chrysanthemum chain of the four AD7767 devices is shown in Figure 36 and Figure 37. In the case of FIG. 36, the output of the AD7767 marked as A is the output of the complete chrysanthemum chain. The last device in the chain (AD7767 marked with D) has
its serial data input (SDI) pin ground. All the devices in the chain must use public MCLK, SCLK, CS and Sync/PD signals. To enable the chrysanthemum chain conversion process, please use the public SYNC/PD pulse to all equipment, and all equipment in the synchronous chain (see power loss, reset and synchronization).
After using the Sync/PD pulse should be used for all device, there is a delay before the output of the device chain (as listed in Table 7) before the output of the device chain. As shown in Figure 37, the first conversion result was output from the AD7767 device marked as A. After the 24 -bit conversion result, the conversion results of the devices of B, C, and D, respectively, all the conversion results are output in the first order of MSB. The conversion result circulates the timing of each device in the chain, and finally timed to the AD7767 marked AD7767 labeled APrepare SDO tube feet. The conversion result of all devices in the chain must be timely to the final device in the chain, and its DRDY signal is in a low activation state.
This is explained in the examples shown (Figure 37 and Figure 38), where the conversion results marked as the device of A, B, C, and D are A) Rising edge.
Select the frequency of SCLK
As shown in Figure 37, the number of SCLK decreased edges occurs during the low active period, and the number of devices in the chain must be multiplied by 24 (each per each The device must be matched through the number of SDO (A) clock).
Therefore, the SCLK (T) cycle required to use the known chrysanthemum chain length that is known to use the known public MCLK frequency must be determined in advance. Note that the maximum SCLK frequency is controlled by T and specified in the timing specification table of different V voltage.
If CS is limited to a logical low,
Among them: K is the number of AD7767 devices in the chain.
TSCLK is the cycle of SCLK. 
If you use CS in the chrysanthemum link interface,
Among them: K is the number of AD7767 devices in the chain.
TSCLK is the cycle of SCLK. 
Note that the maximum value of the SCLK is controlled by T8, and the voltage specifies in the timing specification table of different drivers.
Chrysanthemum chain mode configuration and time sequencing diagram
Driving the ad7767
AD7767 must be drove with a full differential input. The common mode voltage of the AD7767 device input, so the limit of the differential input is set to the reference voltage (V) setting to the device. The co -mode voltage of AD7767 is V/2. When the AD7767 V pins have 5 V power supply (using ADR445, ADR435, or ADR425), the co-mode voltage is 2.5 V. 
The analog voltage of 2.5 V is the AD7767 AV pin. However, AD7767 allows users to apply a reference voltage of up to 5 V. This provides users with a larger scale range, and provides users with options with AD7767 with a larger LSB voltage. Figure 39 shows the biggest input of AD7767.
Differential signal source 
Single-end signal source
For the application of using a single-end simulation signal (bipolar or single pole), ADA4941-1 single-end to differential driver was created to AD7767/AD7767-1/AD7767- 2 The full differential input. The schematic diagram is shown in Figure 41.
R1 and R2 set the attenuation ratio between the input range and the ADC range (V). The choice of R1, R2, and C depends on the required input resistance, signal bandwidth, anti -aliasing and noise contribution. The ratio of R2 to R1 should be equal to the ratio of REF to peak input voltage. For example, for the ± 10 v range of 4 kΩ, R2 1 kΩ, and R1 4 kΩ.
R3 and R4 set up co -mode at the input end, and R5 and R6 set up co -mode at the input terminal of ADC. The voltage when the co -mode is equal to V should be close to V/2. The current voltage should be roughly set to the ratio of V to 1+R2/R1.
AD7767/AD7767-1/AD7767-2 Sample. The car digital filter provides any possible mixed frequencies at an attenuation of any possible mixture frequency at an attenuation of any possible mixture frequency from the scope of the scope of an image of a digital filter. This occurs when the MCLK minus the filter stop belt (MCLK 0.547 × ODR), as shown in Figure 42.
Table 9 shows that before the signal enters AD7767/AD7767-1/AD7767-2, the digital filter stop belt (1.024 MHz 0.547 × ODR)) At the image, attenuation of the front -end anti -mixing filter through different steps.
AD7764 and AD7765∑-Δ device can be used by customers who need additional resistance to mixing protection. These devices perform internal sampling of the signal at a rate of 20 MM to reach an output data rate of up to 156 kg or 312 kg. This means that when running at the highest speed, the first individual names of these devices are 19.921 MM and 19.843 MMB, respectively.
Power ConsumpExcellent performance. Figure 43, Figure 44, and Figure 45 shows how the current consumption of AD7767/AD7767-1/AD7767-2 changes with the MCLK frequency applied to the device. As the frequency of MCLK decreases, the numbers and simulation currents are smaller. The actual throughput is equal to the application of the application of the application. For example, operating the AD7767 device under the 800 kHz MCLK, due to 8 times the filtering, the output data rate is 100 kHz.
VREF+input signal
AD7767/AD7767-1/AD7767-2 V pins is 2.4 V to 2 × AV (nominal 5 V). It is recommended to generate V input from the low noise voltage benchmark. These reference examples are ADR445, ADR435, ADR425 (5 V output) and ADR421 (2.5 V output). Typical reference power circuit is shown in Figure 46.Reference voltage input pin (V) is also used as a power supply for AD7767/AD7767-1/AD7767-2 device. For 5 V V inputs, 5 V can be applied on V and V, and the voltage supply of the pin AV can be maintained at 2.5 V. This configuration reduces the number of different supply required.
The output of the low noise voltage benchmark does not require a buffer; however, the output of separation of low noise benchmark is important. Place a 0.1 μF capacitor at the output end of the voltage reference device (ADR445, ADR435, ADR425, and ADR421, and follow the decoupling advisory provided by the selected reference device.
As mentioned earlier, the nominal power supply of the V pins is 5 V to achieve the available full dynamic range. When using 2.5 V V input (that is, in low -power applications), the signal tone ratio and dynamic range chart (generate 5 V generated VInput) in the Specifications section decrease result. 
Multi-Lu Simulation Input Channel
AD7767/AD7767-1/AD7767-2 can be used with multi-way relics configuration. Filter according to digital filterAny converter in the wave block, the maximum switching rate of each channel or the output data rate is a function of the stable time of the digital filter.
Users who enable input multiplexes to converters using digital filters must wait for the setting time of the full digital filter to get effective conversion results; after this setting time, the channel can be switched. Then, before the effective conversion result can be used and switching input again, it must be observed completely stable time.
The stability time of AD7767 filter is equal to 74 divided by the output data rate that is being used. Therefore, the maximum switching frequency in multi -way reuse applications is 1/(74/ODR), where the output data rate (ODR) is the function of the application of the MCLK frequency and the extraction rate of the device. For example, the use of 1.024MHz MCLK frequency to AD7767 will generate a maximum output data rate of 128kHz, which allows 1.729kHz to switch rate of 1.729kHz.
AD7767-1 and AD7767-2 use digital filters with longer stable time to obtain higher accuracy; therefore, the maximum switching frequencies of these devices are 864 Hz and 432 Hz, respectively. 
[1] The dynamic range of the maximum output data rate.
[2] Specifications are suitable for all devices, AD7767, AD7767-1, and AD7767-2. See the term part.
[3] The transient current with a height of 100 mAh will not cause the crystal tube to be atresia.