Abstract

High -performance 32 -bit/40 -bit floating -point processor; optimized for high -performance audio processing; segmentation level code compatibility, use the same instruction set as other Sharc DSP; Treatment of high-performance audio and enable low performance at the same time; system cost; audio decoder and post-processor algorithm support; can be configured to contain PCM 96 kHz, Dolby numerals, Dolby numbers; DTS-ES matrix 6.1, DTS, 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA Pro V7.1, Dolby Pro Logic II, Dolby Pro Logic 2X, DTS Neo: 6 different multi-channel multi-channel The surround sound decoder is included in ROM. For the configuration of the decoder algorithm, see Table 3 on page 4; single instruction Multi -data (SIMD) computing architecture Two 32 -bit IEEE floating point/32 -bit fixed point/40 -digit extended accuracy floating point calculation unit, each unit, each unit There are a multiplier, ALU, displacement, and register file; high bandwidth I/O -a parallel port, a SPI port, 6 serial port; port, digital application interface (DAI) and JTAG; DAI contains two two Precision clock generator (PCG), an input data port (IDP), including a parallel data collection port (PDAP) and 3 programmable timers; software control of signal route unit (SRU); SRAM and a DEDI-processed 4 megenic film covering the model programming ROM; ADSP-2126X processor offers 150 MM or the core instruction rate of 200 Mixh. For full order, please refer to the ordering guide on page 45.

Sharc and Sharc logo are registered trademarks of Analog Devices, Inc.

General description

adsp-21261 / adsp-21262 / adsp-21266 sharc dsp is simd Members of the Sharc series DSP, with analog equipment company and super Harvard architecture. ADSP-2126X source code and ADSP-21160 and ADSP-21161 DSP, as well as the first-generation ADSP2106X Sharc processor are compatible with SISD (single instruction, single data) mode. Like other Sharc DSP, ADSP-2126X is a 32-bit/40 floating-point processor, which is optimized for high-performance audio applications. It has multiple internal bus and mask programming ROM, eliminating I/O bottlenecks and eliminating I/O bottlenecks. Innovative digital application interface.

Table 1 shows the performance benchmark running in the 200MHz processor. Table 2 shows the characteristics of each product.

As shown in the functional frame diagram in Figure 1 in Figure 1, A DSP-2126X uses two calculation units, which is compared with the previous SHARC processor on a series of DSP algorithms. Performance is increased by 5 to 10 times. ADSP-2126XDSPS uses an advanced high-speed CMOS process. At 200MHz, the instruction cycle is 5NS, and the instruction cycle of 150MHz is 6.6ns. Use SIMD to calculate the hardware, ADSP-2126X can run 1200 MFLOPS at 200MHz, or run 900 MFLOPS at 150MHz.

ADSP-2126X continues the Sharc family's industry leading standards in DSP integration, combining high-performance 32-bit DSP kernel with integrated film system functions. These functions include 2 mega dual -port SRAM memory, 4 mega dual -port ROM, I/O processor supporting 22 DMA channels, 6 serial ports, SPI interfaces, external parallel bus and digital application interface.

ADSP-2126X's box diagram on page 1 explains the following architecture features:

each of which contains one ALU, Multi-PLIER, displacement and shift, and Data register file

data address generator (DAG1, DAG2)

The DM bus can support the four 32 -bit data transmission between the memory and the core of each core processor. Features, pulse capture/pulse width measurement and external event counter function

Double port SRAM on the film (up to 2 meters)

Moder programming only reads the memory (up to 4 megs)

JTAG test access port

Parallel port

DMA controller

six full dual-work serial ports (four on ADSP-21261)

# 8226; SPI compatible interface

Digital application interface, including two precision clock generators (PCG), one input data port (IDP), six serial ports, eight serial seriesThe interface, a 20 -bit synchronous parallel input port, ten interrupts, six logo output, six logo inputs, three programmable timers, and a flexible signal route unit (SRU)

The core architecture of the family [ 123]

ADSP-2126X is compatible with ADSP-2136X and ADSP-2116X and the first generation of ADSP-2106X Sharc DSP. ADSP-2126X and ADSP-2136X and ADSP-2116X SIMD Sharc series DSP sharing architecture functions, see the following chapters for details.

SIMD calculation engine

ADSP-2126X contains two computing processing elements, which run as a single instruction multiple data (SIMD) engine. The processing element is called PEX and PEY, and each element contains an alu, multiplier, displacement and register file. PEX is always active, and PEY can be enabled by setting the PEYEN mode bit in the Mode1 register. When this mode is enabled, the same instructions are performed in the two processing elements, but each processing element operates different data. This architecture is very effective when performing mathematical dense audio algorithms.

Entering the SIMD mode also affects the method of transmitting data between memory and processing components. In the SIMD mode, you need to double the data bandwidth to maintain the calculation operation in the processing unit. Due to this requirement, entering the SIMD mode will also double the bandwidth between memory and processing elements. When using Dags to transmit data in SIMD mode, two data values are transmitted every time you access the memory or register file.

Independent parallel computing unit

There is a set of computing units in each processing unit.

Calculating units include arithmetic/logic units (ALU), multiplication and displacement. These units perform all operations within a cycle. The three units in each processing unit are arranged in parallel to maximize the calculation throughput. A single multifunctional instruction executes parallel operation unit and multiplier operation. In the SIMD mode, the operation of the parallel ALU and the multiplier occurs at the same time in two processing units. These computing units support the IEEE 32 -bit single -precision floating point, 40 -bit extension accuracy floating point, and 32 -bit fixed -point data format.

Data register file

The general data register file is included in each processing element. The register file transmits data between the calculation unit and the data bus, and stores the intermediate result. These 10 ports, 32 registers (16 main registers, 16 secondary registers) register files, combined with the ADSP-2126X enhanced Harvard architecture, allowing the calculated data flow between the calculation units and internal memory. The register in PEX is called R0–R15, and the register in PEY is called S0 -S15.

Instructions and four operations single cycles obtain

ADSP-2126X adopt an enhanced Harvard architecture, where data memory (DM) bus transmission data, program memory (PM) bus transmission instruction and data (See page 1 Figure 1). Using ADSP-2126X's independent programs and data storage bus and instruction cache on the film, the processor can obtain four operations (two operations of each data bus) and one instruction (from the cache) within one cycle.

The instruction cache

ADSP-2126X includes a high-speed cache on the board, so that the three bus operations can obtain one instruction and four data values. The cache is selective, only the instructions for obtaining the data access conflict with the PM bus. The cache allows full -speed execution of core, circulating operations (such as digital filter multiplication) and FFT butterfly treatment.

Data address generator supports zero-expense hardware circulating buffer

Two data address generators (DAG) of ADSP-2126X for indirect addressing and realizing cyclic data buffer in the hardware Area. The circular buffer allows other data structures required for effective programming delay lines and digital signal processing, which is usually used for digital filter and Fourier transformation. The two DAGs of ADSP-2126X contain sufficient registers, which can create up to 32 cyclic buffer (16 main registers and 16 registers). DAG automatically processes the surrounding address pointer to reduce expenses, improve performance, and simplify implementation. The circulating buffer can start and end at any memory position.

Flexible instruction set

48 -bit instructions can accommodate various parallel operations to achieve simple programming. For example, ADSP-2126X can perform the multiplication, addition and subtraction of the two processing elements, and at the same time branch and extract up to four 32-bit values from the memory in a instruction.

Memory and I/O interface functions

ADSP-2126X adds the following architecture function to the core of the SIMD Sharc series:

Double-end portal memory

ADSP -21262 and ADSP-21266 contain 2 trillion internal SRAM and 4 mega-level internal mask programming ROM. ADSP-21261 contains 1 mega-level internal SRAM and 3 mega-level internal mask programming ROM. Each block can be configured as different code and data storage combinations (see memory diagrams, Table 4 and Table 5). Each memory block is dual -port, and the core processor and I/O processor are interviewed by single -cycle. The two -terminal memory combined with three independent films on the bus, allowing two data from the core and I/O processor within a cycle.

ADSP-2126X can provide a variety of multi-channel surround sound decoders, in ROM memoryPre -program. Table 3 shows the configuration of the code device algorithm.

SRAM of ADSP-2126X can be configured to be configured with 32-bit data with a maximum of 64K, 16-bit data of 128K characters, 48-bit instructions (or 40 digits of data) of 42K characters (or 40 digits) Or the combination of different font size can reach a maximum of 2 trillion. All memory can be accessed as 16 -bit, 32 -bit, 48 -bit or 64 -bit words. Support 16 -bit floating -point storage format, which effectively doubles the amount of data that can be stored on the chip. The conversion between 32 -bit floating point and 16 -bit floating -point format is executed in a instruction. Although each storage block can store the combination of code and data, when one block uses DM bus storage data for transmission, and the other blocks use the PM bus storage instruction and data for transmission, the access efficiency is the highest.

With DM bus and PM bus, each memory block has a dedicated bus to ensure the single cycle execution of the two data transmission. In this case, the instruction must be available in the cache.

DMA controller

ADSP-2126X on the DMA controller allows zero-expense data to transmit without processor intervention. The DMA controller operates independently and invisible to the processor's core, allowing DMA operations when the core is performed at the same time. DMA transmission can occur between ADSP-2126X's internal memory and its serial port, SPI compatibility (serial peripheral interface) port, IDP (input data port), parallel data collection port (PDAP), or parallel port. ADSP-2126X-One can provide up to 22 DMA channels for SPI interfaces, 12 through serial ports, 8 parallel ports that pass through the data port, and a parallel port of the processor. You can use DMA transmission to download the program to ADSP-2126X. Other DMA functions include a DMA chain generated by DMA transmission, and the DMA chain used to automatically link DMA transmission.

Digital Application Interface (DAI)

Digital application interface can connect various peripherals to any DAI pin (DAI_P20–1) of Sharc DSP (DAI_P20–1) Essence Use the signal routing unit (SRU, as shown in the box 1 square graph) to connect.

SRU is a matrix routing unit (or multi -road repeat device group), which enables the peripheral device provided by DAI to be connected under software control. This enables a set of algorithms with larger signal paths than unopened, which can easily use DAI -related peripheral devices in a wider range of applications.

DAI also includes six serial ports, two precision clock generators (PCG), one input data port (IDP), six logo output and six logo inputs, and three timers. IDP mentionThe additional input path for ADSP-2126X core can be configured to be configured to eight I2S or serial data channels, or seven channels plus a 20-bit wide synchronous parallel data collection port. Each data channel has its own DMA channel, which is independent of the serial port of ADSP-2126X.

For complete information about using DAI, see ADSP-2126X Sharc DSP peripheral manual.

Serial port

ADSP-2126X has six full-double synchronous serial ports, which are various numbers and mixed signal peripheral devices (such as analog device AD183X series audio compilation decoder, ADC ADC Provide cheap interfaces with DAC). The serial port consists of two data cables, one clock and frame synchronization. The data cable can be programmed to send or receive, and each data cable has its own DMA channel.

The serial port is enabled through 12 programmable and receiving or sending pipe footsteps at the same time. When all 6 movements are enabled, these pipes support up to 24 audio data transmission or 24 receiving channels, or each time, or each time, or each time, or each time, or each time, or each time, or each time, or each time, or every time, or each time, or each time, or every time, or each, it 6 full -duplex TDM streams of 128 channels.

The operating rate of the serial port is as high as a quarter of the DSP core clock rate. The maximum data rate provided for each port is: 200MHz core is 50m bit/second, and the core of 150MHz is 37.5m. Essence The serial port data can be automatically transmitted between the memory through a dedicated DMA. Each serial port can work with another serial port to provide TDM support. One movement provides two transmitting signals, and the other moves two receiving signals. Frame synchronization and clock are shared. The serial port work in four modes:

standard digital signal processor serial mode

Multi -channel (TDM) mode

I2S mode

Left -to -alternate pair mode

Left alignment sampling mode is in each frame synchronization cycle, send/receive two data sample patterns in each frame synchronization cycle One sample is located at the high section of the frame synchronization, and the other sample is at the low section of the frame synchronization. The program can control the various attributes of this model.

Each serial port supports the sampling pair of left -alignment and I2S protocol (I2S is an industry standard interface commonly used by audio code decoder, ADC and DAC). The port allows four left -aligned sample pairs or I2S channels (using two stereo sound equipment), up to 24 audio channels. The serial port allows small -term or large -end transmission formats from 3 to 32 -bit. For the sample pairs of the left pair and I2S mode, the length of the data word can be selected between 8 and 32 bits. The serial port provides optional synchronization and transmission mode, and optional ∏ based on each channelLaw or A rhythm of pressure expansion. The serial port clock and frame synchronization can be generated inside or outside.

Serial peripheral (compatible) interface

Serial peripheral interface is an industrial standard synchronous serial link, which enables the ADSP-2126X SPI compatibility port to communicate with other SPI compatible devices. SPI is an interface consisting of two data tube, one device choice tube and a clock tube foot. It is a full -duplex synchronous serial interface, which supports the main mode and the pattern. The SPI port can run in multiple main environments, and it can be connected to as many as four other SPI compatible devices (as the main device or from the device). The ADSP-2126X SPI compatible peripheral also has a programmable baud rate. The baud rate of the 200 MHz core clock is as high as 50 MHz, and the baud rate of the 150 MHz core clock is as high as 37.5 MHz, and the clock phase and polarity. The ADSP-2126X SPI compatibility port uses an open leak driver to support multi-host configuration and avoid data fighting.

Parallel port

The parallel port provides interfaces with SRAM and peripheral devices. Multi -way address and data tube foot (AD15–0) can access 8 -bit devices with a maximum of 24 -bit addresses, or 16 -bit devices with a maximum of 16 -bit address. In the 8 -bit or 16 -bit mode, the maximum data transmission rate is one -third of the core clock speed. For example, the clock rate of 200 MI is equal to 66 mega bytes/second, and the clock rate of 150 trillion clock is equal to 50 mega bytes/second.

DMA transmission is used to move data back and forth in memory. The assistant can also easily access the core -lel port register read/write function. RD, WR, and ALE (address lock -on) foot are the control pin of parallel port.

timer

ADSP-2126X has four timers: one core timer that can generate periodic software interruption, and three periods that can generate periodic interruptions and set them independently to three types in three types Universal timer for work under one mode:

pulse wave shape generation mode

pulse width count/capture mode

external external Event surveillance program mode

The core timer can be configured to use FLAG3 as an expired output signal of the timer, and each general timer has a two -way tube foot and four registers that implement its operation mode: 6 digits Configure register, 32 -bit count register, 32 -bit cycle register and 32 -bit pulse width register. A separate control and state register independently enable or disable all three general timers.

Based on ROM-based

ADSP-2126X has ROM security functions. By preventing unauthorized reading internal code (when enabled)For hardware support. When using this function, DSP does not guide any external code, and is executed only from the inside SRAM/ROM. In addition, it is impossible to freely access DSP through the JTAG port. Instead, the only 64 -bit key scanned through the JTAG or test access ports will be assigned to each customer. The device will ignore the wrong key. Only after scanning the correct key can the simulation function and external guidance mode are available.

Program activation

internal memory of ADSP-2126X at the system of parallel port, SPI device, SPI device or internal guidance from 8-bit EPROM when the system is powered on. The guidance is determined by the guidance configuration (boot_cfg1–0) foot.

Locking Ring

ADSP-2126X uses the lock ring (PLL) to generate the core clock. When power is powered, the CLK U CFG1–0 pin is used to select the ratio of 16: 1, 8: 1, and 3: 1. After starting, you can choose many other ratio through software control. The ratio of the ratio of 1 to 64 is composed of a molecular value and a software with 2, 4, 8, and 16.

Power supply

ADSP-2126X has an independent internal (VDDint), external (VDDEXT) and analog (AVDD/AVSS) power connection. Internal and simulated power supply must meet the requirements of 1.2V. The external power supply must meet the requirements of 3.3V. All external power pins must be connected to the same power supply.

Note that the simulation power quotation (AVDD) is powered by the internal clock generator PLL of ADSP-2126X. In order to generate a stable clock, it is recommended that PCB design uses an external filter circuit with AVDD pins. Tarze the filter component as close to the AVDD/AVSS pin. For example, please refer to Figure 2. (The recommended iron oxygen chip is Murata

BLM18AG102

SN1D). To reduce noise coupling, the printing circuit board should use a parallel parallel power supply and ground plane VDDINT and GND. Use a wide recorder to connect the bypass container to the analog power supply (AVDD) and ground (AVSS) pin. Please note that the AVDD and AVSS pins specified in Figure 2 are the input of the processor, not the analog ground plane-AVSS pin on the board should directly connect to the digital ground (GND) on the chip.

The target board JTAG simulator connector

The simulation device DSP tool product line of the JTAG simulation device uses ADSP-2126X processor IEEE during the simulation process. 1149.1JTAG test access port monitoring the target board processor. The DSP tool product line of the JTAG simulation device provides the simulation of the speed of the whole processor, allowing inspection and modification of memory, and sendingStock and processor stack. The processor's JTAG interface ensures that the simulator does not affect the target system loading or timing.

For the complete information about the SHARC DSP tool product line of the JTAG simulator operation, please refer to the corresponding simulator hardware user guide.

Development Tool

The simulation device supports its processor through a set of software and hardware development tools, including the integrated development environment (including CrossCore Embedded Studio and/or Visualdsp ++), evaluated products, simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulator and simulate device and simulator. Various software plugins.

Integrated development environment (IDE)

For C/C ++ software writing and editing, code generation and debugging support, the simulation device provides two IDEs.

The latest Ide Crosscore Embedded Studio is based on the Eclipse framework. It supports most analog device processor series, which is the preferred IDE of future processors (including multi -core devices). CrossCore Embedded Studio seamlessly integrates available software plug -in to support real -time operating systems, file systems, TCP/IP stacks, USB stacks, algorithm software modules, and evaluation hardware board support packages. For more information, visit/ccess. Trademark

Other analog devices IDE, VisualDSP ++, supports CrossCore embedded Studio's processor series before release. The IDE includes an analog device VDK real -time operating system and an open source TCP/IP protocol stack. For more information, visit/Visualdsp. Please note that VisualDSP ++ will not support future analog device processors.

EZ-Kit Lite evaluation board

For the processor assessment, the simulation device provides a wide range of EZ-Kit Lite evaluation boards. Including processors and key peripherals, the evaluation board also supports evaluation and development functions such as simulation capabilities on the film. Various EZ extensors are also provided, which are sub -cards that provide additional special features, including audio and video processing. For more information, please access and search for Ezkit " or "EZEXTENDER ".

EZ-KIT LITE evaluation kit

In a more economical and effective way